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The PSC2 internal interrupt expansion consists of a maskable inter-
rupt source register (ISR), which is the source of interface OR-com-
posed from each interrupt input, interrupt mask register (IMR) control-
ling the mask control , status read level register (SRL) reading the
status of input which is not masked, status read register (SRR) read-
ing edges, and status clear register (SCR) generating edges for the
next interrupt.

IBM-PC’s 8259 is programmed based on rising edges and incor-
porates edge generators on the rear step of each interrupt handling of
level input. Edges are generated based on the output of OR-composi-
tion when performing dummy writing to the SCR.

The steps generating an edge for general interrupts are as follows:

1) Read the ISR.

2) Check the factor of interrupt.

3) Perform the handling of interrupt for each factor.

4) Write clear the corresponding SCR bit to generate the following

edge.

Read in interrupt disable state and clear the corresponding bit to
"1" to write.

5) Return from the interrupt handling.

12-3-3. RS232 Interface

2 UARTs (8250) for RS232 are incorporated in the PSC2 as a Mega
Macro Function. UART1 and 2 are decoded as follows by the setting
of bit 7 of the SSR0 register.

Bit 7: CMOS (decode control of UART1 and 2)

SW7=1: DOS compatible COM3/COM4 mode (initial value)

COM3: 3E8H to 3EFH (8-byte address)
COM4: 2E8H to 2EFH (8-byte address)

SW7=0: Unique decode mode

Unique: PSC2+410H (16-byte address)

i.e. UART1 unit: PSC2+(410-417H)

UART2 unit: PSC2+(418-41FH)

The assignment of interrupt can be freely defined using system SW6
of special system register 0 and the assign register.

The hardware configuration conforms to the RS232 of AT specifica-
tions.

12-3-4. Drawer Interface

The I/O port driving the drawer solenoid is composed of the internal
gates of PSC2.

When power off (ACL signal = "0") is detected, each output port is
preset and the driving of the drawer solenoid is immediately stopped.
The driving time of the drawer solenoid is automatically set to 45ms
by the hardware timer control after turning each drive port ON.

12-3-5. CKDC Interface

As previously defined, the CKDC interface, is 2 sets of 8-bit serial
interface is incorporated in the PSC2. This interface is composed of
an 8-bit parallel-in/parallel-out shift register and a SCKF register for
generating shift clock. Also CKDCRES1/2 signals (reset of CKDC)
and SHEN1/2# signals (shift enable signal) must be prepared as
CKDC interface. However SHEN1/2# are used in the PSC2 as dedi-
cated signal pins inputting interrupt events.

SCKF is outputted to SCK pin without the logic changed and preset to
"1" by RESET. The serial data is in the form of LSB first. SCKF
operates with synchronized with SCK, and the operation speed
depends on the speed of CPU because the shift operation needs to
clear and set SCKF by software control for each bit.

STH is shifted in by the rising of SCK, and shifted out by the falling of
SCK. The shift-in and shift-out have a margin to the delay of line
because of 1/2 bit of phase difference.

12-3-6. Timer Counter

The PSC2 incorporates 2 8-bit hardware free run counters necessary
to control dedicated devices. This 8-bit counter can be read or written
as TCNT register 0 and 1, counted up by input clock. This input clock
is selected using CLOCK SELECT (2 bits respectively) of the TCR
register. When TCNT0 is equal to the value of timer compare con-
stant register (TCC0), compare match signal can be generated and a
maskable interrupt can be generated. Also when TCNT1 is equal to
TCC1, compare match signal can be generated and a maskable
interrupt can be generated. When the TCNT0 overflows, an overflow
signal can be generated and a maskable interrupt can be generated.

Types of internal timer interrupt

IS14: TINT0# (timer compare match interrupt 0)

IS13: TINT1# (timer compare match interrupt 1)

IS12: TOINT# (timer overflow interrupt)

12-3-7. MCR Interface

This interface has 2 channels containing 96 bytes of FIFO respective-
ly. Read data are stored in the FIFO. Each channel functions inde-
pendently, so the 2 channels can be read simultaneously.

Description of Read Operation

1) The MCR interface goes into the status of waiting for reading a

card after the following settings are performed by the main CPU.

•

Setting a mode: Sets a mode corresponding to the standard of
the handled card (JBA/ABA/IATA).

•

Setting a start mark: Sets a start mark corresponding to the
standard of the card.

•

Resetting the interrupt: Resets the interrupt because no card
can be read when any interrupt is active.

INT EVENT

IMR

SRL