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8-3. Pin description
8-3-1. CPU Interface Signals Set
Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
Host Data Bus
HD[63:0]
Refer to
Table 3-2
I/O
(4mA)
Host Data Bus Lines 63 through 0: Provides a 64-bit data path to
the CPU.
CPU Address
HA[31:3]
Refer to
Table 3-2
I/O
(4mA)
Host Address Bus Lines 31 through 3: HA[31:3] are the address
lines of the CPU bus. HA[31:3] are connected to CPU lines A[31:3].
Along with the byte enable signals, HA[31:3] define the physical area
of memory or I/O being accessed.
During CPU cycles, the HA[31:3] lines are inputs. They are used for
address decoding and second level cache tag lookup sequences.
During inquire cycles, the HA[31:5] lines are outputs to the CPU to
snoop the first level cache tags. They also are outputs to the L2
cache.
BE[7:0]#
V4:V1,
W4:W1
I
Byte Enables 7 through 0: Selects the active byte lanes on
HD[63:0].
NMI
AD5
O
(4mA)
Non-Maskable Interrupt: This signal is activated when a parity error
from a local memory read is detected or when the IOCHK# signal
from the ISA bus is asserted and the corresponding control bit in Port
B is also enabled.
Strap option
pin, refer to
Table 3-7
INTR
AF5
O
(4mA)
Interrupt Request: INTR is driven to signal the CPU that an interrupt
request is pending and needs to be serviced. The interrupt controller
must be programmed following a reset to ensure that INTR is at a
known state.
Strap option
pin, refer to
Table 3-7
FERR#
T1
I
Floating Point Coprocessor Error: This input causes two
operations to occur. IRQ13 is triggered and IGERR# is enabled. An
I/O write to Port F0h will set IGERR# low when FERR# is low.
IGERR#
AC6
I/O
(4mA)
Ignore Coprocessor Error: Normally high, IGERR# will go low after
FERR# goes low and an I/O write to Port 0F0h occurs. When FERR#
goes high, IGERR# is driven high.
Strap option
pin, refer to
Table 3-7
CPU Control/Status
CPUINIT
AD6
O
CPU Initialize: a shutdown cycle or a low-to-high transition of I/O
Port 092h bit 0 will trigger CPUINIT. If keyboard emulation is enabled
(default), a CPUINIT will be generated when a Port 064h write cycle
with data FEh is decoded. If keyboard emulation has been disabled,
then this signal will be triggered when it sees the KBRST from the
keyboard.
M/IO#
Y5
I
Memory/Input-Output: M/IO#, D/C#, and W/R# define CPU bus
cycles. Interrupt acknowledge cycles are forwarded to the PCI bus as
PCI interrupt acknowledge cycles. All I/O cycles and any memory
cycles that are not directed to memory controlled by the DRAM
interface are forwarded to PCI.
D/C#
T3
I
Data/Control: D/C#, M/IO#, and W/R# define CPU bus cycles. (See
M/IO# definition above.)
W/R#
AA5
I/O
(4mA)
Cycle
Multiplexed
Write/Read: W/R#, D/C#, and M/IO# define CPU bus cycles. (See
M/IO# definition above.)
INV
O
(4mA)
Invalidate: Pin AA5 also serves as an output signal and is used as
INV for L1 cache during an inquire cycle.
ADS3
V5
I
Address Strobe: The CPU asserts ADS# to indicate that a new bus
cycle is beginning. ADS# is driven active in the same clock as the
address, byte enables, and cycle definition signals.
ADS# has an internal pull-up resistor that is disabled when the
system is in the Suspend mode.
BRDY#
U5
O
(4mA)
Burst Ready: BRDY# indicates that the system has responded in
one of three ways:
1) Valid data has been placed on the CPU data bus in response to a
read,
2) CPU write data has been accepted by the system, or
3) the system has responded to a special cycle.
5 – 12
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