Terasic ALTERA VEEK-MT User Manual Download

Page: 1 / 48

Summary of Contents for ALTERA VEEK-MT

Page 1: ...1 ...

Page 2: ...14 3 4 Using 5 megapixel Digital Image Sensor 16 3 5 Using the Digital Accelerometer 17 3 6 Using the Ambient Light Sensor 17 3 7 Using Terasic Multi touch IP 18 CHAPTER 4 VEEK MT DEMONSTRATIONS 20 4 1 System Requirements 20 4 2 Factory Configuration 20 4 3 Painter Demonstration 21 4 4 Picture Viewer 25 4 5 Video and Image Processing 27 4 6 Camera Application 30 4 7 Video and Image Processing for ...

Page 3: ...2 5 3 Application Selector Details 40 5 4 Restoring the Factory Image 42 CHAPTER 6 APPENDIX 45 6 1 Revision History 45 6 2 Copyright Statement 45 ...

Page 4: ...accelerometer make up the rich feature set The VEEK MT is preconfigured with an FPGA hardware reference design including several ready to run demonstration applications stored on the provided SD card Software developers can use these reference designs as their platform to quickly architect develop and build complex embedded systems By simply scrolling through the demos of your choice on the LCD to...

Page 5: ...ory o 4 PLLs Configuration o On board USB Blaster circuitry o JTAG and AS mode configuration supported o EPCS64 serial configuration device Memory Devices o 128MB SDRAM o 2MB SRAM o 8MB Flash with 8 bit mode o 32Kb EEPROM Switches and Indicators o 18 switches and 4 push buttons o 18 red and 9 green LEDs o Eight 7 segment displays Audio o 24 bit encoder decoder CODEC o 3 5mm line in line out and mi...

Page 6: ...o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V VGA out Connector o VGA DAC high speed triple DACs DB9 Serial Connector o RS232 port with flow control PS 2 Connector o PS 2 connector for connecting a PS2 mouse or keyboard TV in Connector o TV decoder NTSC PAL SECAM Remote Control o Infrared receiver module Power o 12V DC input o Switching and step down regulators LM3150MH Capacitive L...

Page 7: ...de to take frames on demand Horizontal and vertical mirror image Column and row skip modes to reduce image size without reducing field of view Column and row binning modes to improve image quality when resizing Simple two wire serial interface Programmable controls gain frame rate frame size exposure Table 1 2 shows the key parameters of the CMOS sensor Note Table 1 2 Key Performance Parameters of...

Page 8: ... user defined upper and lower threshold settings 16 bit digital output with I2 C fast mode at 400 kHz Programmable analog gain and integration time 50 60 Hz lighting ripple rejection Note for more detailed information of the LCD touch panel and CMOS sensor module please refer to their datasheets respectively 1 1 1 1 About the Kit About the Kit The kit includes everything users need to run the demo...

Page 9: ...CD License license_multi_touch dat There are two ways to install the license The first one is to add the license file license_multi_touch dat to the License file listed in Quartus II as shown in Figure 1 3 In order to reach this window please navigate through to Quartus II Æ Tools Æ License Setup Figure 1 3 License Setup The second way is to add license content to the existing license file The pro...

Page 10: ...at the end of your Quartus II license file Note Do not delete any FEATURE lines from the Quartus II license file Doing so will result in an unusable license file 4 Save the Quartus II license file 7 1 3 1 3 Getting Help Getting Help Here is information of how to get help if you encounter any problem Terasic Technologies Tel 886 3 550 8800 Email support terasic com ...

Page 11: ...h VEEK MT including block diagram and components 8 2 1 2 1 Layout and Components Layout and Components The picture of the VEEK MT is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components Figure 2 1 VEEK MT PCB and Component Diagram Top ...

Page 12: ...lock Diagram of the VEEK MT Figure 2 3 gives the block diagram of the VEEK MT board To provide maximum flexibility for the user all connections are made through the Cyclone IV E FPGA device Thus the user can configure the FPGA to implement any system design Figure 2 3 Block Diagram of VEEK MT ...

Page 13: ...plied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS64 serial configuration device It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the VEEK MT is turned off When th...

Page 14: ... FPGA perform the following steps Ensure that power is applied to the VEEK MT Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the RUN position See Figure 3 4 Connect the supplied USB cable to the USB Blaster port on the VEEK MT The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename...

Page 15: ...le to the USB Blaster port on the VEEK MT Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the PROG position The EPCS64 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and ...

Page 16: ...tion The bus controller provides level shifting functionality from 2 5V HSMC to 3 3V domains Block Diagram of the Bus Controller Figure 3 6 gives the block diagram of the connection setup from the HSMC connector to the bus controller on the Max II EPM240 to the touch screen module To provide maximum flexibility for the user all connections are established through the HSMC connector Thus the user c...

Page 17: ...ble 3 1 Table 3 2 gives the pin assignment information of the LCD touch panel Table 3 1 LCD timing specifications ITEM SYMBOL MIN TYP MAX UNIT NOTE Dot Clock 1 tCLK 33 MHZ DCLK DCLK pulse duty Tcwh 40 50 60 Setup time Tesu 8 ns Hold time Tehd 8 ns Horizontal period tH 1056 tCLK Horizontal Valid tHA 800 tCLK Horizontal Blank tHB 256 tCLK Vertical Period tV 525 tH Vertical Valid tVA 480 tH DE Vertic...

Page 18: ...0 P26 LCD green data bus bit 0 2 5V LCD_G1 P25 LCD green data bus bit 1 2 5V LCD_G2 N26 LCD green data bus bit 2 2 5V LCD_G3 N25 LCD green data bus bit 3 2 5V LCD_G4 L22 LCD green data bus bit 4 2 5V LCD_G5 L21 LCD green data bus bit 5 2 5V LCD_G6 U26 LCD green data bus bit 6 2 5V LCD_G7 U25 LCD green data bus bit 7 2 5V LCD_HSD U22 Horizontal sync input 2 5V LCD_MODE L24 DE SYNC mode select 2 5V ...

Page 19: ...s and other parameters Table 3 3 contains the pin names and descriptions of the image sensor module Table 3 3 Pin Assignment of the CMOS Sensor Signal Name FPGA Pin No Description I O Standard CAMERA_PIXCLK J27 Pixel clock 2 5V CAMERA_D0 F24 Pixel data bit 0 2 5V CAMERA_D1 F25 Pixel data bit 1 2 5V CAMERA_D2 D26 Pixel data bit 2 2 5V CAMERA_D3 C27 Pixel data bit 3 2 5V CAMERA_D4 F26 Pixel data bit...

Page 20: ...GSENSOR_ALT_ADDR K27 I2C Address Select 2 5V GSENSOR_SDA_SDI_SDIO K28 Serial Data 2 5V GSENSOR_SCL_SCLK M27 Serial Communications Clock 2 5V 3 6 3 6 Using the Ambient Light Sensor Using the Ambient Light Sensor The APDS 9300 is a low voltage digital ambient light sensor that converts light intensity to digital signal output capable of direct I2C communication Each device consists of one broadband ...

Page 21: ...ould be connected of the TOUCH_INT_n TOUCH_I2C_SCL and TOUCH_I2C_SDA signals in the 2x20 GPIO header respectively When oREADY rises it means there is touch activity and associated information is given in the oREG_X1 oREG_Y1 oREG_X2 oREG_Y2 oREG_TOUCH_COUNT and oREG_GESTURE pins For the control application when touch activity occurs it should check whether the value of oREG_GESTURE matched a pre de...

Page 22: ...7 Table 3 7 Gestures Gesture ID hex One Point Gesture North 0x10 North East 0x12 East 0x14 South East 0x16 South 0x18 South West 0x1A West 0x1C North West 0x1E Rotate Clockwise 0x28 Rotate Anti clockwise 0x29 Click 0x20 Double Click 0x22 Two Point Gesture North 0x30 North East 0x32 East 0x34 South East 0x36 South 0x38 South West 0x3A West 0x3C North West 0x3E Click 0x40 Zoom In 0x48 Zoom Out 0x49 ...

Page 23: ...arted with Altera s DE2 115 Board tut_initialDE2 115 pdf which is available on the DE2 115 system CD Copy the entire demonstrations folder from the VEEK MT system CD to your host computer 4 2 4 2 Factory Configuration Factory Configuration The VEEK MT development kit comes preconfigured with a default utility that boots up on power on and allows users to quickly select load and run different Ready...

Page 24: ...cessing the reference design is developed based on the Altera Video and Image Processing Suite VIP The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is filled by NIOS II processor according to users input For multi touch processing a Terasic Memory Mapped IP is used to retrieve the ...

Page 25: ...ed on your PC 2 Power on the DE2 115 board 3 Connect USB Blaster to the DE2 115 board and install USB Blaster driver if necessary 4 Execute the demo batch file test bat under the batch file folder Painter demo_batch 5 After Nios II program is downloaded and executed successfully you will see a painter GUI in the LCD Figure 4 3 shows the GUI of the Painter Demo The GUI is classified into three area...

Page 26: ...sers paint in the canvas area Figure 4 5 shows the phone when counter clockwise rotation gesture is detected Figure 4 6 shows the photo when zoom in gesture is detected Figure 4 3 GUI of Painter Demo Figure 4 4 Single Touch Painting 23 ...

Page 27: ...Figure 4 5 Counter clockwise Rotation Gesture Figure 4 6 Zoom in Gesture Note execute the test bat under Picture_Viewer demo_batch will automatically download the sof and elf file 24 ...

Page 28: ...ration The Nios II CPU here takes a key role in the demonstration It is responsible of decoding the JPEG images and coordinates the works of all the peripherals The touch panel handling program uses the timer as a regular interrupter and periodically updates the sampled coordinates Figure 4 7 Block Diagram of the Picture Viewer Demonstration Demonstration Source Code Project directory Picture_View...

Page 29: ...d after the delay period 8 You can control the slide show as follows Press Forward to advance Reverse to go back to previous image Play Stop to play the slide or stop it On the top corner you will see the delay period seconds You can increase or decrease the delay period by touching the or buttons The max delay is 120 seconds the min delay is 1 second and the default delay is 10 seconds You can hi...

Page 30: ... stream to smooth or sharpen images Alpha Blending Mixer Mixes and blends multiple image streams useful for implementing text overlay and picture in picture mixing Scaler A sophisticated polyphase scaler that allows custom scaling and real time updates of both the image sizes and the scaling coefficients Deinterlacer Converts interlaced video formats to progressive video format using a motion adap...

Page 31: ...deo system is implemented using the SOPC Builder system level design tool This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon...

Page 32: ...to be configured to provide NTSC output or PAL output Connect the VGA output of the VEEK MT to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA note Run the Nios II IDE and choose VIP Software as the workspace Click on the Run button note Press the screen of the VEEK MT and drag the video frame box will result in scaling the playing window to any size as sh...

Page 33: ... 5 megapixel CMOS sensor and 7 inch LCD modules on the VEEK MT The CMOS sensor module sends the raw image data to FPGA on the DE2 115 board the FPGA on the board handles image processing part and converts the data to RGB format to display on the LCD module The I2C Sensor Configuration module is used to configure the CMOS sensor module Figure 4 12 shows the block diagram of the demonstration ...

Page 34: ...AW2RGB block After that the Multi Port SDRAM Controller acquires and writes the RGB data streams to the SDRAM which performs as a frame buffer The Multi Port SDRAM Controller has two write ports and read ports also with 16 bit data width each The writing clock is the same as CMOS sensor pix clock and the reading clock is provided by the LCD Controller which is 33MHz Finally the LCD controller fetc...

Page 35: ...the SW 0 and KEY 1 to set the exposure time for brightness adjustment of the image captured When SW 0 is set to Off the brightness of image will be increased as KEY 1 is pressed longer If SW 0 is set to On the brightness of image will be decreased as KEY 1 is pressed shorter User can use SW 17 to mirror image of the line However remember to press KEY 0 after toggle SW 17 Note execute the test bat ...

Page 36: ...nctions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 2 This demonstration needs the Quartus II license file includes the VIP suite feature These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EP4CE115F29 featured on t...

Page 37: ...valon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery For the objective of a better visual...

Page 38: ...e as the workspace Click on the Run button note The system enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit Press KEY 2 to stop run you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the VGA display User can use SW 17 to mirror image of the line However remember to press KEY 0 after tog...

Page 39: ...en tilting the VEEK MT the ADXL345 measures the static acceleration of gravity In the Nios II software the change of angle in the x axis and y axis is computed and shown as angle data in the LCD display The value of light sensor will change as the brightness changes around the light sensor Figure 4 16 shows the hardware system block diagram of this demonstration The system is clocked by an externa...

Page 40: ...nsor elf Demonstration Setup Load the bit stream into the FPGA on the VEEK MT Run the Nios II software under the workspace G_sensor Software Note After the Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal its ADXL345 s ID e5 Tilt the VEEK MT to all directions and you will find that the angle of the accelerometer and value of light sensor ...

Page 41: ...Figure 4 17 Digital Accelerometer Demonstration Note Execute G_sensor demo_batch test bat to download sof and elf files 38 ...

Page 42: ...d demos in your SD card root directory as well as in the System CD under Factory_Recovery Application_Selector folder Figure 5 1 shows the photograph of the application selector main interface Figure 5 1 Application selector main interface Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications in...

Page 43: ... controller Application Files Each loadable application consists of two binary files all stored on the SD card The first binary file represents the software portion of the example and must be derived from an ELF file as described in the section of this document titled Creating Your Own Loadable Applications This binary file can be named anything supported by the FAT16 file system the only restrict...

Page 44: ... hardware a Nios II ELF file The only restrictions are The hardware designs must contain a CFI Flash controller 1 If the SOF file contains a Nios II CPU then its reset address should be set to CFI Flash at offset 0x0 Before compiling the software make sure you have set your software s program memory text section in Flash memory under the System Library Properties Nios II IDE page or through BSP Ed...

Page 45: ...opy I srec O binary your software name flash your software name _SW bin 3 You may pad a compress option for saving binary image space because the Cyclone IV E series support the decompress feature while loading hardware image from EPCS device 4 The command will use the default HAL boot loader and link it to the text section 5 You can also use the tool bin_demo_batch to convert your sof and elf to ...

Page 46: ...nerated Selector bin is our target binary file Restoring the original binary file To restore the original contents of the Application Selector perform the following steps Copy Selector project into a local directory of your choice The Selector project is placed in Demonstrations Selector Power on the VEEK MT with the USB cable connected to the USB Blaster port Download the Selector sof to the boar...

Page 47: ...Figure 5 2 Programming Flash settings 44 ...

Page 48: ... Appendix 45 6 1 6 1 Revision History Revision History Version Change Log V1 0 Initial Version Preliminary 6 2 6 2 Copyright Statement Copyright Statement Copyright 2011 Terasic Technologies All rights reserved ...

Search results

Summary of Contents for ALTERA VEEK-MT

Reviews:

Related manuals for ALTERA VEEK-MT

Brands by name

Popular brands

Terasic ALTERA VEEK-MT, User Manual

Search results

Summary of Contents for ALTERA VEEK-MT

Reviews:

Related manuals for ALTERA VEEK-MT

Brands by name

Popular brands