Sharp UP-5300, Service Manual

Page: 48 / 123

Signal Name Pin No.
Signal Type
(Drive)
Selected By Signal Description
SDRAS# D7 O SDAM Row Address Strobe (primary copy): This output is part of
the SDRAM command combination. This pin should be connected to
the SDRAM through a damping resistor.
DWE# E10 O
(8mA)
Cycle
Multiplexed DRAM Write Enable (primary copy): This signal is the common
write enable for all 64 bits of DRAM if either fast page mode or EDO
DRAMs are used. This signal can be buffered externally before
connection to the WE# input of the DRAMs.
SDWE# SDRAM Write Enable: This output is the write enable signal for
SDRAM.
MA[11:0] Refer to
Table 3-2 O
(8/12mA)
Memory Address Bus Lines 11 through 0: Multiplexed row/column
address lines to the DRAMs. Depending on the kind of DRAM
modules being used, these signals may or may not need to be
buffered externally. MA12 is optionally available instead of RAS3# or
RAS4#.
MD[63:32] Refer to
Table 3-2 I/O
(4mA)
Higher Order Memory Data Bus: These pins are connected directly
to the higher order DRAM data bus.
MD[31:0] Refer to
Table 3-2 I/O
(4mA)
Lower Order Memory Data Bus: These pins are connected directly
to the lower order DRAM data bus.
PCI Bus Interface
AD[31:0] Refer to
Table 3-2 I/O
(PCI)
PCI Address an Data: AD[31:0] are bidirectional address and data
lines for the PCI bus. The AD[31:0] signals sample or drive the
address and data on the PCI bus.
C/BE[3:0]# AE14,
AF14,
AC15,
AD15
I/O
(PCI)
PCI Bus Command and Byte Enables: During the address phase
of a transaction, C/BE[3:0]# define the PCI command. During the
data phase, C/BE[3:0]# are used as the PCI byte enables. The PCI
commands indicate the current cycle type, and the PCI byte enables
indicate which byte lanes carry meaningful data. FireStar drives
C/BE# as an initiator of a PCI bus cycle and monitors C/BE[3:0]# as
a target.
CPAR AC17 I/O
(PCI)
Calculated Parity Signal: PAR is "even" parity and is calculated on
36 bits - AD[31:0] plus C/BE[3:0]#. PAR is generated for address and
data phases and is only guaranteed to be valid on the PCI clock after
the corresponding address or data phase.
FRAME# AB9 I/O
(PCI)
Cycle Frame: FRAME# is driven by the current bus master to
indicate the beginning and duration of an access. FRAME# is
asserted to indicate that a bus transaction is beginning. FRAME# is
an input when FireStar is the target and an output when it is the
initiator.
IRDY# AB11 I/O
(PCI)
Initiator Ready: IRDY# indicates FireStar’s ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on each clock
that both IRDY# and TRDY# are sampled asserted. IRDY# is an
input to when FireStar is the target and an output when it is the
initiator.
TRDY# AB12 I/O
(PCI)
Target Ready: TRDY# indicates FireStar’s ability to complete the
current data phase of the transaction. It is used in conjunction with
IRDY#. A data phase is completed on each clock that TRDY# and
IRDY# are both sampled asserted. TRDY# is an input when FireStar
is the initiator and an output when it is the target.
DEVSEL# AF15 I/O
(PCI)
Device Select: FireStar asserts DEVSEL# to claim a PCI
transaction. As an output, FireStar asserts DEVSEL# when it
samples configuration cycles to the configuration registers. FireStar
also asserts DEVSEL# when an internal IPC address is decoded.
As an input, DEVSEL# indicates the response to a transaction. If no
slave claims the cycle, FireStar will assert DEVSEL# to terminate the
cycle.
STOP# AC16 I/O
(PCI)
Stop: STOP# indicates that FireStar, as a targent, is requesting a
master to sotp the current transaction. As a master, STOP# causes
FireStar to stop the current transaction. STOP# is an output when
FireStar is a target and an input when it is the initiator.
PLOCK# AE15 I/O
(PCI)
PCI Lock: PLOCK# is used to indicate an atomic operation that may
require multiple transactions to complete. When PLOCK# is asserted,
non-exclusive transactions may proceed to an address that is not
currently locked. Control of PLOCK# is obtained under its own
protocol in conjunction with PGNT#.
5 – 15