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7-3. Pin description
Table 4. Quick Pin Reference
Symbol
Type
Name and Function
A20M#
I
When the address bit 20 mask pin is asserted, the Pentium processor emulates the address wrap around at 1 Mbyte
which occurs on the 8086. When A20M# is asserted, the processor masks physical address bit 20 (A20) before
performing a lookup to the internal caches or driving a memory cycle on the bus. The effect of A20M# is undefined in
protected mode. A20M# must be asserted only when the processor is in real mode.
A31-A3
I/O
As outputs, the address lines of the processor along with the byte enables define the physical area of memory or I/O
accessed. The external system drives the inquire address to the processor on A31-A5.
ADS#
O
The address status indicates that a new valid bus cycle is currently being driven by the processor.
AHOLD
I
In response to the assertion of address hold, the processor will stop driving the address lines (A31-A3), and AP in the
next clock. The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles.
AP
I/O
Address parity is driven by the processor with even parity information on all processor generated cycles in the same
clock that the address is driven. Even parity must be driven back to the processor during inquire cycles on this pin in
the same clock as EADS# to ensure that correct parity check status is indicated.
APCHK#
O
The address parity check status pin is asserted two clocks after EADS# is sampled active if the processor has detected
a parity error on the address bus during inquire cycles. APCHK# will remain active for one clock each time a parity
error is detected.
BE7#-BE5#
BE4#-BE0#
O
I/O
The byte enable pins are used to determine which bytes must be written to extemal memory, or which bytes were
requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-
3).
BF [1:0]
I
Bus Frequency determines the bus-to-core ratio. BF [1:0] is sampled at RESET, and cannot be changed until another
non-warm (1 ms) assertion of RESET. Additionally, BF [1:0] must not change values while RESET is active.
BOFF#
I
The backoff input is used to abort all outstanding bus cycles that have not yet completed. In response to BOFF#, the
processor will float all pins normally floated during bus hold in the next clock. The processor remains in bus hold until
BOFF# is negated, at which time the Pentium processor restarts the aborted bus cycle(s) in their entirety.
BP [3:2]
PM/BP [1:0]
O
The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0. These pins extemally indicate a breakpoint
match when the debug registers are programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the performance monitoring pins (PM1 and PM0). The PB1 and PB0 bits in the
Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The
pins come out of RESET configured for performance monitoring.
BRDY#
I
The burst ready input indicates that the external system has presented valid data on the data pins in response to a
read or that the external system has accepted the processor data in response to a write request. This signal is
sampled in the T2, T12 and T2P bus states.
BREQ
O
The bus request output indicates to the extemal system that the processor has internally generated a bus request. This
signal is always driven whether or not the processor is driving its bus.
BUSCHK#
I
The bus check input allows the system to signal an unsuccessful completion of a bus cycle. If this pin is sampled
active, the processor will latch the address and control signals in the machine check registers. If, in addition, the MCE
bit in CR4 is set, the processor will vector to the machine check exception.
CACHE#
O
For processor-initiated cycles, the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst
writeback cycle (if a write). If this pin is driven inactive during a read cycle, the processor will not cache the returned
data, regardless of the state of the KEN# pin. This pin is also used to determine the cycle length (number of transfers
in the cycle).
CLK
I
The clock input provides the fundamental timing for the processor. Its frequency is the operating frequency of the
processor external bus and require TTL levels. All external timing parameters except TDI, TDO, TMS, TRST# and
PICD0-1 are specified with respect to the rising edge of CLK.
NOTE:
It is recommended that CLK begin 150 ms after Vcc reaches its proper operating level. This recommendation is only to
assure the long term reliability of the device.
D/C#
O
The data/code output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS#
signal is asserted. D/C# distinguishes between data and code or special cycles.
D63-D0
I/O
These are the 64 data lines for the processor. Lines D7-D0 define the least significant byte of the data bus; Lines D63-
D56 define the most significant byte of the data bus. When the CPU is driving the data lines, they are driven during the
T2, T12 or T2P clocks for that cycle. During reads, the CPU samples the data bus when BRDY# is returned.
DP7-DP0
I/O
These are the data parity pins for the processor. There is one for each byte of the data bus. They are driven by the
processor with even parity information on writes in the same clock as write data. Even parity information must be
driven back to the Pentium processor with voltage reduction technology on these pins in the same clock as the data to
ensure that the correct parity check status is indicated by the processor. DP7 applies to D63-D56; DP0 applies to D7-
D0.
EADS#
I
This signal indicates that a valid external address has been driven onto the processor address pins to be used for an
inquire cycle.
EWBE#
I
The external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the extemal
system. When the processor generates a write and EWBE# is sampled inactive, the processor will hold off all
subsequent writes to all E-or M-state lines in the data cache until all write cycles have completed, as indicated by
EWBE# being active.
FERR#
O
The floating point error pin is driven active when an unmasked floating point error occurs. FERR# is similar to the
ERROR# pin on the Intel387™ math coprocessor. FERR# is included for compatibility with systems using DOS-type
floating point error reporting.
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