Sharp UP-5300, Service Manual

Page: 42 / 123

Symbol Type Name and Function
FLUSH# I When asserted, the cache flush input forces the processor to write back all modified lines in the data cache and
invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the processor indicating
completion of the writeback and invalidation.
NOTE:
If FLUSH# is sampled low when RESET transitions from high to low, tristate test mode is entered.
HIT# O The hit indication is driven to reflect the outcome of an inquire cycle. If an inquire cycle hits a valid line in either the
data or instruction cache, this pin is asserted two clocks after EADS# is sampled asserted. If the inquire cycle misses
the cache, this pin is negated two clocks after EADS#. This pin changes its value only as a result of an inquire cycle
and retains its value between the cycles.
HITM# O The hit to a modified line output is driven to reflect the outcome of an inquire cycle. It is asserted after inquire cycles
which resulted in a hit to a modified line in the data cache. It is used to inhibit another bus master from accessing the
data until the line is completely written back.
HLDA O The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin. It
indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master.
When leaving bus hold, HLDA will be driven inactive and the processor will resume driving the bus. If the processor
has a bus cycle pending, it will be driven in the same clock that HLDA is de-asserted.
HOLD I In response to the bus hold request, the processor will float most of its output and input/output pins and assert HLDA
after completing all outstanding bus cycles. The processor will maintain its bus in this state until HOLD is de-asserted.
HOLD is not recognized during LOCK cycles. The processor will recognize HOLD during reset.
IERR# O The internal error pin is used to indicate internal parity errors. If a parity error occurs on a read from an internal array,
the processor will assert the IERR# pin for one clock and then shutdown.
IGNNE# I This is the ignore numeric error input. This pin has no effect when the NE bit in CR0 is set to 1. When the CR0.NE bit
is 0, and the IGNNE# pin is asserted, the processor will ignore any pending unmasked numeric exception and continue
executing floating-point instructions for the entire duration that this pin is asserted. When the CR0.NE bit is 0, IGNNE#
is not asserted a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one of
FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the processor will execute the
instruction in spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked
numeric exception exists (SW.ES = 1), and the floating-point instruction is one other than FINIT, FCLEX, FSTENV,
FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the processor will stop execution and wait for an external
interrupt.
INIT I The processor initialization input pin forces the processor to begin execution in a known state. The processor state
after INIT is the same as the state after RESET except that the internal caches, write buffers, and floating point
registers retain the values they had prior to INIT. INIT may NOT be used in lieu of RESET after power up.
If INIT is sampled high when RESET transitions from high to low, the processor will perform built-in self test prior to the
start of program execution.
INTR I An active maskable interrupt input indicates that an external interrupt has been generated. If the IF bit in the EFLAGS
register is set, the processor will generate two locked interrupt acknowledge bus cycles and vector to an interrupt
handler after the current instruction execution is completed. INTR must remain active until the first interrupt
acknowledge cycle is generated to assure that the interrupt is recognized.
INV I The invalidation input determines the final cache line state (S or I) in case of an inquire cycle hit. It is sampled together
with the address for the inquire cycle in the clock EADS# is sampled active.
KEN# I The cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to
determine cycle length. When the processor generates a cycle that can be cached (CACHE# asserted) and KEN# is
active, the cycle will be transformed into a burst line fill cycle.
LOCK# O The bus lock pin indicates that the current bus cycle is locked. The processor will not allow a bus hold when LOCK# is
asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the first locked bus cycle and
goes inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at
least one clock between back-to-back locked cycles.
M/IO# O The memory/input-output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the
ADS# signal is asserted. M/IO# distinguishes between memory and I/O cycles.
NA# I An active next address input indicates that the external memory system is ready to accept a new bus cycle although all
data transfers for the current cycle have not yet completed. The processor will issue ADS# for a pending cycle two
clocks after NA# is asserted. The processor supports up to two outstanding bus cycles.
NMI I The non-maskable interrupt request signal indicates that an extemal non-maskable interrupt has been generated.
PCD O The page cache disable pin reflects the state of the PCD bit in CR3; Page Directory Entry or Page Table Entry. The
purpose of PCD is to provide an extemal cacheability indication on a page-by page basis.
PCHK# O The parity check output indicates the result of a parity check on a data read. It is driven with parity status two clocks
after BRDY# is returned. PCHK# remains low one clock for each clock in which a parity error was detected. Parity is
checked only for the bytes on which valid data is returned.
PEN# I The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result
of a data parity error on a read cycle. If this pin is sampled active in the clock, a data parity error is detected. The
processor will latch the address and control signals of the cycle with the parity error in the machine check registers. If,
in addition, the machine check enable bit in CR4 is set to "1", the processor will vector to the machine check exception
before the beginning of the next instruction.
PM/BP[1:0] O These pins function as part of the performance monitoring feature.
The breakpoint 1-0 pins are multiplexed with the performance monitoring 1-0 pins. The PB1 and PB0 bits in the Debug
Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins
come out of RESET configured for performance monitoring.
5 – 9