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Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
TAG3
B9
I/O
(4mA)
SYSCFG
00h[5] = 0
11h[3] = 0
Tag RAM Data Bit3: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG4
A9
I/O
(4mA)
SYSCFG
11[3] = 0
Tag RAM Data Bit 4: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG5
D8
I/O
(4mA)
SYSCFG
11h[3] = 0
Tag RAM Data Bit 5: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG6
C8
I/O
(4mA)
SYSCFG
11h[3] = 0
Tag RAM Data Bit 6: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG7
B8
I/O
(4mA)
SYSCFG
11h[3] = 0
Tag RAM Data Bit 7: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAGWE#
A10
O
(4mA)
PCIDV1
81h = 00h
Tag RAM Write Enable: This control strobe is used to update the
Tag RAM with the valid tag of the new cache line that replaces the
current one during external cache read miss cycles.
ADSC#
P5
O
(4mA)
PCIDV1
82h = 00h
Controller Address Strobe: For a synchronous L2 cache operation,
this pin is connected to the ADSC# input of the synchronous SRAMs.
ADV#
P2
O
(4mA)
PCIDV1
83h = 00h
Advance Output: For synchronous cache L2 operation, this pin
becomes the advance output and is connected to the ADV# input of
the synchronous SRAMs.
8-3-2. DRAM and PCI Interface Signal Set
Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
DRAM Interface
RAS0#m E12
E12
O
(8/12mA)
Cycle
Multiplexed
Row Address Strobe 0: Each RAS# signal corresponds to a unique
DRAM bank. Depending on the kind of DRAM modules being used,
this signal may or may not need to be buffered externally. This signal,
however, should be connected to the corresponding DRAM RAS#
line through a damping resistor.
SDCS0#
SDRAM Chip Select Line 0: Each SDCS# output corresponds to a
unique SDRAM Bank. When active, the SDRAM will accept the
command from FireStar. These outputs must be connected to the
SDRAM banks through a damping resistor.
RAS1#
E13
O
(8/12mA)
Cycle
Multiplexed if
PCIDV1
85h = 00h
Row Address Strobe 1: Refer to RAS0# signal description.
SDCS1#
SDRAM Chip Select Line 1: Refer to SDCS0# description.
RAS2#
B12
O
(8/12mA)
Cycle
Multiplexed if
PCIDV1
84h = 00h
Row Address Strobe 2: Refer to RAS0# signal description.
SDCS2#
SDRAM Chip Select Line 2: Refer to SDCS0# description.
RAS3#
C12
O
(8/12mA)
Cycle
Multiplexed
Row Address Strobe 3: Refer to RAS0# signal description.
SDCS3#
SDRAM Chip Select Line 3: Refer to SDCS0# description.
RAS4#
E22
O
(8/12mA)
SYSCFG
19h[3] = 1
Row Address Strobe 4 (primary copy): Refer to RAS0# signal
description.
MA12
SYSCFG
19h[3] = 1
PCIDV1
53h[6:5] = 10
Memory Address Bus Line 12
CAS[7:0]#
A12,
D11,
C11,
B11,
A11,
D10,
C10,
B10
O
(8mA)
Cycle
Multiplexed
Column Address Strobe Lines 7 through 0 (primary copies): The
CAS[7:0]# outputs correspond to the eight bytes for each DRAM
bank. Each DRAM bank has a 64-bit data bus. These signals are
typically connected directly to the DRAM’s CAS# inputs through a
damping resistor.
SDDQM[7:0]#
SDRAM Data Mask Control Bits 7 through 0: During SDRAM read
cycles, these outputs control whether the DRAM output buffers are
driven on the MD bus or not.
During SDRAM write cycles, these outputs control whether or not MD
data will be written into the memory device.
SDCAS#
A8
O
SDRAM Column Address Strobe (primary copy): This output is
part of the SDRAM command combination. This pin should be
connected to the SDRAM through a damping resistor.
5 – 14
Summary of Contents for UP-5300
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Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
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