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Pin name
I/O
Level
Function
LCDON
I/O
COMS
LCD Driving Power Supply On
This output is the signal which requests turning-on of the power supply for driving the LCD panel on.
LOW:
Off
HIGH:
On
This terminal can also be used as a general-purpose I/O port.
In the external RAMDAC mode, this terminal outputs the register address Bit0 to RAMDAC.
LOGICON
I/O
CMOS
LCD Logic Power Supply On
This output is the signal which requests turning on of the logic power supply for the LCD panel.
LOW:
Off
HIGH:
On
This terminal can also be used as a general-purpose I/O port.
In the external RAMDAC mode, this terminal outputs the register address Bit1 to RAMDAC.
LP
O
Latch Pulse
This output is the pulse which indicates the 1-line data latch timing of the STNLCD panel. For the TFTLCD
panel and in the external RAMDAC mode, it indicates a horizontal synchronizing signal.
FP
O
Frame Pulse
This output is the pulse which indicates the frame start of the STNLCD panel. For the TFTLCD panel and in
the external RAMDAC mode, it indicates a vertical. synchronizing signal.
DISP
O
Display Enable
This output is the signal which enables the LCD to display. It is used as the blanking signal in the external
RAMDAC mode and as the display enable signal for the TFTLCD panel.
SCK
O
Shift Clock
This output is the data shift clock to the STNLCD panel. The dot clock is output for the TFTLCD panel and in
the external RAMDAC mode.
UD[7:0]
LD[7:0]
O
Upper/Lower Data 7:0
This is data for outputting display data.
In the external RAMDAC mode, LD[7:0] is display data while UD[7:0] is write data line to the RAMDAC
register
10-3-4. Chip settings
Pin name
I/O
Level
Function
RESET/RST
I
5VTTL
RESET(ISA)/RST(386, 486, PCI)
The chip is reset to the initial state when this input is at high. This reset signal controls the phase of the clock
when the host is in the 386 mode. Remember that this terminal is positive logic.
MA[2:0]
I
CMOS
HOST Type
MA[2:0] remains in the input mode during setting. In the input mode, it is used as the terminal that sets the
host type to be connected.
Settings other than given below are prohibited.
MA[2:0] Host Type
0 0 0 ISA
0 0 1 386SX
0 1 0 386DX
0 1 1 486
1 0 0 PCI
XIN/XO
I/O
CMOS
Clock In/Out
This is the clock I/O of the chip. Connect a crystal resonator. This is used for the display clock. The refresh
rate of the LCD panel is determined by the input frequency of this pin.
The input frequency must be from 4MHZ to 30MHz.
EXTCLK
I
CMOS
EXTERNAL MCLK
Input from this terminal is used as an MCLK instead of the oscillation of the built-in PLL. If the oscillation
starts when the reset is active, the PLL automatically becomes disable and the signal from this terminal is
used as the MCLK. Input the signal at a higher clock frequency than XIN and within the range from 35MHz
to 65MHz. Secure it to VDD or VSS when not used.
MINTEST
I
COMOS
TEST
TEST[2:0]
I
5VTTL
Secure the MINTEST pin to VSS.
Secure to VSS for operation. (PCI mode only)
PLLTEST
I/O
Terminal for testing PLL. Secure to VSS for operation.
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Summary of Contents for UP-5300
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