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Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
Miscellaneous
A20M#
R3
O
(4mA)
Address Bit 20 Mask: This pin is an output and generates the
A20M# output by trapping GATEA20 commands to the keyboard or
to Port 092h. The CPUINIT signal to the CPU is generated whenever
it senses reset commands to Port 060h/064h, or a Port 092h write
command with bit 0 set high.
When keyboard emulation is disabled, FireStar traps only Port 092h
GATEA20 commands and accepts the GATEA20 input from the
keyboard controller, which os sent out as A20M# to the CPU.
ROMCS#
J24
O
(4mA)
PCIDV1
52h[2] = 0
97h = 00h
4Fh[1] = 0
BIOS ROM Chip Select: This output goes active on both reads and
writes to the ROM area to support flash ROM. For flash ROM
support, writes to ROM can be supported by appropriately setting
PCIDV1 47h[7].
SPKROUT
H23
I/O
(8mA)
Speaker Data: This pin is used to drive the system board speaker.
This signal is a function of the Timer-0 Counter-2 and Port 061h bit 1.
Can use CISA Protocol to gang several.
KBDCS#
J26
O
(8mA)
Default PCIDV1
98h = 00h
Keyboard Chip Select: Used to decode accesses to the keyboard
controller.
8-3-5 Test Mode Selection Pins
Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
RSVD
B7
I/O (4mA)
Reserved: This pin is reserved for possible additional functionality on
future revisions of FireStar. However, it is used as an input for the
ATE Test Mode selection address. See TMS (pin AB5) description.
Strap option
pin for future
2.5V CPU
interface,
refer to Table
3-7
RSVD
A7
I/O (4mA)
Reserved in FireStar: An input for the ATE Test Mode selection
address. See TMS (Pin AB5) description.
TMS
AB5
I/O
Test Mode Select: An input for the ATE Test Mode selection
address.
AB5
B7
A7
Mode
0
X
X
Normal operation (default)
1
0
0
Tristate all pins
1
0
1
NAND tree test
1
1
0
Reserved for factory test
1
1
1
Reserved for Factory test
8-3-6 Power and Ground Pins
Signal Name
Pin No.
Signal Type
Signal Description
GND
AA6, AA13,
AA14, AA21,
AB13, E14,
F6, F13, F14,
F21, N5, N6,
N21, P6,
P21, P22
G
Ground Connections
VCC_ISA
L22, U22, Y22
P
ISA Bus Power Plane: 3.3V or 5.0V
VCC_CPU
E8, G5, T5,
W5
P
CPU Bus Power Plane: 3.3V (and 2.5V in future 2.5V CPU interface revision)
VCC_CORE
AB19, H22,
K5,
P
FireStar Core power Plane: 3.3V only
VCC_DRAM
E11, E17,
E20
P
Memory Power Plane: 3.3V or 5.0V
VCC_PCI
AB7, AB10,
AB16
P
PCI Bus Power Plane: 3.3V or 5.0V
5VREF
AB21, E7
P
5.0V Reference: Connect to 5.0V is available in the system. Connect to 3.3V for an all
3.3V design.
5 – 21
Summary of Contents for UP-5300
Page 103: ... B S i d e 9 2 ...
Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
Page 108: ...6 I N V E R T E R P W B A S i d e B S i d e 7 L C D R E L A Y P W B A S i d e B S i d e 9 7 ...