![background image](http://html.mh-extra.com/html/sharp/up-5300/up-5300_service-manual_373328044.webp)
8-2. Pin assignments
HD48
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
H46D
B
HD43
C
HD39
D
HD35
E
HD30
F
HD26
G
HD21
H
HD16
J
HD12
K
HD7
L
HD3
M
GWE#
N
CDOE#
P
CPU-
RST
R
FERR#
T
SMI-
ACT#
U
BE4#
V
BE0#
W
HA6
Y
HA10
AA
HA14
AB
HA17
AC
HA19
AD
HA20
AE
HA21
AF
HD49
HD47
HD44
HD40
HD36
HD31
HD27
HD22
HD17
HD13
HD8
HD4
HD0
ADV#
KEN#
CACHE
LOCK#
BE5#
BE1#
HA5
HA9
HA13
HA16
HA18
HA22
HA23
HD50
HD51
HD45
HD41
HD37
HD32
HD28
HD23
HD18
HD14
HD9
HD5
HD1
CACS#
A20M#
D/C#
AHOLD
BE6#
BE2#
HA4
HA8
HA12
HA15
HA24
HA25
HA26
HD52
HD53
HD54
HD42
HD38
HD33
HD29
HD24
HD19
HD15
HD10
HD6
HD2
BWE#
HITM#
EADS#
NA#
BE7#
BE3#
HA3
HA7
HA11
HA27
HA28
HA29
HA30
HD55
HD56
HD57
HD58
OSC_
14MHZ
HD34
VCC
_CPU
HD25
HD20
VCC
_CORE
HD11
CPU-
CLKIN
GND
ADSC#
BOFF#
VCC
_CPU
BRDY#
ADS#
VCC
_CPU
M/IO#
W/R#
TMS
HA31
NMI
SMI#
INTR
HD59
HD60
HD61
HD62
HD63
GND
GND
GND
GND
PCI
CLKIN
IGERR#
CPU-
INIT
STP
CLK#
AD31
SDCKE*
RSVD
OSC32
SD
RAS#
5VREF
VCC
_PCI
AD30
AD29
AD28
AD27
SD
CAS#
TAG7
TAG6
TAG5
VCC
_CPU
AD26
AD25
AD24
AD23
AD22
TAG4
TAG3
TAG2
TAG1
TAG0
FRAME
#
AD21
AD20
AD19
AD18
TAG-
WE#
CAS0#
CAS1#
CAS2#
DWE#
VCC
_PCI
AD17
AD16
AD15
AD14
CAS3#
CAS4#
CAS5#
CAS6#
VCC
_DRAM
IRDY#
AD13
AD12
AD11
AD10
CAS7#
RAS2#
RAS3#
MA0
RAS0#
TRDY#
AD9
AD8
AD7
AD6
MA1
MA2
MA3
MA4
RAS1#
GND
GND
GND
AD5
AD4
AD3
AD2
MA5
MA6
MA7
MA8
GND
GND
GND
PCI
CLK0
AD1
AD0
C/BE3#
C/BE2#
MA9
MA10
MA11
MD63
MD62
GNT2#
C/BE1#
C/BE0#
PLOCK
#
DEV-
SEL#
MD61
MD60
MD59
MD58
MD57
VCC
_PCI
STOP#
GNT0#
REQ2#
CLK
RUN#
MD56
MD55
MD54
MD53
VCC
_DRAM
GNT1#
CPAR
SERR#
PERR#
REQ0#
MD52
MD51
MD50
MD49
MD48
REQ1#
GNT3#
REQ3#
IRQ
SER
IRQ1
MD47
MD46
MD45
MD44
HD43
VCC
_CORE
IRQ
3/A
IRQ
4/B
IRQ
5/C
IRQ
6/D
MD42
MD41
MD40
MD39
VCC
_DRAM
CMD#
SEL#/
ATB#
IRQ
7/E
IRQ6#
IRQ
9/F
MD38
MD37
MD36
MD35
HD34
GND
GND
GND
GND
5VREF
IRQ
11/H
IRQ12
IRQ14
IRQ15
MD33
MD32
MD31
MD30
RAS4#
MD5
MD0
DACK
0#/A#
VCC
_ISA
AEN
SA1
GND
SA10
SA15
VCC
_ISA
SMWR#
BALE
VCC
_ISA
ATCLK
IRQ
10/G
SD15
SD14
SD13
SD12
MD29
MD28
MD27
MD26
MD10
MD6
MD1
DACK
1#/B#
DRQ
3/D
TC
SA0
SA5
SA9
SA14
SA19
SA23
IO16#
XD3
XD7
MWR#
PPWRL
SD11
SD10
SD9
MD25
MD24
MD23
MD14
MD11
MD7
MD2
DACK
2#/C#
DRQ
5/E
DRQ
0/A
RTC
AS
SA4
SA8
SA13
SA18
SA22
M16#
XD2
XD6
IOR#
RESET
#
SD2
SD8
SD7
MD22
MD21
MD17
MD15
MD12
MD8
MD3
DACK
3#/D#
DRQ
6/F
DRQ
1/B
RTC
RD#
SA3
SA7
SA12
SA17
SA21
SBHE#
XD1
XD5
IOW#
RST
DRV
SD1
SD4
SD6
MD20
MD19
MD18
MD16
MD13
MD9
MD4
DACK
5#/E#
DRQ
7/G
DRQ
2/C
RTC
WR#
SA2
SA6
SA11
SA16
SA20
SMRD#
XD0
XD4
IOCH-
RDY
MRD#
SD0
SD3
SD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Ground
Power
Multiplexed Signal - Refer to Table 3-2
Key :
Top View
DACK
_CORE
SPKR
OUT
DBEW# DDRQ0 PWR
GD
DACK
6#/F#
DACK
7#/G#
DACK
CS#
RFSH# KBD
CS#
Note: *In FireStar ACPI pin A7 becomes SDCKE, where as in the non~ACPI version it is reserved. However, in both versions pin A7 is still
used as part of the input address for NAND tree test mode.
5 – 11
Summary of Contents for UP-5300
Page 103: ... B S i d e 9 2 ...
Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
Page 108: ...6 I N V E R T E R P W B A S i d e B S i d e 7 L C D R E L A Y P W B A S i d e B S i d e 9 7 ...