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Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
SERR#
AD17
I/O
(PCI)
System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active,
FireStar generates a non-maskable interrupt (NMI) to the 3.3V
Pentium CPU.
PERR#
AE17
I/O
(4mA)
Party Error: PERR# may be pulsed by any agent that detects a
parity error during an address phase, or by the master or by the
selected target during any data phase in which the AD[31:0] lines are
inputs. Upon sampling PERR# active, FireStar generates a non-
maskable interrupt (NMI) to the 3.3V Pentium CPU.
PCICLKIN
AB6
I
PCI Clock Input: Master PCI clock input on the CPU power plane.
PCICLKIN is a 5.0V tolerant input, even when its power plane is
connected to 3.3V as long as the 5VREF pins of FireStar are
connected to +5.0V.
PIO6
AF16
I/O
(PCI)
PCIDV1
86h
≠
00h
Programmable Input/Output 6: See Section 3.3, "Programmable
I/O Pins"
REQ0#
AF17
I
PCI Bus Request 0: REQ# is used by PCI bus masters to request
control of the bus.
GNT0#
AD16
O
(PCI)
PCI Bus Grant 0: GNT# is returned to PCI bus masters asserting
REQ#, when the bus becomes available.
PIO7
AB18
I/O
(4mA)
PCIDV1
87h
≠
00h
Programmable Input/Output 7: See Section 3.3, "Programmable
I/O Pins", on page 33 for more details.
PCICLK0
AB14
O
(PCI)
PCI Clock Output 0: This PCI clock output is always available.
Strap option
pin, refer to
Table 3-7
PCICLK1
AB17
O
(4mA)
RTCRD# strap
option
PCI Clock Output 1
REQ2#
AB16
I
PCIDV1
88h = 00h
PCI Bus Request 2: REQ# is used by PCI bus masters to request
control of the bus.
GNT2#
AB15
O
(PCI)
Default
PCI Bus Grant 2: GNT# is returned to PCI bus masters asserting
REQ#, when the bus becomes available.
REQ3#
AD18
I
PCI Bus Request 3: REQ# is used by PCI bus masters to request
control of the bus.
GNT3#
AC18
O
(PCI)
PCI Bus Grant 3: GNT# is returned to PCI bus masters asserting
REQ#, when the bus becomes available.
8-3-3. IDE Interface Signal Set
Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
Bus Master IDE Interface
DBEW#
H24
Strap option
pin, refer to
Table 3-7
O
(4mA)
Default
Drive W Buffer Control
DDRQ0
H25
I/O
(4mA)
PCIDV1
89h=00h
Drive Cable A DMA Request
Clock and Reset Interface
RESET#
AC24
O
(8mA)
System Reset: When asserted, this signal resets the CPU. RESET#
is asserted in response to a PWRGD only and is guaranteed to be
active for 1ms such that CLK and VCC are stable.
If RSTDRV is programmed to toggle in Suspend (via SYSCFG
40h[0]), so will RESET# since RESET# is derived from RSTDRV.
PWRGD
H26
I
Power Good: This input reflects the "wired-OR" status of the external
reset switch and the power good status from the power supply.
OSC_14MHZ
E5
I
Timer Oscillator Clock: This is the main clock used by the internal
8254 timers. It is connected to a 14.31818MHz oscillator.
OSC_14MHz is a 5.0V tolerant input, even when its power plane is
connected to 3.3.V as long as the 5VREF pins of FireStar are
connected to +5.0V.
5 – 16
Summary of Contents for UP-5300
Page 103: ... B S i d e 9 2 ...
Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
Page 108: ...6 I N V E R T E R P W B A S i d e B S i d e 7 L C D R E L A Y P W B A S i d e B S i d e 9 7 ...