Rev. 2.00, 09/03, page 666 of 690
Trc
Trc
Trc
Trc
Trr
Tpw
Tp
Trc
t
CSD2
t
CSD2
t
CSD2
t
CSD2
t
AD3
t
AD3
t
AD3
t
AD3
t
RWD2
t
RWD2
t
RWD2
t
RASD2
t
RASD2
t
RASD2
t
RASD2
CKIO
A25 to A0
CSn
RD/
WR
A12/A11
*
1
D31 to D0
RASU/L
t
CASD2
t
CASD2
CASU/L
(Hi-Z)
BS
CKE
DQMxx
DACKn
*
2
t
CKED2
t
CKED2
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.41 Synchronous DRAM Self-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode)
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