Rev. 2.00, 09/03, page 262 of 690
CKIO
A25 to A0
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
D31 to D0
WEn
RD
DACKn
(Active-Low)
CSn
Transfer source
address
Transfer destination
address
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Figure 8.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)
•
Single Address Mode
In single address mode, either the transfer source or transfer destination peripheral device is
accessed (selected) by means of the DACK signal, and the other device is accessed by address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in
the case of transfer between external memory and an external device with DACK shown in
figure 8.7, when the external device outputs data to the data bus, that data is written to the
external memory in the same bus cycle.
Summary of Contents for SH7705
Page 2: ......
Page 70: ...Rev 2 00 09 03 page 24 of 690 ...
Page 194: ...Rev 2 00 09 03 page 148 of 690 ...
Page 284: ...Rev 2 00 09 03 page 238 of 690 ...
Page 338: ...Rev 2 00 09 03 page 292 of 690 ...
Page 354: ...Rev 2 00 09 03 page 308 of 690 ...
Page 374: ...Rev 2 00 09 03 page 328 of 690 ...
Page 420: ...Rev 2 00 09 03 page 374 of 690 ...
Page 476: ...Rev 2 00 09 03 page 430 of 690 ...
Page 482: ...Rev 2 00 09 03 page 436 of 690 ...
Page 552: ...Rev 2 00 09 03 page 506 of 690 ...
Page 630: ...Rev 2 00 09 03 page 584 of 690 ...
Page 739: ...SH7705 Group Hardware Manual REJ09B0082 0200O ...