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Rev. 2.00, 09/03, page 261 of 690

Address Modes

•

Dual Address Mode

In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.

DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 8.5, data is read to the DMAC from one external memory in a data read cycle, and
then that data is written to the other external memory in a write cycle.

Data buffer

Address bus

Data bus

Address bus

Data bus

Memory

Transfer source

module

Transfer destination

module

Memory

Transfer source

module

Transfer destination

module

SAR

DAR

Data buffer

SAR

DAR

The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.

The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.

DMAC

DMAC

First bus cycle

Second bus cycle

Figure 8.5 Data Flow of Dual Address Mode

Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode.
Channel control register (CHCR) can specify whether the DACK is output in read cycle or
write cycle.

Figure 8.6 shows an example of DMA transfer timing in dual address mode.

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Summary of Contents for SH7705

Page 1: ...2003 9 19 32 SH7705 Group Hardware Manual Renesas 32 Bit RISC Microcomputer SuperH RISC engine Family SH7700 Series Rev 2 00 ...

Page 2: ......

Page 3: ...Renesas 32 Bit RISC Microcomputer SuperH RISC engine Family SH7700 Series SH7705 Group Hardware Manual REJ09B0082 0200O ...

Page 4: ... The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com 4...

Page 5: ...ization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of pro...

Page 6: ...iguration of the functional description of each module differs according to the module However the generic style includes the following items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given a...

Page 7: ... to explain the hardware functions and electrical characteristics of the SH7705 MCU to the above users Refer to the SH 3 SH 3E SH3 DSP Programming Manual for a detailed description of the instruction set Notes on reading this manual Product names The following products are covered in this manual Product Classifications and Abbreviations Basic Classification Product Code SH7705 HD6417705 In order t...

Page 8: ... Related Manuals The latest versions of all related manuals are available from our web site Please ensure you have the latest versions of all documents you require http www renesas com eng SH7705 manuals Manual Title ADE No SH7705 Hardware Manual This manual SH 3 SH 3E SH3 DSP Programming Manual ADE 602 096 Users manuals for development tools Manual Title ADE No SH Series C C Compiler Assembler Op...

Page 9: ... Access Controller etu Elementary Time Unit FIFO First In First Out Hi Z High Impedance UDI User Debugging Interface INTC Interrupt Controller IrDA Infrared Data Association JTAG Joint Test Action Group LQFP Low Profile QFP LRU Least Recently Used LSB Least Significant Bit MMU Memory Management Unit MPX Multiplex MSB Most Significant Bit PC Program Counter PFC Pin Function Controller PLL Phase Loc...

Page 10: ...ronous DRAM TAP Test Access Port T B D To Be Determined TLB Translation Lookaside Buffer TMU Timer Unit TPU Timer Pulse Unit UART Universal Asynchronous Receiver Transmitter UBC User Break Controller USB Universal Serial Bus WDT Watchdog Timer ...

Page 11: ... O Test data output UDI input output port F 144 F14 ASEBRKAK PTF6 O I O ASE break acknowledge UDI input output port F 145 E17 ASEMD0 2 7 PTF7 I I O ASE mode UDI input output port F 195 C6 RESETP 6 I Power on reset request Notes 6 Pull up MOS connected 7 The pull up MOS turns on if the pin function controller PFC is used to select other functions UDI 4 4 1 Address Array Address Array Write Associat...

Page 12: ...upt source TMU2 IPRA 7 to 4 7 4 2 CSn Space Bus Control Register CSnBCR n 0 2 3 4 5A 5B 6A 6B 160 Bits 14 to 12 description added Note SDRAM can be specified only in area 2 and area 3 If SDRAM is connected to only one area SDRAM should be specified for area 3 In this case area 2 should be specified as normal space 161 Note 5 added Note 5 The SDRAM bank active mode can only be used for the CS3 spac...

Page 13: ...ion address setting prohibited in 16 byte transfer 245 Bits 13 12 description amended 00 Fixed source address setting prohibited in 16 byte transfer 8 4 3 Channel Priority Round Robin Mode 258 The priority of round robin mode is CH0 CH1 CH2 CH3 immediately after a reset When the round robin mode is specified cycle steal mode and burst mode should not be mixed among the bus modes for multiple chann...

Page 14: ...y Function 301 Description amended This function can be used to reduce the power consumption in the normal mode and sleep mode 427 Table amended Interrupt Source Description DMAC Activation 16 5 SCIF Interrupt Sources and DMAC Table 16 4 SCIF Interrupt Sources ERI Interrupt initiated by receive error flag ER or break flag BRK Not possible RXI Interrupt initiated by receive FIFO data full flag RDF ...

Page 15: ...BANK LDC L Rm R7_BANK LDC L Rn MOD LDC L Rn RS LDC L Rn RE LDC Rn MOD LDC Rn RS LDC Rn RE BSR label BSRF Rm JSR Rm 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 Instruction Value Decremented 23 2 Input Output Pins 569 Note added Note The pull up MOS turns on if the pin function controller PFC is used to select other functions UDI 23 3 3 Boundary Scan Register SDBSR 570 Description amended SDBSR is a...

Page 16: ... mode 0 1 2 4 5 6 7 Note 1 amended Note 1 RESETP RESETM NMI and IRQ5 to IRQ0 are asynchronous Figure 25 15 Pin Drive Timing at Standby 638 Figure amended CKIO tSTD STATUS 0 STATUS 1 Normal mode Normal mode Standby mode 25 3 4 Basic Timing Figure 25 16 Basic Bus Cycle No Wait 640 Note 2 added tAH tWED tWED tWDH1 tWDH4 tWDD1 WEn 2 D31 to D0 Write Notes 1 DACKn is a waveform when active low is specif...

Page 17: ...1 tWDH1 tWDH1 tWDD1 D15 to D0 WEn 2 Write Notes 1 DACKn is a waveform when active low is specified 2 Output timing is the same when reading byte selection SRAM 25 3 11 SCIF Module Signal Timing Table 25 13 SCIF Module Signal Timing 671 Item amended Transmission data delay time clock synchronization RTS delay time clock synchronization 679 Note 11 added Reset Power Down States A I O Port States in ...

Page 18: ...ased I O Handling of Unused Pins Port NF PTD 5 I I Z I I I I Pull up PTE 7 V P K P P IO Open NF PTJ 7 L O O O O O O Open NF PTJ 6 0 H 13 O O O O O O Open Note 13 The values of PTJ6 PTJ1 and PTJ0 differ during power on reset and after the power on reset state is released They conform to the port J data register value after being switched to port status by the pin function controller PFC After Power...

Page 19: ... 35 2 4 Data Formats 37 2 4 1 Register Data Format 37 2 4 2 Memory Data Formats 38 2 5 Features of CPU Core Instructions 40 2 5 1 Instruction Execution Method 40 2 5 2 CPU Instruction Addressing Modes 42 2 5 3 CPU Instruction Formats 45 2 6 Instruction Set 48 2 6 1 CPU Instruction Set Based on Functions 48 2 6 2 Operation Code Map 62 Section 3 Memory Management Unit MMU 65 3 1 Role of MMU 65 3 1 1...

Page 20: ...3 6 3 Usage Examples 92 3 7 Usage Note 92 Section 4 Cache 93 4 1 Features 93 4 1 1 Cache Structure 93 4 2 Register Descriptions 95 4 2 1 Cache Control Register 1 CCR1 96 4 2 2 Cache Control Register 2 CCR2 97 4 2 3 Cache Control Register 3 CCR3 100 4 3 Operation 101 4 3 1 Searching the Cache 101 4 3 2 Read Access 102 4 3 3 Prefetch Operation 102 4 3 4 Write Access 102 4 3 5 Write Back Buffer 103 4...

Page 21: ...t Pins 127 6 3 Register Descriptions 127 6 3 1 Interrupt Priority Level Setting Registers A to H IPRA to IPRH 128 6 3 2 Interrupt Control Register 0 ICR0 129 6 3 3 Interrupt Control Register 1 ICR1 130 6 3 4 Interrupt Control Register 2 ICR2 132 6 3 5 PINT Interrupt Enable Register PINTER 132 6 3 6 Interrupt Request Register 0 IRR0 133 6 3 7 Interrupt Request Register 1 IRR1 134 6 3 8 Interrupt Re...

Page 22: ...gnment 180 7 6 Normal Space Interface 187 7 6 1 Basic Timing 187 7 6 2 Access Wait Control 192 7 6 3 CSn Assert Period Expansion 194 7 7 Address Data Multiplex I O Interface 195 7 8 SDRAM Interface 198 7 8 1 SDRAM Direct Connection 198 7 8 2 Address Multiplexing 200 7 8 3 Burst Read 212 7 8 4 Single Read 214 7 8 5 Burst Write 215 7 8 6 Single Write 217 7 8 7 Bank Active 218 7 8 8 Refreshing 225 7 ...

Page 23: ... 274 9 3 Clock Operating Modes 275 9 4 Register Descriptions 279 9 4 1 Frequency Control Register FRQCR 279 9 4 2 USB Clock Frequency Control Register UCLKCR 281 9 4 3 Usage Notes 281 9 5 Changing Frequency 282 9 5 1 Changing Multiplication Rate 282 9 5 2 Changing Division Ratio 282 9 5 3 Modification of Clock Operating Mode 282 9 6 Usage Notes 283 Section 10 Watchdog Timer WDT 285 10 1 Features 2...

Page 24: ...y Mode 302 11 8 Timing of STATUS Pin Changes 303 Section 12 Timer Unit TMU 309 12 1 Features 309 12 2 Input Output Pin 311 12 3 Register Descriptions 311 12 3 1 Timer Start Register TSTR 312 12 3 2 Timer Control Registers TCR 313 12 3 3 Timer Constant Registers TCOR 317 12 3 4 Timer Counters TCNT 317 12 3 5 Input Capture Register_2 TCPR_2 317 12 4 Operation 318 12 4 1 Counter Operation 318 12 4 2 ...

Page 25: ...3 7 Timer General Registers TGR 341 14 3 8 Timer Start Register TSTR 341 14 4 Operation 342 14 4 1 Overview 342 14 4 2 Basic Functions 343 14 4 3 Buffer Operation 346 14 4 4 PWM Modes 348 Section 15 Realtime Clock RTC 351 15 1 Features 351 15 2 Input Output Pins 353 15 3 Register Descriptions 353 15 3 1 64 Hz Counter R64CNT 354 15 3 2 Second Counter RSECCNT 354 15 3 3 Minute Counter RMINCNT 355 15...

Page 26: ...criptions 379 16 3 1 Receive Shift Register SCRSR 380 16 3 2 Receive FIFO Data Register SCFRDR 380 16 3 3 Transmit Shift Register SCTSR 380 16 3 4 Transmit FIFO Data Register SCFTDR 381 16 3 5 Serial Mode Register SCSMR 381 16 3 6 Serial Control Register SCSCR 385 16 3 7 FIFO Error Count Register SCFER 389 16 3 8 Serial Status Register SCSSR 390 16 3 9 Bit Rate Register SCBRR 395 16 3 10 FIFO Cont...

Page 27: ... Register EPDR0s 445 18 3 10 EP1 Data Register EPDR1 446 18 3 11 EP2 Data Register EPDR2 446 18 3 12 EP3 Data Register EPDR3 446 18 3 13 EP0o Receive Data Size Register EPSZ0o 447 18 3 14 EP1 Receive Data Size Register EPSZ1 447 18 3 15 Trigger Register TRG 448 18 3 16 Data Status Register DASTS 449 18 3 17 FIFO Clear Register FCLR 449 18 3 18 DMA Transfer Setting Register DMAR 450 18 3 19 Endpoin...

Page 28: ...ol Register PACR 480 19 2 2 Port B Control Register PBCR 481 19 2 3 Port C Control Register PCCR 483 19 2 4 Port D Control Register PDCR 485 19 2 5 Port E Control Register PECR 487 19 2 6 Port E Control Register 2 PECR2 488 19 2 7 Port F Control Register PFCR 489 19 2 8 Port F Control Register 2 PFCR2 490 19 2 9 Port G Control Register PGCR 491 19 2 10 Port H Control Register PHCR 493 19 2 11 Port...

Page 29: ...DR 517 20 9 Port J 518 20 9 1 Register Description 518 20 9 2 Port J Data Register PJDR 518 20 10 Port K 519 20 10 1 Register Description 519 20 10 2 Port K Data Register PKDR 519 20 11 Port L 520 20 11 1 Register Description 520 20 11 2 Port L Data Register PLDR 521 20 12 Port M 521 20 12 1 Register Description 522 20 12 2 Port M Data Register PMDR 522 20 13 Port N 523 20 13 1 Register Descriptio...

Page 30: ...MRA 544 22 2 3 Break Bus Cycle Register A BBRA 544 22 2 4 Break Address Register B BARB 545 22 2 5 Break Address Mask Register B BAMRB 546 22 2 6 Break Data Register B BDRB 546 22 2 7 Break Data Mask Register B BDMRB 547 22 2 8 Break Bus Cycle Register B BBRB 547 22 2 9 Break Control Register BRCR 549 22 2 10 Execution Times Break Register BETR 552 22 2 11 Branch Source Register BRSR 553 22 2 12 B...

Page 31: ...ddresses by functional module in order of the corresponding section numbers 586 24 2 Register Bits 595 24 3 Register States in Each Operating Mode 614 Section 25 Electrical Characteristics 623 25 1 Absolute Maximum Ratings 623 25 2 DC Characteristics 625 25 3 AC Characteristics 630 25 3 1 Clock Timing 631 25 3 2 Control Signal Timing 636 25 3 3 AC Bus Timing 638 25 3 4 Basic Timing 640 25 3 5 Burs...

Page 32: ...9 03 page xxxii of xlvi 25 3 16 AC Characteristics Measurement Conditions 677 25 4 A D Converter Characteristics 678 Appendix 679 A I O Port States in Each Processing State 679 B Package Dimensions 685 Index 687 ...

Page 33: ...68 Figure 3 3 Virtual Address Space MMUCR AT 0 69 Figure 3 4 P4 Area 69 Figure 3 5 External Memory Space 70 Figure 3 6 Overall Configuration of the TLB 75 Figure 3 7 Virtual Address and TLB Structure 76 Figure 3 8 TLB Indexing IX 1 77 Figure 3 9 TLB Indexing IX 0 78 Figure 3 10 Objects of Address Comparison 79 Figure 3 11 Operation of LDTLB Instruction 82 Figure 3 12 Synonym Problem 32 kbyte Cache...

Page 34: ...ronous DRAM Connection 32 Bit Data Bus 199 Figure 7 15 Example of 64 MBit Synchronous DRAM 16 Bit Data Bus 200 Figure 7 16 Synchronous DRAM Burst Read Wait Specification Timing Auto Precharge 213 Figure 7 17 Basic Timing for Single Read Auto Precharge 214 Figure 7 18 Basic Timing for Synchronous DRAM Burst Write Auto Precharge 216 Figure 7 19 Basic Timing for Single Write Auto Precharge 217 Figure...

Page 35: ...gure 8 15 Example of DREQ Input Detection in Burst Mode Edge Detection 268 Figure 8 16 Example of DREQ Input Detection in Burst Mode Level Detection 269 Figure 8 17 Example of DMA Transfer End Signal in Cycle Steal Level Detection 269 Figure 8 18 BSC Ordinary Memory Access No Wait Idle Cycle 1 Longword Access to 16 Bit Device 270 Section 9 Clock Pulse Generator CPG Figure 9 1 Block Diagram of Cloc...

Page 36: ...nit TPU Figure 14 1 Block Diagram of TPU 331 Figure 14 2 Example of Counter Operation Setting Procedure 343 Figure 14 3 Free Running Counter Operation 344 Figure 14 4 Periodic Counter Operation 344 Figure 14 5 Example of Setting Procedure for Waveform Output by Compare Match 345 Figure 14 6 Example of 0 Output 1 Output Operation 345 Figure 14 7 Example of Toggle Output Operation 346 Figure 14 8 Co...

Page 37: ...nitialization 421 Figure 16 14 Sample Serial Transmission Flowchart 2 Second and Subsequent Transmission 421 Figure 16 15 Sample Serial Reception Flowchart 1 First Reception after Initialization 422 Figure 16 15 Sample Serial Reception Flowchart 2 Second and Subsequent Reception 423 Figure 16 16 Sample Simultaneous Serial Transmission and Reception Flowchart 1 First Transfer after Initialization 4...

Page 38: ...ure 20 9 Port J 518 Figure 20 10 Port K 519 Figure 20 11 Port L 520 Figure 20 12 Port M 521 Figure 20 13 Port N 523 Figure 20 14 SC Port 524 Section 21 A D Converter Figure 21 1 Block Diagram of A D Converter 528 Figure 21 2 A D Conversion Timing 535 Figure 21 3 Definitions of A D Conversion Accuracy 537 Figure 21 4 Definitions of A D Conversion Accuracy 537 Figure 21 5 Analog Input Circuit Exampl...

Page 39: ...WM Bit 0 No Idle Cycle Setting 643 Figure 25 20 Address Data Multiplex I O Bus Cycle Three Address Cycles One Software Wait One External Wait 644 Figure 25 21 Burst ROM Read Cycle One Access Wait One External Wait One Burst Wait Two Bursts 645 Figure 25 22 Synchronous DRAM Single Read Bus Cycle Auto Precharge CAS Latency 2 TRCD 1 Cycle TRP 1 Cycle 646 Figure 25 23 Synchronous DRAM Single Read Bus ...

Page 40: ...8 Synchronous DRAM Mode Register Write Timing TRP 2 Cycle 662 Figure 25 39 Access Timing in Low Frequency Mode Auto Precharge 664 Figure 25 40 Synchronous DRAM Auto Refresh Timing TRP 2 Cycle Low Frequency Mode 665 Figure 25 41 Synchronous DRAM Self Refresh Timing TRP 2 Cycle Low Frequency Mode 666 Figure 25 42 Synchronous DRAM Mode Register Write Timing TRP 2 Cycle Low Frequency Mode 667 Figure 2...

Page 41: ...Rev 2 00 09 03 page xli of xlvi Appendix Figure B 1 Package Dimensions FP 208C 685 Figure B 2 Package Dimensions TBP 208A 686 ...

Page 42: ...D C and PR Bits 80 Section 4 Cache Table 4 1 Number of Entries and Size Way in Each Cache Size 93 Table 4 2 LRU and Way Replacement when Cache Locking Mechanism Is Disabled 95 Table 4 3 Way Replacement when a PREF Instruction Misses the Cache 99 Table 4 4 Way Replacement when Instructions other than the PREF Instruction Miss the Cache 99 Table 4 5 LRU and Way Replacement when W2LOCK 1 and W3LOCK 0...

Page 43: ...7 14 Relationship between A2 3BSZ 1 0 A2 3ROW 1 0 and Address Multiplex Output 5 1 208 Table 7 15 Relationship between A2 3BSZ 1 0 A2 3ROW 1 0 and Address Multiplex Output 6 1 210 Table 7 16 Relationship between Access Size and Number of Bursts 212 Table 7 17 Access Address in SDRAM Mode Register Write 229 Table 7 18 Relationship between Bus Width Access Size and Number of Bursts 232 Section 8 Dir...

Page 44: ...r Serial Transfer Format Selection 403 Table 16 3 Serial Transfer Formats 404 Table 16 4 SCIF Interrupt Sources 427 Section 17 Infrared Data Association Module IrDA Table 17 1 Pin Configuration 432 Section 18 USB Function Module Table 18 1 Pin Configuration 439 Table 18 2 Command Decoding on Application Side 464 Section 19 Pin Function Controller Table 19 1 Multiplex Pins 475 Section 20 I O Ports ...

Page 45: ...ble 23 2 UDI Commands 570 Table 23 3 SH7705 Pins and Boundary Scan Register Bits 571 Table 23 4 Reset Configuration 579 Section 25 Electrical Characteristics Table 25 1 Absolute Maximum Ratings 623 Table 25 2 DC Characteristics 1 Common Items 625 Table 25 2 DC Characteristics 2 a Excluding USB Related Pins 627 Table 25 2 DC Characteristics 2 b USB Related Pins 628 Table 25 2 DC Characteristics 2 c...

Page 46: ...Rev 2 00 09 03 page xlvi of xlvi Appendix Table A 1 I O Port States in Each Processing State 679 ...

Page 47: ...ontroller DMAC and an external memory access support function enables direct connection to different kinds of memory This LSI also includes powerful peripheral functions that are essential to system configuration such as USB Function functionality and a serial interface with a large FIFO A powerful built in power management function keeps power consumption low even during high speed operation This...

Page 48: ...or basic instructions Logical address space 4 Gbytes Five stage pipeline Memory management unit MMU 4 Gbytes of address space 256 address space identifiers ASID 8 bits Page unit sharing Supports multiple page sizes 1 kbyte or 4 kbytes 128 entry 4 way set associative TLB Supports software selection of replacement method and random replacement algorithms Contents of TLB are directly accessible by ad...

Page 49: ...ct the CS assert negate timing SDRAM refresh function Supports auto refresh and self refresh modes SDRAM burst access function Different SDRAM can be connected to area 2 or area 3 size latency Usable as either big or little endian machine Direct memory access controller DMAC Four channels Two of these channels support external requests Burst mode and cycle steal mode Outputs transfer end signal in...

Page 50: ...transmit receive FIFOs High speed UART UART supports FIFO stop and FIFO trigger Supports RTS CTS Supports IrDA 1 0 only channel 0 USB function module USB Conforms to USB 2 0 full speed specification Supports modes with an on chip and external USB transceiver Supports control transfer endpoint 0 bulk transfer endpoint 1 2 and interrupt transfer endpoint 3 The USB standard commands are supported and...

Page 51: ...h trace AUD Power supply voltage I O 3 3 0 3 V internal 1 5 0 1 V Power Supply Voltage Product Name I O On chip Modules Operating Frequency Product Code Package 133 MHz HD6417705F133 100 MHz HD6417705F100 208 pin plastic LQFP FP 208C 133 MHz HD6417705BP133 SH7705 3 3 0 3 V 1 5 0 1 V 100 MHz HD6417705BP100 208 pin TFBGA TBP 208A Product lineup ...

Page 52: ...fer Interrupt controller Clock pulse generator watchdog timer Central processing unit User break controller Advanced user debugger Bus state controller Direct memory access controller Timer unit 16 bit timer pulse unit Realtime clock Compare match timer Serial communication interface with FIFO Infrared data association module Universal serial bus A D converter User debugging interface Pin function...

Page 53: ...BACK PTG5 PTD5 NF CKE PTD4 CASU PTD3 V SS Q INDEX 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CASL PTD2 RASU PTD1 RASL PTD0 CS6B PTD7 CS6A PTC7 CS5B PTD6 CS5A PTC6 CS4 PTC5 CS3 PTC4 CS2 PTC3 CS0 RD WR WE3 DQMUU AH PTC2 WE2 DQMUL PTC1 WE1 DQMLU VCCQ WE0 DQMLL VSSQ RD BS PTC0 A25 PTK7...

Page 54: ...4 3 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A B C D E F G H J K L M N P R T U SH7705 TBP 208A Top view INDEX MARK Note The terminal area surrounded by the dotted line is the perspective view Figure 1 3 Pin Assignment TBP 208A ...

Page 55: ...rrupt 16 F1 D27 PTB3 PINT11 I O I O I Data bus input output port B PINT interrupt 17 G4 VssQ I O power supply 0 V 18 G3 D26 PTB2 PINT10 I O I O I Data bus input output port B PINT interrupt 19 G2 VccQ I O power supply 3 3 V 20 G1 D25 PTB1 PINT9 I O I O I Data bus input output port B PINT interrupt 21 H4 D24 PTB0 PINT8 I O I O I Data bus input output port B PINT interrupt 22 H3 D23 PTA7 PINT7 I O I...

Page 56: ...3 N3 D6 I O Data bus 44 N4 VssQ I O power supply 0 V 45 P1 D5 I O Data bus 46 P2 VccQ I O power supply 3 3 V 47 P3 D4 I O Data bus 48 R1 D3 I O Data bus 49 R2 D2 I O Data bus 50 P4 D1 I O Data bus 51 T1 D0 I O Data bus 52 T2 VssQ I O power supply 0 V 53 U1 A0 PTK0 O I O Address bus input output port K 54 U2 A1 O Address bus 55 R3 A2 O Address bus 56 T3 A3 O Address bus 57 U3 VssQ I O power supply ...

Page 57: ...put port K 80 R9 Vcc Internal power supply 1 5 V 81 U10 A22 PTK4 O I O Address bus input output port K 82 T10 A23 PTK5 O I O Address bus input output port K 83 R10 A24 PTK6 O I O Address bus input output port K 84 P10 A25 PTK7 O I O Address bus input output port K 85 U11 BS PTC0 O I O Bus cycle start signal input output port C 86 T11 RD O Read strobe 87 R11 VssQ I O power supply 0 V 88 P11 WE0 DQM...

Page 58: ...supply 0 V 106 T17 CASU 3 PTD3 O I O Upper 32 Mbytes address CAS SDRAM input output port D 107 R15 CKE PTD4 O I O CK enable SDRAM input output port D 108 R16 PTD5 NF 4 I Input port D NF 4 109 R17 BACK PTG5 O I O Bus acknowledge input output port G 110 P15 BREQ PTG6 I I O Bus request input output port G 111 P16 VssQ I O power supply 0 V 112 P17 WAIT PTG7 I I O Hardware wait request input output por...

Page 59: ...0 V 134 H16 PTM0 I O Input output port M 135 H15 PTM1 I O Input output port M 136 H14 PTM2 I O Input output port M 137 G17 PTM3 I O Input output port M 138 G16 VccQ I O power supply 3 3 V 139 G15 TDI 7 PTG0 I I O Test data input UDI input output port G 140 G14 TCK 7 PTG1 I I O Test clock UDI input output port G 141 F17 TMS 7 PTG2 I I O Test mode select UDI input output port G 142 F16 TRST 1 7 PTG3...

Page 60: ...put enable 164 A14 PTN2 XVDATA I O I input output port N USB differential receive input 165 D13 PTN3 TXDMNS I O O input output port N USB D transmit output 166 C13 PTN4 TXDPLS I O O input output port N USB D transmit output 167 B13 PTN5 DMNS I O I input output port N D input from USB receiver 168 A13 PTN6 DPLS I O I input output port N D input from USB receiver 169 D12 PTN7 I O input output port N...

Page 61: ...uest input output port H 194 B6 DREQ1 PTH6 I I O DMA request input output port H 195 C6 RESETP 6 I Power on reset request 196 D6 CA I Hardware standby request 197 A5 MD3 I Area 0 bus width setting 198 B5 MD4 I Area 0 bus width setting 199 C5 AVss Analog power supply 0 V 200 D5 AN0 PTL0 I I A D converter input input port L 201 A4 AN1 PTL1 I I A D converter input input port L 202 B4 AN2 PTL2 I I A D...

Page 62: ...power on reset When these pins are connected to memory and so on their levels must be fixed externally 4 The initial functions of NF No Function pins are not assigned after power on reset Specifies the functions with Pin Function Controller PFC 5 In hardware standby mode supply power to all power supply pins including the RTC power supply pins 6 Pull up MOS connected 7 The pull up MOS turns on if ...

Page 63: ...tem power supply There will be no operation if any pins are open Power supply VssQ Ground Ground pin Connect all VssQ pins to the system power supply 0 V There will be no operation if any pins are open Vcc PLL1 PLL1 power supply Power supply for the on chip PLL1 oscillator Vss PLL1 PLL1 ground Ground pin for the on chip PLL1 oscillator Vcc PLL2 PLL2 power supply Power supply for the on chip PLL2 o...

Page 64: ...ship has been released to an external device Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus System control CA I Chip active High in normal operation and low in hardware standby mode NMI I Non maskable interrupt Non maskable interrupt request pin Fix to high level when not in use IRQ5 to IRQ0 I Interrupt requests 5 to 0 Maskable interru...

Page 65: ...byte write Indicates that bits 15 to 8 of the data in the external memory or device are being written WE0 O Lowest byte write Indicates that bits 7 to 0 of the data in the external memory or device are being written CKE O CK enable Clock enable SDRAM DQMUU O DQ mask UU Selects D31 to D24 SDRAM DQMUL O DQ mask UL Selects D23 to D16 SDRAM DQMLU O DQ mask LU Selects D15 to D8 SDRAM DQMLL O DQ mask LL...

Page 66: ...K0 SCK2 I O Serial clock Clock input output pin RTS0 RTS2 O Transmit request Modem control pin Serial communication interface with FIFO SCIF0 SCIF2 CTS0 CTS2 I Transmit enable Modem control pin IrTX O IrDA TX port IrDA transmit data output IrDA IrRX I IrDA RX port IrDA receive data input EXTAL2 I RTC clock RTC crystal oscillator pin 32 768 kHz XTAL2 O RTC clock RTC crystal oscillator pin 32 768 kH...

Page 67: ...ransmit output pin for the driver DPLS I D input D signal input pin from the receiver to the driver DMNS I D input D signal input pin from the receiver to the driver TXENL O Output enable Output enable pin for the driver SUSPND O Suspend Suspend state output pin for the transceiver Vcc USB USB analog power supply USB power supply pin When the USB is not in use connect this pin to the port power su...

Page 68: ...TF0 I O General purpose port 8 bit general purpose I O port pins PTG7 to PTG0 I O General purpose port 8 bit general purpose I O port pins PTH6 to PTH0 I O General purpose port 7 bit general purpose I O port pins PTJ7 to PTJ0 O General purpose port 8 bit general purpose output port pins PTK7 to PTK0 I O General purpose port 8 bit general purpose I O port pins PTL3 to PTL0 I General purpose port 4 ...

Page 69: ...set Initial signal input pin AUDATA3 to AUDATA0 O AUD data Destination address output pin in branch trace mode AUDCK O AUD clock Synchronous clock output pin in branch trace mode Advanced user debugger AUD AUDSYNC O AUD synchronous signal Data start position acknowledge signal output pin in branch trace mode ASEBRKAK O Break mode acknowledge Indicates that the E10A emulator has entered its break m...

Page 70: ...Rev 2 00 09 03 page 24 of 690 ...

Page 71: ...t After initialization the program branches to address H A0000000 to pass control to the reset processing program to be executed Exception Handling State In the exception handling state the CPU processing flow is changed temporarily by a general exception or interrupt exception processing The program counter PC and status register SR are saved in the save program counter SPC and save status regist...

Page 72: ...annot be executed This function effectively protects the system resources from the user program To change the processing mode from user to privileged mode a transition to exception handling state is required Note To call a service routine used in privileged mode from user mode the LSI supports an unconditional trap instruction TRAPA When a transition from user mode to privileged mode occurs the co...

Page 73: ...e a transition to an address error exception occurs P1 Area The P1 area is defined as a cacheable but non address translatable area Normally programs executed at high speed in privileged mode such as exception processing handlers which are at the core of the operating system S are assigned to the P1 area P2 Area The P2 area is defined as a non cacheable but non address translatable area A reset pr...

Page 74: ... details please refer to section 7 Bus State Controller BSC In addition area 1 in the external memory space is used as an on chip I O space where most of this LSI s on chip module control registers are mapped 1 Normally the upper three bits of the 32 bit logical address are masked and the lower 29 bits are used for external memory addresses 2 For example address H 00000100 in the P0 area address H...

Page 75: ...nd R8 to R15 R0 to R7 are banked The process mode and the register bank RB bit in the status register SR define which set of banked registers R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1 are accessed as general registers System Registers This LSI incorporates the multiply and accumulate registers MACH MACL and procedure register PR as system registers These registers can be accessed regardless of ...

Page 76: ...gister Type Registers Initial Values General registers R0_BANK0 to R7_BANK0 R0_BANK1 to R7_BANK1 R8 to R15 Undefined System registers MACH MACL PR Undefined Program counter PC H A0000000 SR MD bit 1 RB bit 1 BL bit 1 I3 to I0 bits H F 1111 reserved bits all 0 other bits undefined GBR SSR SPC Undefined Control registers VBR H 00000000 Note Initialized by a power on or manual reset ...

Page 77: ...NK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL VBR PR PC SPC 0 a User mode register configuration b Privileged mode register configuration RB 1 c Privileged mode register configuration RB 0 Notes 1 The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode 2 Bank register 3 Bank regis...

Page 78: ... mode that is entered by a transition to exception handling state the RB bit is set to 1 to select bank 1 In privileged mode sixteen registers R0_BANK1 to R7_BANK1 and R8 to R15 are accessed as general registers R0 to R15 A bank is switched automatically when an exception handling state is entered registers R0 to R7 need not be saved by the exception handling routine The R0_BANK0 to R7_BANK0 regis...

Page 79: ...ate registers MACH MACL and procedure register PR as system registers can be accessed by the LDS and STS instructions Multiply and Accumulate Registers MACH MACL The multiply and accumulate registers MACH MACL store the results of multiplication and accumulation instructions or multiplication instructions The MACH MACL registers also store addition values for the multiplication and accumulations A...

Page 80: ... the PC is saved in the save program counter SPC Before a subroutine call is executed the PC is saved in the procedure register PR In addition the PC can be used for PC relative addressing mode Figure 2 5 shows the system register and program counter configurations MACH MACL 31 0 PR 31 0 PC 31 0 Multiply and accumulate high and low registers MACH MACL Procedure register PR Program counter PC Figur...

Page 81: ...e 29 RB 1 R W Register Bank The general registers R0 to R7 are banked registers The RB bit selects a bank used in the privileged mode 0 Selects bank 0 registers In this case R0_BANK0 to R7_BANK0 and R8 to R15 are used as general registers R0_BANK1 to R7_BANK1 can be accessed by the LDC or STR instruction 1 Selects bank 1 registers In this case R0_BANK1 to R7_BANK1 and R8 to R15 are used as general...

Page 82: ...is not affected in an exception handling state 0 T R W T Bit Indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow This bit can be specified by the SETT and CLRT instructions in user mode At reset this bit is undefined This bit is not affected in an exception handling state Note The M Q S and T bits can be set cleared by th...

Page 83: ...0000 Figure 2 6 shows the control register configuration 31 0 31 SPC SSR 0 Save status register SSR Save program counter SPC 31 0 31 VBR GBR 0 Global base register GBR Vector base register VBR 31 0 0 MD RB BL 0 Status register SR T S 0 0 I0 I1 I2 I3 Q M 0 Figure 2 6 Control Register Configuration 2 4 Data Formats 2 4 1 Register Data Format Register operands are always longwords 32 bits When the me...

Page 84: ...he register corresponds to the highest address For example if the contents of the general register R0 is stored at an address indicated by the general register R1 in longword the MSB byte of the R0 is stored at the address indicated by the R1 and the LSB byte of the R1 register is stored at the address indicated by the R1 3 The on chip device registers assigned to memory are accessed in big endian...

Page 85: ...e address indicated by the R1 3 and the LSB byte of the R1 register is stored at the address indicated by the R1 If the little endian mode is selected the on chip device registers assigned to memory are accessed in big endian mode Note that the available access size byte word or long word differs in each register Note The CPU instruction codes of this LSI must be stored in word units In little end...

Page 86: ...ever bit manipulation instructions such as AND are executed directly on memory Delayed Branching Unconditional branch instructions are executed as delayed branches With a delayed branch instruction the branch is made after execution of the instruction called the slot instruction immediately following the delayed branch instruction This minimizes disruption of the pipeline when a branch is made Thi...

Page 87: ...ss the absolute address value is placed in a table in memory beforehand as well as word or longword literal constant Using the method whereby immediate data is loaded when an instruction is executed this value is transferred to a register and the data is referenced using register indirect addressing mode 16 Bit 32 Bit Displacement When data is referenced with a 16 or 32 bit displacement the displa...

Page 88: ...d to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand Rn Rn 1 2 4 Rn 1 2 4 Rn After instruction execution Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Register indirect with pre decrement Rn Effective address is register Rn contents decremented by a constant beforehand 1 for a byte operand 2 for a word operand 4 for a longword operand Rn Rn 1 2 4 1 2 ...

Page 89: ... according to the operand size GBR GBR disp 1 2 4 1 2 4 disp Zero extended Byte GBR disp Word GBR disp 2 Longword GBR disp 4 Indexed GBR indirect R0 GBR Effective address is sum of register GBR and R0 contents GBR GBR R0 R0 GBR R0 PC relative with displacement disp 8 PC Effective address is PC with 8 bit displacement disp added After disp is zero extended it is multiplied by 2 word or 4 longword a...

Page 90: ... 8 8 bit immediate data imm of TST AND OR or XOR instruction is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended Immediate imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For addressing modes with displacement disp as shown below the assembler description in this manual indicates the value before it is scal...

Page 91: ...ent Table 2 4 CPU Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0 NOP n type xxxx nnnn xxxx xxxx 15 0 nnnn register direct MOVT Rn Control register or system register nnnn register direct STS MACH Rn Control register or system register nnnn pre decrement register indirect STC L SR Rn m type xxxx mmmm xxxx xxxx 15 0 mmmm r...

Page 92: ...ncrement register indirect nnnn register direct MOV L Rm Rn mmmm register direct nnnn pre decrement register indirect MOV L Rm Rn mmmm register direct nnnn indexed register indirect MOV L Rm R0 Rn md type xxxx xxxx mmmm dddd 15 0 mmmmdddd register indirect with displacement R0 register direct MOV B disp Rm R0 nd4 type xxxx xxxx nnnn dddd 15 0 R0 register direct nnnndddd register indirect with disp...

Page 93: ...R0 dddddddd PC relative BF label d12 type xxxx dddd dddd dddd 15 0 dddddddddddd PC relative BRA label label disp PC nd8 type xxxx nnnn dddd dddd 15 0 dddddddd PC relative with displacement nnnn register direct MOV L disp PC Rn i type xxxx xxxx i i i i i i i i 15 0 iiiiiiii immediate Indexed GBR indirect AND B imm R0 GBR iiiiiiii immediate R0 register direct AND imm R0 iiiiiiii immediate TRAPA imm ...

Page 94: ...ture data transfer 39 MOVA Effective address transfer MOVT T bit transfer SWAP Upper lower swap Data transfer instructions 5 XTRCT Extraction of middle of linked registers 21 ADD Binary addition 33 ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double...

Page 95: ...w 6 AND Logical AND 14 NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST Logical AND and T bit setting Logic operation instructions XOR Exclusive logical OR 12 ROTL 1 bit left shift 16 ROTR 1 bit right shift ROTCL 1 bit left shift with T bit ROTCR 1 bit right shift with T bit SHAL Arithmetic 1 bit left shift SHAR Arithmetic 1 bit right shift SHLL Logical 1 bit left shift SHLLn Lo...

Page 96: ...al branch JSR Branch to subroutine procedure Branch instructions RTS Return from subroutine procedure 15 CLRT T bit clear 75 CLRMAC MAC register clear CLRS S bit clear LDC Load into control register LDS Load into system register LDTLB PTEH PTEL load into TLB NOP No operation PREF Data prefetch to cache RTE Return from exception handling SETS S bit setting SETT T bit setting SLEEP Transition to pow...

Page 97: ...nt 2 Indicates summary of operation Explanation of Symbols Transfer direction xx Memory operand M Q T Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit n n bit left shift n n bit right shift Indicates a privileged instruction Value when no wait states are inserted 1 Value of T bit after instruction is executed Explanation of Sym...

Page 98: ...nmmmm0010 Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 MOV B Rm Rn 0110nnnnmmmm0100 Rm Sign extension Rn Rm 1 Rm 1 MOV W Rm Rn 0110nnnnmmmm0101 Rm Sign extension Rn Rm 2 Rm 1 MOV L Rm Rn 0110nnnnmmmm0110 Rm Rn Rm 4 Rm 1 MOV B R0 disp Rn 10000000nnnndddd R0 disp Rn 1 MOV W R0 disp Rn 10000001nnnndddd R...

Page 99: ...01dddddddd R0 disp x 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp x 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 11000101dddddddd disp x 2 GBR Sign extension R0 1 MOV L disp GBR R0 11000110dddddddd disp x 4 GBR R0 1 MOVA disp PC R0 11000111dddddddd disp x 4 PC R0 1 MOVT Rn 0000nnnn00101001 T Rn 1 SWAP B Rm Rn 0110nnnnmmmm1000 Rm Swap lowest two by...

Page 100: ...result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GT Rm Rn 0011nnnnmmmm0111 If Rn Rm with signed data 1 T 1 Comparison result CMP PL Rn 0100nnnn00010101 If Rn 0 1 T 1 Comparison result CMP PZ Rn 0100nnnn00010001 If Rn 0 1 T 1 Comparison result CMP STR Rm Rn 0010nnnnmmmm1100 If Rn and Rm have an equivalent byte 1 T 1 Comparison result DIV1 Rm Rn 0011nnnnmm...

Page 101: ...f Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 2 to 5 MUL L Rm Rn 0000nnnnmmmm0111 Rn Rm MACL 32 32 32 bits 2 to 5 MULS W Rm Rn 0010nnnnmmmm1111 Signed operation of Rn Rm MACL 16 16 32 bits 1 to 3 MULU W Rm Rn 0010nnnnmmmm1110 Unsigned operation of Rn Rm MACL 16 16 32 bits 1 to 3 NEG Rm Rn 0110nnnnmmmm1011 0 Rm Rn 1 NEGC Rm Rn 0110nnnnmmmm1010 0 Rm T Rn Borrow T 1 Borrow SUB Rm Rn 0011nnnnmmmm10...

Page 102: ...011Rn Rm Rn 1 OR imm R0 11001011iiiiiiii R0 imm R0 1 OR B imm R0 GBR 11001111iiiiiiii R0 GBR imm R0 GBR 3 TAS B Rn 0100nnnn00011011 If Rn is 0 1 T 1 MSB of Rn 4 Test result TST Rm Rn 0010nnnnmmmm1000Rn Rm if the result is 0 1 T 1 Test result TST imm R0 11001000iiiiiiii R0 imm if the result is 0 1 T 1 Test result TST B imm R0 GBR 11001100iiiiiiii R0 GBR imm if the result is 0 1 T 3 Test result XOR ...

Page 103: ... Rm Rn 0100nnnnmmmm1100 Rn 0 Rn Rm Rn Rn 0 Rn Rm MSB Rn 1 SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLD Rm Rn 0100nnnnmmmm1101 Rn 0 Rn Rm Rn Rn 0 Rn Rm 0 Rn 1 SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn 2 Rn 1 SHLR2 Rn 0100nnnn00001001 Rn 2 Rn 1 SHLL8 Rn 0100nnnn00011000 Rn 8 Rn 1 SHLR8 Rn 0100nnnn000...

Page 104: ...C if T 0 nop 3 1 BT S disp 10001101dddddddd Delayed branch if T 1 disp 2 PC PC if T 0 nop 2 1 BRA disp 1010dddddddddddd Delayed branch disp 2 PC PC 2 BRAF Rm 0000mmmm00100011 Delayed branch Rm PC PC 2 BSR disp 1011dddddddddddd Delayed branch PC PR disp 2 PC PC 2 BSRF Rm 0000mmmm00000011 Delayed branch PC PR Rm PC PC 2 JMP Rm 0100mmmm00101011 Delayed branch Rm PC 2 JSR Rm 0100mmmm00001011 Delayed b...

Page 105: ...00mmmm10111110 Rm R3_BANK 4 LDC Rm R4_BANK 0100mmmm11001110 Rm R4_BANK 4 LDC Rm R5_BANK 0100mmmm11011110 Rm R5_BANK 4 LDC Rm R6_BANK 0100mmmm11101110 Rm R6_BANK 4 LDC Rm R7_BANK 0100mmmm11111110 Rm R7_BANK 4 LDC L Rm SR 0100mmmm00000111 Rm SR Rm 4 Rm 8 LSB LDC L Rm GBR 0100mmmm00010111 Rm GBR Rm 4 Rm 4 LDC L Rm VBR 0100mmmm00100111 Rm VBR Rm 4 Rm 4 LDC L Rm SSR 0100mmmm00110111 Rm SSR Rm 4 Rm 4 LD...

Page 106: ...ayed branch SSR SR SPC PC 5 SETS 0000000001011000 1 S 1 SETT 0000000000011000 1 T 1 1 SLEEP 0000000000011011 Sleep 4 1 STC SR Rn 0000nnnn00000010 SR Rn 1 STC GBR Rn 0000nnnn00010010 GBR Rn 1 STC VBR Rn 0000nnnn00100010 VBR Rn 1 STC SSR Rn 0000nnnn00110010 SSR Rn 1 STC SPC Rn 0000nnnn01000010 SPC Rn 1 STC R0_BANK Rn 0000nnnn10000010 R0_BANK Rn 1 STC R1_BANK Rn 0000nnnn10010010 R1_BANK Rn 1 STC R2_B...

Page 107: ...4 Rn MACL Rn 1 STS L PR Rn 0100nnnn00100010 Rn 4 Rn PR Rn 1 TRAPA imm 11000011iiiiiiii Unconditional trap exception occurs 2 8 Notes The table shows the minimum number of clocks required for execution In practice the number of execution cycles will be increased in the following conditions a If there is a conflict between an instruction fetch and a data access b If the destination register of a loa...

Page 108: ... Rn BRAF Rm 0000 Rn Rm 01MD MOV B Rm R0 Rn MOV W Rm R0 Rn MOV L Rm R0 Rn MUL L Rm Rn 0000 0000 00MD 1000 CLRT SETT 0000 0000 01MD 1000 CLRS SETS 0000 0000 Fx 1001 0000 0000 Fx 1010 NOP DIV0U CLRMAC 0000 0000 Fx 1011 0000 Rn Fx 1000 RTE 0000 Rn Fx 1001 RTS SLEEP MOVT Rn 0000 Rn Fx 1010 0000 Rn Fx 1011 STS MACH Rn STS MACL Rn STS PR Rn LDTLB 0000 Rn Rm 11MD MOV B R0 Rm Rn MOV W R0 Rm Rn MOV L R0 Rm ...

Page 109: ...MD 0011 STC L R0_BANK Rn STC L R1_BANK Rn STC L R2_BANK Rn STC L R3_BANK Rn 0100 Rn 11MD 0011 STC L R4_BANK Rn STC L R6_BANK Rn 0100 Rn Fx 0100 ROTL Rn STC L R5_BANK Rn ROTCL Rn 0100 Rn Fx 0101 ROTR Rn CMP PL Rn ROTCR Rn 0100 Rm Fx 0110 LDS L Rm MACH LDS L Rm MACL LDS L Rm PR STC L R7_BANK Rn 0100 Rm 00MD 0111 LDC L Rm SR 0100 Rm 01MD 0111 LDC L Rm SPC LDC L Rm GBR LDC L Rm VBRLDC L Rm SSR 0100 Rm...

Page 110: ...n NEG Rm Rn 0110 Rn Rm 11MD EXTU B Rm Rn EXTU W Rm Rn EXTS B Rm Rn EXTS W Rm Rn 0111 Rn imm ADD imm 8 Rn 1000 00MD Rn disp MOV B R0 disp 4 Rn MOV W R0 disp 4 Rn 1000 01MD Rm disp MOV B disp 4 Rm R0 MOV W disp 4 Rm R0 1000 10MD imm disp BT disp 8 BF disp 8 1000 11MD imm disp CMP EQ imm 8 R0 BT S disp 8 BF S disp 8 1001 Rn disp MOV W disp 8 PC Rn 1010 disp BRA disp 12 1011 disp BSR disp 12 1100 00MD...

Page 111: ...y Mapping from virtual memory to physical memory is handled by the MMU The MMU is normally controlled by the operating system switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion Switching of physical memory is performed via secondary storage etc The virtual memory system that came into being in this way is particularly e...

Page 112: ...d flexibly by software The MMU has two methods of mapping from virtual memory to physical memory a paging method using fixed length address translation and a segment method using variable length address translation With the paging method the unit of translation is a fixed size address space usually of 1 to 64 kbytes called a page In the following text the address space in virtual memory is referre...

Page 113: ...the upper three bits of an address in these areas with 0s creates the address in the corresponding physical address space If the CE bit of the CCR1 register is set to 1 access via the cache is enabled When the cache is used either the copy back or write through mode is selected for write access via the WT bit in CCR1 If these areas are mapped to the on chip module control register area in area 1 i...

Page 114: ...dress translation not possible Area P2 non cacheable address translation not possible Area P3 cacheable address translation possible Area P4 non cacheable address translation not possible Address error H 0000 0000 H 8000 0000 H FFFF FFFF H 0000 0000 Privileged mode User mode Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 7 Area 6 External address space 256 256 Figure 3 2 Virtual Address Space MMUC...

Page 115: ...0 0000 H 8000 0000 H FFFF FFFF H 0000 0000 Privileged mode User mode Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 7 Area 6 External address space Figure 3 3 Virtual Address Space MMUCR AT 0 H F000 0000 H F100 0000 H F200 0000 H F300 0000 H F400 0000 H FFFF FFFF H FC00 0000 Reserved area Reserved area Cache address array Cache data array TLB address array TLB data array H E000 0000 Control regist...

Page 116: ...re information see section 3 6 Memory Mapped TLB The area from H FC00 0000 to H FFFF FFFF is reserved for the on chip module control registers For more information see section 24 List of Registers Physical Address Space This LSI supports a 29 bit physical address space As shown in figure 3 5 the physical address space is divided into eight areas Area 1 is mapped to the on chip module control regis...

Page 117: ... address are ignored as shadow areas For details refer to section 7 Bus State Controller BSC For example address H 00001000 in the P0 area address H 80001000 in the P1 area address H A0001000 in the P2 area and address H C0001000 in the P3 area are all mapped to the same physical memory If these addresses are accessed while the cache is enabled the upper three bits are always cleared to 0 to guara...

Page 118: ...3 2 1 Page Table Entry Register High PTEH The page table entry register high PTEH register residing at address H FFFFFFF0 which consists of a virtual page number VPN and ASID The VPN set is the VPN of the virtual address at which the exception is generated in case of an MMU exception or address error exception When the page size is 4 kbytes the VPN is the upper 20 bits of the virtual address but i...

Page 119: ...PN R W Number of Physical Page 9 8 7 6 5 4 3 2 1 0 V PR SZ C D SH 0 0 0 R R W R R W R W R W R W R W R Page Management Information For more details see section 3 3 TLB Functions 3 2 3 Translation Table Base Register TTB The translation table base register TTB residing at address H FFFFFFF8 which points to the base address of the current page table The hardware does not set any value in TTB automati...

Page 120: ...ess at which the exception occurred are checked If all ways are valid 1 is added to RC if there is one or more invalid way they are set by priority from way 0 in the order way 0 way 1 way 2 and way 3 In the event of an MMU exception other than a TLB miss exception the way which caused the exception is set in RC 3 0 R Reserved These bits are always read as 0 The write value should always be 0 2 TF ...

Page 121: ...ier and the control information for the page which is the unit of address translation Figure 3 6 shows the overall TLB configuration The TLB is 4 way set associative with 128 entries There are 32 entries for each way Figure 3 7 shows the configuration of virtual addresses and TLB entries Entry 1 Address array Data array Entry 0 Entry 1 Entry 31 Ways 0 to 3 Ways 0 to 3 VPN 11 10 VPN 31 17 ASID 7 0 ...

Page 122: ...the ASID in PTEH when address comparison is performed SH Share status bit 0 Page not shared between processes 1 Page shared between processes SZ Page size bit 0 1 kbyte page 1 4 kbyte page V Valid bit Indicates whether entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not affected by a manual reset PPN Physical page number Upper 22 bits of physical address PPN bits 11 to10 are not ...

Page 123: ... ASID bits 4 to 0 to generate a 5 bit index number The first method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space multiple virtual memory and a specific entry is selected by indexing of each process In single virtual memory mode MMUCR SV 1 IX bit should be set to 0 Figures 3 8 and 3 9 show the indexing schemes 31...

Page 124: ...is described below It is necessary to ensure that this kind of setting is not made by software 1 If there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID H FF when one is in the shared state SH 1 and the other in the non shared state SH 0 then if the ASID in PTEH is set to H FF there is a possibility of simultaneous TLB ...

Page 125: ... are compared when there is no sharing between processes SH 0 but not when there is sharing SH 1 When single virtual memory is supported MMUCR SV 1 and privileged mode is engaged SR MD 1 all process resources can be accessed This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged The objects of address comparison are shown in figure 3 10 SH 1 o...

Page 126: ...mapped set the C bit to 0 The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory Attempts at non permitted accesses result in TLB protection violation exceptions Access states designated by the D C and PR bits are shown in table 3 1 Table 3 1 Access States Designated by D C and PR Bits Privileged Mode User Mode Reading Writing Reading Writi...

Page 127: ...re not generated in the MMU disabled state with the AT bit cleared to 0 use in the disabled state must be avoided with software that does not use the MMU 2 TLB entry recording deletion and reading TLB entry recording can be done in two ways by using the LDTLB instruction or by writing directly to the memory mapped TLB For TLB entry deletion and reading the memory allocation TLB can be accessed See...

Page 128: ...Registers Consequently if the LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine TLB entry recording is possible Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR As the LDTLB instruction changes address translation information there is a risk of destroying address translation information if this instruction is issued in th...

Page 129: ... not be the same as the virtual address bits 12 to 10 For example assume that with 1 kbyte page TLB entries TLB entries for which the following translation has been performed are recorded in two TLBs Virtual address 1 H 00000000 physical address H 00000C00 Virtual address 2 H 00000C00 physical address H 00000C00 Virtual address 1 is recorded in cache entry H 000 and virtual address 2 in cache entr...

Page 130: ... expansion ensure that the VPN bits 20 to 10 are the same When using a 4 kbyte page Virtual address 31 VPN 0 12 13 11 10 Offset Physical address 28 PPN 0 Offset Virtual address 12 to 4 Physical address 28 to 10 Cache When using a 1 kbyte page Virtual address 31 VPN 0 10 11 12 13 Offset Physical address 28 PPN 0 10 11 12 13 Offset Virtual address 12 to 4 Physical address 28 to 10 Cache 12 13 11 10 ...

Page 131: ... If the exception occurred in a delay slot the PC value indicating the address of the related delayed branch instruction is written to the SPC 5 The contents of the status register SR at the time of the exception are written to the save status register SSR 6 The mode MD bit in SR is set to 1 to place the privileged mode 7 The block BL bit in SR is set to 1 to mask any further exception requests 8 ...

Page 132: ...causing the exception is written to the TEA register 3 Either exception code H 0A0 for a load access or H 0C0 for a store access is written to the EXPEVT register 4 The PC value indicating the address of the instruction in which the exception occurred is written into SPC if the exception occurred in a delay slot the PC value indicating the address of the related delayed branch instruction is writt...

Page 133: ...he mode MD bit in SR is set to 1 to place the privileged mode 7 The block BL bit in SR is set to 1 to mask any further exception requests 8 The RB bit in SR is set to 1 9 The way number causing the exception is written to RC in MMUCR 10 Execution branches to the address obtained by adding the value of the VBR contents and H 00000100 and the TLB protection violation exception handler starts Softwar...

Page 134: ...instruction is written to the SPC 5 The contents of SR at the time of the exception are written to SSR 6 The MD bit in SR is set to 1 to place the privileged mode 7 The BL bit in SR is set to 1 to mask any further exception requests 8 The RB bit in SR is set to 1 9 The way that caused the exception is set in the RC field in MMUCR 10 Execution branches to the address obtained by adding the value of...

Page 135: ...ception TLB protection violation exception PR TLB protection violation exception R W R W R W R W PR TLB invalid exception TLB miss exception CPU address error VPNs match No No No No Non cacheable Yes Cacheable Yes Yes Yes Yes Yes No Address error Yes No No User mode Privileged mode 01 11 00 10 00 01 10 11 W W W W R R R R Figure 3 13 MMU Exception Generation Flowchart ...

Page 136: ...ng the way bits 9 to 8 and H F2 to indicate address array access bits 31 to 24 The IX bit in MMUCR indicates whether an EX OR is taken of the entry address and ASID The following two operations can be used on the address array 1 Address array read VPN V and ASID are read from the TLB entry corresponding to the entry address and way set in the address field 2 TLB address array write The data specif...

Page 137: ...10 9 8 7 0 1 2 31 10 8 7 0 6 6 5 4 3 2 1 0 0 0 VPN 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 1 TLB address array access Read access Write access 2 TLB data array access Read write access 6 VPN W 0 VPN 0 0 VPN 0 V ASID VPN W 0 VPN V ASID VPN W PPN X V X PR SZ C D SH X PPN Physical page number PR Protection key field C Cacheable bit SH Share status bit VPN Virtual page number X 0 for read don t care bit for w...

Page 138: ...try The bit order indicated in the data field in figure 3 14 2 is read R0 specifies the address and the data section of a selected entry is read to R1 R0 H F300 4300 VPN 16 12 B 00100 Way 3 MOV L R0 R1 3 7 Usage Note The following operations should be performed in the P1 or P2 areas In addition when the P0 P3 or U0 areas are accessed consecutively this access includes instruction fetching the inst...

Page 139: ...ata and uses a 4 way set associative system It is composed of four ways banks and each of which is divided into an address section and a data section Note that the following sections will be described for the 32 kbyte mode as an example For other cache size modes change the number of entries and size way according to table 4 1 Each of the address and data sections is divided into 512 entries The e...

Page 140: ...The tag address is not initialized by either a power on or manual reset Data Array Holds a 16 byte instruction or data Entries are registered in the cache in line units 16 bytes The data array is not initialized by a power on or manual reset LRU With the 4 way set associative system up to four instructions or data with the same entry address can be registered in the cache When an entry is register...

Page 141: ... 000011 001011 100001 101001 101011 2 000110 000111 001111 010110 011110 011111 1 111000 111001 111011 111100 111110 111111 0 4 2 Register Descriptions The cache has the following registers For details on register addresses and register states during each process refer to section 24 List of Registers Cache control register 1 CCR1 Cache control register 2 CCR2 Cache control register 3 CCR3 ...

Page 142: ...its are always read as 0 The write value should always be 0 3 CF 0 R W Cache Flush Writing 1 flushes all cache entries clears the V U and LRU bits of all cache entries to 0 This bit is always read as 0 Write back to external memory is not performed when the cache is flushed 2 CB 0 R W Write Back Indicates the cache s operating mode for space P1 0 Write through mode 1 Write back mode 1 WT 0 R W Wri...

Page 143: ...e way that is to be replaced when the cache is missed by a prefetch instruction On the other hand when the cache is hit by a prefetch instruction new data is not loaded into the cache and the valid entry is held For example a prefetch instruction is issued while bits W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0 the cache is hit and new data is not load...

Page 144: ...on while in cache lock mode and when bits W3LOAD and W3LOCK in CCR2 are set to 1 the data is always loaded into way 3 Under any other condition the prefetched data is loaded into the way to which LRU points 7 to 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 W2LOAD W2LOCK 0 0 R W R W Way 2 Load W2LOAD Way 2 Lock W2LOCK When the cache is missed by a prefetch i...

Page 145: ...Determined by LRU table 4 2 1 0 0 Determined by LRU table 4 2 1 0 1 Determined by LRU table 4 5 1 1 0 Determined by LRU table 4 6 1 1 1 Determined by LRU table 4 7 Notes Don t care W3LOAD and W2LOAD should not be set to 1 at the same time Table 4 5 LRU and Way Replacement when W2LOCK 1 and W3LOCK 0 LRU Bits 5 to 0 Way to be Replaced 000000 000001 000100 010100 100000 100001 110000 110100 3 000011 ...

Page 146: ...orporated in the LSI correct operation cannot be guaranteed Note that programs that change the contents of the CCR3 register should be placed in un cached address space In addition note that all cache entries must be invalidated by setting the CF bit of the CCR1 to 1 before accessing the cache after the CCR3 is modified Bit Bit Name Initial Value R W Description 31 to 24 0 R Reserved These bits ar...

Page 147: ...ry and the tag address of that entry is read The virtual address bits 31 to 10 of the access to memory and the physical address tag address read from the address array are compared The address comparison uses all four ways When the comparison shows a match and the selected entry is valid V 1 a cache hit occurs When the comparison does not show a match or the selected entry is not valid V 0 a cache...

Page 148: ... Prefetch Miss Instructions and data are not transferred from the cache to the CPU The way that is to be replaced is shown in table 4 2 The other operations are the same as those for a read miss 4 3 4 Write Access Write Hit In a write access in write back mode the data is written to the cache and no external memory write cycle is issued The U bit of the entry that has been written to is set to 1 a...

Page 149: ...te back buffer can hold one line of cache data 16 bytes and its physical address Figure 4 3 shows the configuration of the write back buffer Longword 0 Longword 1 Longword 2 Longword 3 PA 31 to 4 PA 31 to 4 Longword 0 to 3 Physical address written to external memory One line of cache data to be written to external memory Figure 4 3 Write Back Buffer Configuration 4 3 6 Coherency of Cache and Exter...

Page 150: ...ad Read the tag address LRU bits U bit and V bit for the entry that corresponds to the entry address and way specified by the address field of the read instruction In reading the associative operation is not performed regardless of whether the associative bit A bit specified in the address is 1 or 0 Address Array Write non Associative Operation Write the tag address LRU bits U bit and V bit specif...

Page 151: ...ngword position within the 16 byte line W for selecting the way and H F1 for indicating data array access As for L 00 indicates longword 0 01 indicates longword 1 10 indicates longword 2 and 11 indicates longword 3 As for W 00 indicates way 0 01 indicates way 1 10 indicates way 2 and 11 indicates way 3 Since access size of the data array is fixed at longword bits 1 and 0 of the address field shoul...

Page 152: ...3 12 4 3 0 1111 0000 W Entry address 2 A 31 10 4 3 0 LRU 2 X X 9 Tag address 31 to 10 U V 1 31 24 23 15 14 13 12 4 3 0 1111 0001 W Entry address 1 2 L b Data specification 31 0 Longword Don t care bit X 0 for read don t care for write 0 0 0 0 0 2 0 0 Figure 4 4 Specifying Address and Data for Memory Mapped Cache Access 32 kbyte Mode Table 4 8 Address Format Based on Size of Cache to be Assigned to...

Page 153: ...y is written back and the V and U bits specified by the write data are written to In the following example the write data is specified in R0 and the address is specified in R1 32 kbyte mode R0 H 0000 0000 LRU H 000 U 0 V 0 R1 H F000 2080 Way 1 Entry B 000001000 A 0 MOV L R0 R1 To invalidate all entries and ways write 0 to the following addresses 32 kbyte mode 2 048 writes Addresses F000 0000 F000 ...

Page 154: ... L R0 R1 In the following example an address 32 bit to be purged is specified in R0 MOV L H 00001FF0 R1 32 kbyte mode H 00000FF0 in the 16 kbyte mode AND R0 R1 The entry address is fetched MOV L H 00000008 R2 OR R1 R2 The start is set to H F0 and the A bit to 1 MOV L H 1FFFFC00 R3 AND R0 R3 The tag address is fetched U V 0 MOV L R3 R2 Associative purge The above operation should be performed using...

Page 155: ...ed processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program A reset input can terminate the normal program execution and pass control to the reset vector after register initialization This reset operation can also be regarded as an exception handling This section describes an overview of the exception handling oper...

Page 156: ...gned to address H FFFFFFD0 and consists of the 8 bit immediate data imm of the TRAPA instruction TRA is automatically specified by the hardware when the TRAPA instruction is executed Only bits 9 to 2 of the TRA can be re written using the software Bit Bit Name Initial Value R W Description 31 to 10 R Reserved These bits are always read as 0 The write value should always be 0 9 to 2 TRA R W 8 bit I...

Page 157: ...read as 0 The write value should always be 0 11 to 0 EXPEVT R W 12 bit Exception Code Note Initialized to H 000 at power on reset and H 020 at manual reset 5 1 3 Interrupt Event Register INTEVT INTEVT is assigned to address H FFFFFFD8 and consists of a 12 bit exception code Exception codes to be specified in INTEVT are those for interrupt requests These exception codes are automatically specified ...

Page 158: ...nnot be modified using the software Bit Bit Name Initial Value R W Description 31 to 12 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 INTEVT2 R 12 bit Exception Code 5 1 5 Exception Address Register TEA TEA is assigned to address H FFFFFFFC and stores the logical address for an exception occurrence when an exception related to memory accesses occurs TEA ca...

Page 159: ... to 0 of the exception event EXPEVT or interrupt event INTEVT or INTEVT2 register 7 If a TRAPA instruction is executed an 8 bit immediate data specified by the TRAPA instruction is set to TRA For an exception related to memory accesses the logic address where the exception occurred is written to TEA 1 8 Instruction execution jumps to the designated exception vector address to invoke the handler ro...

Page 160: ... exception codes for interrupt requests Table 5 1 lists exception codes for resets and general exceptions 5 2 4 Exception Request and BL Bit Multiple Exception Prevention The BL bit in SR is set to 1 when a reset or exception is accepted While the BL bit is set to 1 acceptance of general exceptions is restricted as described below making it possible to effectively prevent multiple exceptions from ...

Page 161: ...ed is completed the next instruction address is saved to the SPC and then the exception processing is executed During a delayed branch instruction and delay slot the following operations are executed A re execution type exception detected in a delay slot is accepted before executing the delayed branch instruction A processing completion type exception detected in a delayed branch instruction or a ...

Page 162: ...eption is accepted at a time Accepting multiple exceptions sequentially results in all exception requests being processed Table 5 1 Exception Event Vectors Exception Type Current Instruction Exception Event Priority 1 Exception Order Process at BL 1 Vector Code Vector Offset Power on reset 1 1 Reset H A00 Reset Aborted Manual reset 1 2 Reset H 020 User break before instruction execution 2 0 Ignore...

Page 163: ...k I BUS break 2 5 Ignored H 1E0 H 00000100 General interrupt requests Completed DMA address error 2 6 Retained H 5C0 H 00000100 Interrupt requests Completed Interrupt requests 3 2 Retained 3 H 00000600 Notes 1 Priorities are indicated from high to low 1 being the highest and 3 the lowest A reset has the highest priority An interrupt is accepted only when general exceptions are not requested 2 For ...

Page 164: ... initialize the CPU and on chip peripheral modules and branch to the reset vector H A0000000 For details refer to the register descriptions in the relevant sections 5 3 2 General Exceptions CPU Address Error Conditions Instruction is fetched from odd address 4n 1 4n 3 Word data is accessed from addresses other than word boundaries 4n 1 4n 3 Longword is accessed from addresses other than longword b...

Page 165: ...leged instructions LDC STC RTE LDTLB SLEEP instructions that access GBR with LDC STC are not privileged instructions Types Instruction synchronous re execution type Save address An instruction address where an exception occurs Exception code H 180 Remarks None Illegal Slot Instruction Conditions When undefined code in a delay slot is decoded Delayed branch instructions JMP JSR BRA BRAF BSR BSRF RT...

Page 166: ...ditions When a break condition set in the user break controller is satisfied Types Break L bus before instruction execution Instruction synchronous re execution type Operand break L bus Instruction synchronous processing completion type Data break L bus Instruction asynchronous processing completion type I bus break Instruction asynchronous processing completion type Save address Re execution type...

Page 167: ...ransfer is performed asynchronously with the CPU instruction operation an exception is also requested asynchronously with the instruction execution For details on DMAC refer to section 8 Direct Memory Access Controller DMAC 5 3 3 General Exceptions MMU Exceptions When the address translation unit of the memory management unit MMU is valid MMU exceptions are checked after a CPU address error has be...

Page 168: ... but V 0 Types Instruction synchronous re execution type Save address Instruction fetch An instruction address to be fetched when an exception occurred Data access An instruction address where an exception occurs a delayed branch instruction address if an instruction is assigned to a delay slot Exception code An exception occurred during read H 040 An exception occurred during write H 060 Remarks ...

Page 169: ...ons A hit occurred to the TLB for a store access but D 0 Types Instruction synchronous re execution type Save address Instruction fetch An instruction address to be fetched when an exception occurred Data access An instruction address where an exception occurs a delayed branch instruction address if an instruction is assigned to a delay slot Exception code H 080 Remarks The logical address 32 bits...

Page 170: ...t the correct operation cannot be guaranteed if a re execution type exception occurs 2 In an instruction assigned at a delay slot of the RTE instruction a user break cannot be accepted 3 If the MD and BL bits of the SR register are changed by the LDC instruction an exception is accepted according to the changed SR value from the next instruction A processing completion type exception is accepted b...

Page 171: ...y 6 1 Features 16 levels of interrupt priority can be set By setting the interrupt priority registers the priorities of on chip peripheral modules and IRQ interrupts can be selected from 16 levels for individual request sources NMI noise canceller function An NMI input level bit indicates the NMI pin state By reading this bit in the interrupt exception service routine the pin state can be checked ...

Page 172: ...chdog timer UDI User debugging interface RTC Realtime clock REF Refresh request in bus state controller ICR Interrupt control register IPR Interrupt priority level setting register IRR Interrupt request register PINTER PINT interrupt enable register SR Status register Input output control Priority identifier Com parator Interrupt request SR CPU Bus interface Internal bus INTC I3 I2 I1 I0 Interrupt...

Page 173: ...ns The INTC has the following registers For details on register addresses and register states during each processing refer to section 24 List of Registers Interrupt control register 0 ICR0 Interrupt control register 1 ICR1 Interrupt control register 2 ICR2 PINT interrupt enable register PINTER Interrupt priority level setting register A IPRA Interrupt priority level setting register B IPRB Interru...

Page 174: ...2 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRA TMU0 TMU1 TMU2 RTC IPRB WDT REF Reserved Reserved IPRC IRQ3 IRQ2 IRQ1 IRQ0 IPRD PINT0 to PINT7 PINT8 to PINT15 IRQ5 IRQ4 IPRE DMAC SCIF0 SCIF2 ADC IPRF Reserved Reserved USB Reserved IPRG TPU0 TPU1 Reserved Reserved IPRH TPU2 TPU3 Reserved Reserved Note Always read as 0 The write value should always be 0 As shown in table 6 2 on chip peripheral module or...

Page 175: ...ine the NMI pin level This bit cannot be modified 0 NMI input level is low 1 NMI input level is high 14 to 9 0 R Reserved These bits are always read as 0 The write value should always be 0 8 NMIE 0 R W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal at the NMI pin is detected 0 Interrupt request is detected on falling edge of NMI input 1 Interrupt request...

Page 176: ...he NMI pin 1 All interrupt requests are masked when a low level is being input to the NMI pin 14 IRQLVL 1 R W Interrupt Request Level Detect Selects whether the IRQ3 to IRQ0 pins are enabled or disabled to be used as four independent interrupt pins This bit does not affect the IRQ4 and IRQ5 pins 0 Used as four independent interrupt request pins IRQ3 to IRQ0 1 Used as encoded 15 level interrupt pin...

Page 177: ...g edge at the rising edge at low level or at high level Bit 2n 1 Bit 2n IRQn1S IRQn0S 0 0 An interrupt request is detected at IRQn input falling edge 0 1 An interrupt request is detected at IRQn input rising edge 1 0 An interrupt request is detected at IRQn input low level 1 1 An interrupt request is detected at IRQn input high level 11 to 0 IRQ51S to IRQ00S 0 R W Legend n 0 to 5 ...

Page 178: ...are detected at high level input to the PINT pins Legend n 0 to 15 6 3 5 PINT Interrupt Enable Register PINTER PINTER is a 16 bit register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15 When all or some of these pins PINT0 to PINT15 are not used as an interrupt input a bit corresponding to a pin unused as an interrupt request should be cleared to 0 Bit Bit N...

Page 179: ...uest Indicates whether interrupt requests are input to PINT8 to PINT15 pins 0 Interrupt requests are not input to PINT8 to PINT15 pins 1 Interrupt requests are input to PINT8 to PINT15 pins 5 to 0 IRQ5R to IRQ0R 0 R W IRQn Interrupt Request Indicates whether there is interrupt request input to the IRQn pin When edge detection mode is set for IRQn an interrupt request is cleared by writing 0 to the...

Page 180: ...nerated 1 An RXI0 interrupt request is generated 4 ERI0R 0 R ERI0 Interrupt Request Indicates whether an ERI0 SCIF0 interrupt request is generated 0 An ERI0 interrupt request is not generated 1 An ERI0 interrupt request is generated 3 DEI3R 0 R DEI3 Interrupt Request Indicates whether a DEI3 DMAC interrupt request is generated 0 A DEI3 interrupt request is not generated 1 A DEI3 interrupt request ...

Page 181: ... whether an ADI ADC interrupt request is generated 0 An ADI interrupt request is not generated 1 An ADI interrupt request is generated 3 TXI2R 0 R TXI2 Interrupt Request Indicates whether a TXI2 SCIF2 interrupt request is generated 0 A TXI2 interrupt request is not generated 1 A TXI2 interrupt request is generated 2 0 R Reserved This bit is always read as 0 1 RXI2R 0 R RXI2 Interrupt Request Indic...

Page 182: ...sleep mode or standby mode with an NMI interrupt 6 4 2 IRQ Interrupts IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5 The priority level can be set by interrupt priority registers C and D IPRC and IPRD in a range from 0 to 15 When using edge sensing for IRQ interrupts clear the interrupt source by having software read 1 from the corresponding bit in IRR0 then write 0 to the bit Wh...

Page 183: ...ery peripheral clock remain unchanged for two consecutive cycles so that no transient level on the IRL pin change is detected In standby mode as the peripheral clock is stopped noise cancellation is performed using the clock for the RTC instead Therefore when the RTC is not used recovery from standby mode by means of IRL interrupts cannot be performed in standby mode The priority level of the IRL ...

Page 184: ...equest 6 4 4 PINT Interrupt PINT interrupts are input from pins PINT0 to PINT15 with a level The priority level can be set by the interrupt priority level setting register D IPRD in a range from levels 0 to 15 in the unit of PINT0 to PINT7 or PINT8 to PINT15 The PINT interrupt level should be held until the interrupt is accepted and interrupt handling is started The interrupt mask bits I3 to I0 in...

Page 185: ...ity levels 0 to 16 level 16 is the highest and level 1 is the lowest When the priority is set to level 0 that interrupt is masked and the interrupt request is ignored Tables 6 4 and 6 5 list the codes for the interrupt source and the interrupt event registers INTEVT and INTEVT2 and the order of interrupt priority Each interrupt source is assigned a unique code by INTEVT and INTEVT2 The start addre...

Page 186: ...RQ IRQ5 H 6A0 3 0 to 15 0 IPRD 7 to 4 PINT0 to PINT7 H 700 3 0 to 15 0 IPRD 15 to 12 PINT PINT8 to PINT15 H 720 3 0 to 15 0 IPRD 11 to 8 DEI0 H 800 3 High DEI1 H 820 3 DEI2 H 840 3 DMAC DEI3 H 860 3 0 to 15 0 IPRE 15 to 12 Low ERI0 H 880 3 0 to 15 0 IPRE 11 to 8 High RXI0 H 8A0 3 SCIF0 TXI0 H 8E0 3 Low ERI2 H 900 3 High RXI2 H 920 3 SCIF2 TXI2 H 960 3 0 to 15 0 IPRE 7 to 4 Low ADC ADI H 980 3 0 to...

Page 187: ... TUNI1 H 420 2 0 to 15 0 IPRA 11 to 8 TUNI2 H 440 2 High TMU2 TICPI2 H 460 2 0 to 15 0 IPRA 7 to 4 Low ATI H 480 2 High PRI H 4A0 2 RTC CUI H 4C0 2 0 to 15 0 IPRA 3 to 0 Low WDT ITI H 560 2 0 to 15 0 IPRB 15 to 12 REF RCMI H 580 2 0 to 15 0 IPRB 11 to 8 Low Notes 1 The INTEVT2 code 2 The same code as INTEVT2 is set in INTEVT 3 The code indicating an interrupt level H 200 to H 3C0 shown in table 6 ...

Page 188: ...280 3 11 IRL 3 0 0101 H 2A0 3 10 IRL 3 0 0110 H 2C0 3 9 IRL 3 0 0111 H 2E0 3 8 IRL 3 0 1000 H 300 3 7 IRL 3 0 1001 H 320 3 6 IRL 3 0 1010 H 340 3 5 IRL 3 0 1011 H 360 3 4 IRL 3 0 1100 H 380 3 3 IRL 3 0 1101 H 3A0 3 2 IRL 3 0 1110 H 3C0 3 1 IRQ IRQ4 H 680 3 0 to 15 0 IPRD 3 to 0 IRQ5 H 6A0 3 0 to 15 0 IPRD 7 to 4 PINT PINT0 to PINT 7 H 700 3 0 to 15 0 IPRD 15 to 12 PINT8 to PINT 15H 720 3 0 to 15 0...

Page 189: ...PU1 TPI1 H C20 3 0 to 15 0 IPRG 11 to 8 TPU2 TPI2 H C80 3 0 to 15 0 IPRH 15 to 12 TPU3 TPI3 H CA0 3 0 to 15 0 IPRH 11 to 8 TMU0 TUNI0 H 400 2 0 to 15 0 IPRA 15 to 12 TMU1 TUNI1 H 420 2 0 to 15 0 IPRA 11 to 8 TMU2 TUNI2 H 440 2 0 to 15 0 IPRA 7 to 4 High TICPI2 H 460 2 Low RTC ATI H 480 2 0 to 15 0 IPRA 3 to 0 High PRI H 4A0 2 CUI H 4C0 2 Low WDT ITI H 560 2 0 to 15 0 IPRB 15 to 12 REF RCMI H 580 2...

Page 190: ...t priority level setting registers A to H IPRA to IPRH Lower priority interrupts are held pending If two of these interrupts have the same priority level or if multiple interrupts occur within a single module the interrupt with the highest priority is selected according to tables 6 4 and 6 5 3 The priority level of the interrupt selected by the interrupt controller is compared with the interrupt m...

Page 191: ...mp is not a delayed branch The interrupt handler may branch with INTEVT or INTEVT2 value as its offset in order to identify the interrupt source This enables it to branch to the handling routine for the individual interrupt source Notes 1 The interrupt mask bits I3 to I0 in the status register SR are not changed by acceptance of an interrupt in this LSI 2 The interrupt source flag should be cleare...

Page 192: ...NMI low SR BL 0 or sleep mode or software standby mode NMI Level 15 interrupt I3 I0 level 14 or lower Level 14 interrupt I3 I0 level 13 or lower Level 1 interrupt I3 I0 level 0 Set interrupt source in INTEVT and INTEVT2 Save SR to SSR save PC to SPC Set BL MD RB bits in SR to 1 Branch to exception handler I3 I0 Interrupt mask bits in status register SR Figure 6 3 Interrupt Operation Flowchart ...

Page 193: ...externally Thus keep the following note in mind when designing the system Level interrupt The level interrupt request should be held until the CPU accepts it The level interrupt request needs to be cleared released within the specific interrupt handler If the level interrupt request is not held the operation may branch to the interrupt handling routine when the value in INTEVT 2 becomes H 000 When...

Page 194: ...Rev 2 00 09 03 page 148 of 690 ...

Page 195: ...select the data bus width 8 16 or 32 bits for each address space Controls the insertion of the wait state for each address space Controls the insertion of the wait state for each read access and write access Can set the independent idling cycle in the continuous access for five cases read write in same space different space read read in same space different space the first cycle is a write access ...

Page 196: ...Address data controller Area controller CMNCR CSnBCR CSnWCR SDCR RTCSR RTCNT RTCOR Comparator CS0 CS2 CS3 CS4 CS5A CS5B CS6A CS6B BS RD RD WR WE3 to WE0 RASU RASL CASU CASL AH CKE DQMUU DQMUL DQMLU DQMLL WAIT A25 to 0 D31 to 0 Internal address bus Internal data bus Note CSnBCR CSnWCR n 0 2 3 4 5A 5B 6A 6B Legend CSnBCR Area n bus control register CSnWCR Area n wait control register SDCR SDRAM cont...

Page 197: ...is set Selects D31 to D24 when an SDRAM space is set WE2 DQMUL O Indicates that D23 to D16 are being written to when a normal space is set Selects D23 to D16 when a byte selection SRAM space is set Selects D23 to D16 when an SDRAM space is set WE1 DQMLU O Indicates that D15 to D8 are being written to when a normal space and address data multiplex I O space are set Selects D15 to D8 when a byte sel...

Page 198: ...n table 7 2 this LSI can be connected directly to eight areas of memory and it outputs chip select signals CS0 CS2 to CS4 CS5A CS5B CS6A and CS6B for each of them CS0 is asserted during area 0 access CS5B is asserted during area 5B access When an SDRAM is connected to area 2 or area 3 RASU RASL CASU CASL DQMUU DQMUL DQMLU and DQMLL are asserted 7 3 1 Address Map The external address space has a ca...

Page 199: ...l memory 1 Address data multiplex I O MPX Byte selection SRAM H 16000000 to H 17FFFFFF H 20000000 n H 20000000 n Shadow n 1 to 6 H 18000000 to H 19FFFFFF 32 Mbytes 8 16 3 Area 6A Normal memory 1 H 18000000 to H 19FFFFFF H 20000000 n H 20000000 n Shadow n 1 to 6 H 1A000000 to H 1BFFFFFF 32 Mbytes 8 16 3 Area 6B Normal memory 1 H 1A000000 to H 1BFFFFFF H 20000000 n H 20000000 n Shadow n 1 to 6 Area ...

Page 200: ...ranslating a logical address to a physical address refer to table 7 2 P0 P1 P2 P3 P4 Area 5B CS5B Area 6B CS6B H 16000000 H 1A000000 H 1BFFFFFF Figure 7 2 Address Space 7 3 2 Memory Bus Width The memory bus width in this LSI can be set for each area In area 0 external pins can be used to select byte 8 bits word 16 bits or longword 32 bits on power on reset The correspondence between the external p...

Page 201: ...rs are allocated This area has no shadow space 7 4 Register Descriptions The BSC has the following registers Refer to section 24 List of Registers for the details of the addresses of these registers and the state of registers in each operating mode Do not access spaces other than CS0 until the termination of the setting the memory interface Common control register CMNCR Bus control register for CS...

Page 202: ...r in SDRAM is written to For details refer to section 7 8 10 Power On Sequence 7 4 1 Common Control Register CMNCR CMNCR is a 32 bit register that controls the common items for each area Do not access external memory other than area 0 until the CMNCR register initialization is complete Bit Bit Name Initial Value R W Description 31 to 8 0 R Reserved These bits are always read as 0 The write value s...

Page 203: ... This is a read only bit 0 The external pin for specifying endian MD5 was low level on power on reset This LSI is being operated as big endian 1 The external pin for specifying endian MD5 was high level on power on reset This LSI is being operated as little endian 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 HIZMEM 0 R W High Z Memory Control Specifies the pin s...

Page 204: ...s These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space The target access cycles are the write read cycle and write write cycle 00 No idle cycle inserted 01 1 idle cycle inserted 10 2 idle cycles inserted 11 4 idle cycles inserted 27 0 R Reserved This bit is always read as 0 The write value should always be 0 26 25 IWRWD1 IWRWD2 1 1...

Page 205: ...RRD0 1 1 R W R W Idle Cycles for Read read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space The target cycle is a read read cycle of which continuous accesses switch between different space 00 1 idle cycle inserted 01 2 idle cycles inserted 10 3 idle cycles inserted 11 5 idle cycles inserted 18 0 R Reserved This bit is al...

Page 206: ...d to only one area SDRAM should be specified for area 3 In this case area 2 should be specified as normal space Burst ROM can be specified only in area 0 and area 4 Address data multiplex I O MPX can be specified only in area 5B Byte selection SRAM can be specified only in area 4 and area 5B 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 BSZ1 BSZ0 1 1 R W R W ...

Page 207: ...e BACTV bit in the SDRAM control register 6 The initial values of the bus size assignment for areas 5B 6A and 6B after power on reset is specified to prohibited setting Therefore specify the 8 or 16 bit size before accessing these areas 7 When port A or B is used specify the bus size of all areas to 8 bits or 16 bits When the memory type is specified to an area other than the areas that can be spe...

Page 208: ...Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion 00 0 5 cycles 01 1 5 cycles 10 2 5 cycles 11 3 5 cycles 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R W R W R W R W Number of Access Wait Cycles Specify the number of cycles that are necessary for read write access 0000 0 cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cyc...

Page 209: ...id even when the number of access wait cycle is 0 0 External wait is valid 1 External wait is ignored 5 to 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 HW1 HW0 0 0 R W R W Delay Cycles from RD WEn negation to Address CSn negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation 00 0 5 cycles 01 1 5 cycles 10 2 5 cycles...

Page 210: ...010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Setting prohibited 1110 Setting prohibited 1111 Setting prohibited 6 WM 0 R W External Wait Mask Specification Specify whether or not the external wait input is valid The specification by this bit is valid even when the number of access ...

Page 211: ...ry for write access 000 The same cycles as WR3 to WR0 setting read access wait 001 0 cycle 010 1 cycles 011 2 cycles 100 3 cycles 101 4 cycles 110 5 cycles 111 6 cycles 15 to 13 0 R Reserved These bits are always read as 0 The write value should always be 0 12 11 SW1 SW0 0 0 R W R W Number of Delay Cycles from Address CSn Assertion to RD WEn Assertion Specify the number of delay cycles from addres...

Page 212: ...ting prohibited 1110 Setting prohibited 1111 Setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait is valid 1 External wait is ignored 5 to 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 HW1 H...

Page 213: ...ad as 0 The write value should always be 0 18 17 16 WW2 WW1 WW0 0 0 0 R W R W R W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access 000 The same cycles as WR3 to WR0 setting read access wait 001 0 cycle 010 1 cycles 011 2 cycles 100 3 cycles 101 4 cycles 110 5 cycles 111 6 cycles 15 to 13 0 R Reserved These bits are always read as 0 The write value...

Page 214: ...tting prohibited 1110 Setting prohibited 1111 Setting prohibited 6 WM 0 R W External Wait Mask Specification Specify whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait is valid 1 External wait is ignored 5 to 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 HW1 HW...

Page 215: ...0 cycle 01 1 cycle 10 2 cycles 11 3 cycles 15 to 11 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R W R W R W R W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first read write access cycle 0000 0 cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycle...

Page 216: ...Description 31 to 18 0 R Reserved These bits are always read as 0 The write value should always be 0 17 16 BW1 BW0 0 0 R W R W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access 00 0 cycle 01 1 cycle 10 2 cycles 11 3 cycles 15 to 13 0 R Reserved These bits are always read as 0 The write value should always be 0 12 ...

Page 217: ...01 Setting prohibited 1110 Setting prohibited 1111 Setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait is valid 1 External wait is ignored 5 to 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0...

Page 218: ...erved This bit is always read as 1 The write value should always be 1 9 0 R Reserved This bit is always read as 0 The write value should always be 0 8 7 A2CL1 A2CL0 1 0 R W R W CAS Latency for Area 2 Specify the CAS latency for area 2 00 Setting prohibited 01 2 cycles 10 3 cycles 11 Setting prohibited 6 to 0 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 219: ...s common 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 12 0 R Reserved This bit is always read as 0 The write value should always be 0 11 10 TRCD1 TRCD0 0 1 R W R W Number of Cycles from ACTV Command to READ A WRIT A Command Specify the number of minimum cycles from issuing ACTV command to issuing READ A WRIT A command The setting for areas 2 and 3 is common 00 1 cycle 01 2 cycles 10 3 cycles 11 ...

Page 220: ... Release to ACTV Command Specify the number of cycles from issuing the REF command or releasing self refresh to issuing the ACTV command The setting for areas 2 and 3 is common 00 3 cycles 01 4 cycles 10 6 cycles 11 9 cycles Note Specify area 3 as SDRAM when only one area is connected with SDRAM In this case specify area 2 as normal space 7 4 4 SDRAM Control Register SDCR SDCR specifies the method...

Page 221: ...lumn address for area 2 00 8 bits 01 9 bits 10 10 bits 11 Setting prohibited 15 to 13 0 R Reserved These bits are always read as 0 The write value should always be 0 12 SLOW 0 R W Low Frequency Mode Specifies the output timing of command address and write data for SDRAM and the latch timing of read data from SDRAM Setting this bit makes the hold time for command address write and read data extende...

Page 222: ...ved This bit is always read as 0 The write value should always be 0 8 BACTV 0 R W Bank Active Mode Specifies to access whether in auto precharge mode using READA and WRITA commands or in bank active mode using READ and WRIT commands 0 Auto precharge mode using READA and WRITA commands 1 Bank active mode using READ and WRIT commands Note Bank active mode can be used only when either the upper or lo...

Page 223: ... various items about refresh for SDRAM This register only accepts 32 bit writing to prevent incorrect writing In this case the upper 16 bits of the data must be H A55A otherwise writing cannot be performed When reading the upper 16 bits are read as H 0000 RTCSR Bit Bit Name Initial Value R W Description 31 to 8 0 R Reserved 7 CMF 0 R W Compare Match Flag 0 Clearing condition When 0 is written in C...

Page 224: ...φ 1024 110 Bφ 2048 111 Bφ 4096 2 1 0 RRC2 RRC1 RRC0 0 0 0 R W R W R W Refresh Count Specify the number of continuous refresh cycles when the refresh request occurs after the coincidence of the values of the refresh timer counter RTCNT and the refresh time constant register RTCOR These bits can make the period of occurrence of refresh long 000 Once 001 Twice 010 4 times 011 6 times 100 8 times 101 ...

Page 225: ...leared to 0 This register only accepts 32 bit writing to prevent incorrect writing In this case the upper 16 bits of the data must be H A55A otherwise writing cannot be performed When reading the upper 16 bits are read as H 0000 When the RFSH bit in SDCR is 1 a memory refresh request is issued by this matching signal This request is maintained until the refresh operation is performed If the reques...

Page 226: ...ports big endian in which the 0 address is the most significant byte MSByte in the byte data and little endian in which the 0 address is the least significant byte LSByte in the byte data Endian is specified on power on reset by the external pin MD5 When MD5 pin is low level on power on reset the endian will become big endian and when MD5 pin is high level on power on reset the endian will become ...

Page 227: ...Byte access at 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Longword access at 0 Data 31 to Data 24 Data 23 to Data 16 Data 15 to Data 8 Data 7 to Data 0 Assert Ass...

Page 228: ... 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert Assert 1st time at 0 Data 31 to Data 24 Data 23 to Data 16 Assert Assert Longword access at 0 2nd time at 2 Data 15 to Data 8...

Page 229: ...1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 1st time at 0 Data 15 to Data 8 Assert 2nd time at 1 Data 7 to Data 0 Assert Word access at 2 1st time at 2 Data 15 to Data 8 Assert 2nd time at 3 Data 7 to Data 0 Assert Longword access at 0 1st time at 0 Data 31 to Data 24 Assert 2nd time at 1 Data 23 to Data 16 Assert 3rd...

Page 230: ...L Byte access at 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Longword access at 0 Data 31 to Data 24 Data 23 to Data 16 Data 15 to Data 8 Data 7 to Data 0 Assert A...

Page 231: ...at 0 Data 7 to Data 0 Assert Byte access at 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data7 to Data 0 Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert Assert 1st time at 0 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Longword access at 0 2nd time at 1 Data 31 to Data 24 ...

Page 232: ... 1 Data 7 to Data 0 Assert Byte access at 2 Data 7 to Data 0 Assert Byte access at 3 Data 7 to Data 0 Assert Word access at 0 1st time at 0 Data 7 to Data 0 Assert 2nd time at 1 Data 15 to Data 8 Assert Word access at 2 1st time at 2 Data 7 to Data 0 Assert 2nd time at 3 Data 15 to Data 8 Assert Longword access at 0 1st time at 0 Data 7 to Data 0 Assert 2nd time at 1 Data 15 to Data 8 Assert 3rd t...

Page 233: ...writing only the WEn signal for the byte to be written is asserted Read write for cache fill or writeback follows the selected bus width and transfers a total of 16 bytes continuously The bus is not released during this transfer For cache misses that occur during byte or word operand accesses or branching to odd word boundaries the fill is always performed by longword accesses on the chip external...

Page 234: ...e 188 of 690 CKIO A25 to A0 RD WR Data DACK CS T1 T2 T1 T2 RD WEn BS Data Read Write Figure 7 3 Continuous Access for Normal Space No Wait WM Bit in CSnWCR 1 16 Bit Bus Width Longword Access No Wait State between Cycles ...

Page 235: ...Rev 2 00 09 03 page 189 of 690 CKIO A25 to A0 RD Data WEn Data DACKn WAIT CSn T1 T2 Taw T1 T2 Read Write Figure 7 4 Continuous Access for Normal Space No Wait One Wait State between Cycles ...

Page 236: ...16 bit and 8 bit data width SRAM respectively A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 7 5 Example of 32 Bit Data Width SRAM Connection ...

Page 237: ... CSn RD D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 7 6 Example of 16 Bit Data Width SRAM Connection A16 A0 CS OE I O7 I O0 WE A16 A0 CSn RD D7 D0 WE0 This LSI 128k 8 bit SRAM Figure 7 7 Example of 8 Bit Data Width SRAM Connection ...

Page 238: ...ndently in read access and in write access The areas other than 4 5A and 5B have common access wait for read cycle and write cycle The specified number of Tw cycles is inserted as wait cycles in a normal space access shown in figure 7 8 T1 CKIO A25 to A0 CSn RD WR RD Data WEn Data BS Tw Read Write T2 DACKn Note The waveform for DACKn is when active low is specified Figure 7 8 Wait Timing for Norma...

Page 239: ...s a software wait The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle T1 CKIO A25 to A0 CSn RD WR RD Data WEn Data WAIT Tw Tw Twx T2 Read Write BS Wait states inserted by WAIT signal DACKn Note The waveform for DACKn is when active low is specified Figure 7 9 Wait State Timing for Normal Space Access Wait State Insertion by WAITSignal ...

Page 240: ... an external device can be obtained Figure 7 10 shows an example A Th cycle and a Tf cycle are added before and after an ordinary cycle respectively In these cycles RD and WEn are not asserted while other signals are asserted The data output is prolonged to the Tf cycle and this prolongation is useful for devices with slow writing operations T1 CKIO A25 to A0 CSn RD WR RD Data WEn Data BS Th Read ...

Page 241: ...rformed from cycle Ta2 to cycle Ta3 Because cycle Ta1 has a high impedance state collisions of addresses and data can be avoided without inserting idle cycles even in continuous accesses Address output is increased to 3 cycles by setting the MPXW bit to 1 in CS5BWCR The RD WR signal is output at the same time as the CSn signal it is high in the read cycle and low in the write cycle The data cycle ...

Page 242: ...16 CS5B RD WR RD D15 to D0 WEn D15 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note The waveform for DACKn is when active low is specified Figure 7 12 Access Timing for MPX Space Address Cycle Wait 1 Data Cycle No Wait ...

Page 243: ...D15 to D0 WEn D15 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note The waveform for DACKn is when active low is specified Figure 7 13 Access Timing for MPX Space Address Cycle Access Wait 1 Data Cycle Wait 1 External Wait 1 ...

Page 244: ...ll the signals other than CS2 and CS3 are common to all areas and signals other than CKE are valid when CS2 or CS3 is asserted SDRAM can be connected to up to 2 spaces The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits Burst read single write burst length 1 and burst read burst write burst length 1 are supported as the SDRAM operating mode Commands for SDRAM can ...

Page 245: ...WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL 64M synchronous DRAM 1M 16 bit 4 bank A13 A12 A11 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML A13 A12 A11 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML Note x is U or L Figure 7 14 Example of 64 MBit Synchronous DRAM Connection 32 Bit Data Bus ...

Page 246: ...ship between the settings of bits BSZ 1 0 AxROW 1 0 and AxCOL 1 0 and the bits output at the address pins Do not specify those bits in the manner other than this table otherwise the operation of this LSI is not guaranteed A25 to A18 are not multiplexed and the original values of address are always output at these pins When the data bus width is 16 bits BSZ 1 0 10 A0 of SDRAM specifies a word addre...

Page 247: ...A13 A21 2 A21 2 A11 BA0 Specifies bank A12 A20 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 A0 A8 A0 Unused Example of connected memory 64 Mbit product 512 kwords x 32 bits x 4 banks column 8 bits product 1 device 16 Mbit product 512 kwords x 16 bits x ...

Page 248: ...A12 BA0 Specifies bank A13 A21 A13 A11 Address A12 A20 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 A0 A8 A0 Unused Example of connected memory 128 Mbit product 1 Mword x 32 bits x 4 banks column 8 bits product 1 device 64 Mbit product 1 Mword x 16 bits...

Page 249: ...2 BA0 Specifies bank A13 A22 A13 A11 Address A12 A21 L H 1 A10 AP Specifies address precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 A0 A9 A0 Unused Example of connected memory 256 Mbit product 2 Mwords x 32 bits x 4 banks column 9 bits product 1 device 128 Mbit product 2 Mwords x 16 bi...

Page 250: ...22 L H 1 A10 AP Specifies address precharge A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 A11 A1 A0 A10 A0 Unused Example of connected memory 512 Mbit product 4 Mwords x 32 bits x 4 banks column 10 bits product 1 device 256 Mbit product 4 Mwords x 16 bits x 4 banks column 10 bits product 2 devices No...

Page 251: ...2 A21 L H 1 A10 AP Specifies address precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 A0 A9 A0 Unused Example of connected memory 512 Mbit product 4 Mwords x 32 bits x 4 banks column 9 bits product 1 device 256 Mbit product 4 Mwords x 16 bits x 4 banks column 9 bits product 2 devices No...

Page 252: ...A23 A15 A14 A22 A14 Unused A13 A21 2 A21 2 A12 BA1 A12 A20 2 A20 2 A11 BA0 Specifies bank A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 16 Mbit product 512 kwords x 16 bits x 2 banks column 8 bits product 1 device ...

Page 253: ...A15 Unused A14 A22 2 A22 2 A13 BA1 A13 A21 2 A21 2 A12 BA0 A12 A20 A12 A11 Specifies bank Address A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 64 Mbit product 1 Mword x 16 bits x 4 banks column 8 bits product 1 de...

Page 254: ...5 Unused A14 A23 2 A23 2 A13 BA1 A13 A22 2 A22 2 A12 BA0 Specifies bank A12 A21 A12 A11 Address A11 A20 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 128 Mbit product 2 Mwords x 16 bits x 4 banks column 9 bits product 1 d...

Page 255: ...5 Unused A14 A24 2 A24 2 A13 BA1 A13 A23 2 A23 2 A12 BA0 Specifies bank A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 256 Mbit product 4 Mwords x 16 bits x 4 banks column 10 bits product 1...

Page 256: ...24 2 A24 2 A14 BA1 A14 A23 2 A23 2 A13 BA0 Specifies bank A13 A22 A13 A12 A12 A21 A12 A11 Address A11 A20 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 Address A0 A9 A0 A0 Unused Example of connected memory 256 Mbit product 4 Mwords x 16 bits x 4 banks column 9 bits product 1...

Page 257: ...fies bank A13 A23 A13 A12 A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 512 Mbit product 8 Mwords x 16 bits x 4 banks column 10 bits product 1 device Notes 1 L H is a bit used in the comma...

Page 258: ...e SDRAM with burst length 1 For example read access of burst length 1 is performed consecutively 4 times to read 16 byte continuous data from the SDRAM that is connected to a 32 bit data bus Table 7 16 shows the relationship between the access size and the number of bursts Table 7 16 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 8 bits 1 16 bits 1 32 ...

Page 259: ... by the READ command in the SDRAM In the Tap cycle a new command will not be issued to the same bank However access to another CS space or another bank in the same SDRAM space is enabled The number of Tap cycles is specified by the TRP 1 0 bits of the CS3WCR register Tc4 CKIO A25 to A0 CSn RD WR RASU L DQMxx 2 D31 to D0 BS Tap DACKn 3 Tr Tc2 Tc3 Tc1 Td4 Tde Td2 Td3 Td1 A12 A11 1 CASU L Notes 1 Add...

Page 260: ...e required data is output Consequently no unnecessary bus cycles are generated even when a cache through area is accessed Figure 7 17 shows the basic timing chart for single read CKIO A25 to A0 CSn RD WR RASU L DQMxx 2 D31 to D0 BS Tap DACKn 3 Tr Tc1 Tde Td1 Tw A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when activ...

Page 261: ...cheable region Access size in writing is larger than data bus width This LSI always accesses SDRAM with burst length 1 For example write access of burst length 1 is performed continuously 4 times to write 16 byte continuous data to the SDRAM that is connected to a 32 bit data bus The relationship between the access size and the number of bursts is shown in table 7 16 ...

Page 262: ...for completion of the auto precharge induced by the WRITA command in the SDRAM In the Tap cycle a new command will not be issued to the same bank However access to another CS space or another bank in the same SDRAM space is enabled The number of Trw1 cycles is specified by the TRWL 1 0 bits of the CS3WCR register The number of Tap cycles is specified by the TRP 1 0 bits of the CS3WCR register Tc4 ...

Page 263: ...ss size This is called single write Figure 7 19 shows the basic timing chart for single write CKIO A25 to A0 CSn RD WR RASU L DQMxx 2 D31 to D0 BS Tap DACKn 3 Tr Tc1 Trwl A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 19 Basic Timing for Single Write Auto Precharge ...

Page 264: ...s after issuance of the WRITA command When bank active mode is used READ or WRIT commands can be issued successively if the row address is the same The number of cycles can thus be reduced by Trwl Tpc cycles for each write There is a limit on tRAS the time for placing each bank in the active state If there is no guarantee that there will not be a cache hit and another row address will be accessed ...

Page 265: ...QMxx 2 D31 to D0 BS DACKn 3 Tr Tc2 Tc3 Tc1 Td4 Td2 Td3 Td1 Tw Tde A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 20 Burst Read Timing No Auto Precharge ...

Page 266: ...IO A25 to A0 CSn RD WR RASU L DQMxx 2 D31 to D0 BS DACKn 3 A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 21 Burst Read Timing Bank Active Same Row Address ...

Page 267: ...KIO A25 to A0 CSn RD WR RASU L DQMxx 2 D31 to D0 BS DACKn 3 A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 22 Burst Read Timing Bank Active Different Row Addresses ...

Page 268: ... CSn RD WR RASU L DQMxx 2 D31 to D0 BS DACKn 3 A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 23 Single Write Timing No Auto Precharge ...

Page 269: ... RD WR RASU L DQMxx 2 D31 to D0 BS DACKn 3 A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 24 Single Write Timing Bank Active Same Row Address ...

Page 270: ...RD WR RASU L DQMxx 2 D31 to D0 BS DACKn 3 A12 A11 1 CASU L Notes 1 Address pin to be connected to the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 25 Single Write Timing Bank Active Different Row Addresses ...

Page 271: ... RRC 2 0 settings in RTCSR When the clock is selected by bits CKS 2 0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and auto refresh is performed for the number of times specified by bits RRC 2 0 At the same time RTCNT is cleared to zero and the count up is restarted...

Page 272: ...CSnWSR Synchronous DRAM cannot be accessed while in the self refresh state Self refresh mode is cleared by clearing the RMODE bit to 0 After self refresh mode has been cleared command issuance is disabled for the number of cycles specified by the TRC 1 0 bits in CSnWCR Self refresh timing is shown in figure 7 27 Settings must be made so that self refresh clearing and data retention are performed c...

Page 273: ...o the A10 pin of SDRAM 2 xx is UU UL LU or LL 3 The waveform for DACKn is when active low is specified Figure 7 27 Self Refresh Timing 3 Relationship between refresh requests and bus cycle If a refresh request is generated during a bus cycle refresh waits for the bus cycle to be completed If a refresh request is generated while the bus is released by the bus arbitration function refresh waits for ...

Page 274: ...hich is half a cycle faster than the normal timing This timing allows the hold time of commands addresses write data and read data to be extended If SDRAM is operated at a high frequency with the SLOW bit set to 1 the setup time of commands addresses write data and read data are not guaranteed Take the operating frequency and timing design into consideration when making the SLOW bit setting CKIO A...

Page 275: ...r area 3 synchronous DRAM In this operation the data is ignored but the mode write is performed as a word size access To set burst read single write CAS latency 2 to 3 wrap type sequential and burst length 1 supported by the LSI arbitrary data is written in a word size access to the addresses shown in table 7 17 In this time 0 is output at the external address pins of A12 or later Table 7 17 Acces...

Page 276: ...n issued 8 times An MRS command mode register write command is finally issued Idle cycles of which number is specified by the TRP 1 0 bits in CSnWCR are inserted between the PALL and the first REF Idle cycles of which number is specified by the TRC 1 0 bits in CSnWCR are inserted between REF and REF and between the 8th REF and MRS Idle cycles of which number is one or more are inserted between the...

Page 277: ...ion of the RD signal is not executed The accesses after the 2nd access are performed by exchanging only the address In the accesses after the 2nd access the address is changed at the falling edge of CKIO The number of wait cycles specified by the W 3 0 bits in CSnWCR are inserted for the first access cycle The number of wait cycles specified by the BW 1 0 bits in CSnWCR are inserted for the second...

Page 278: ...of Bursts 8 bits 8 bits 1 16 bits 2 32 bits 4 16 bytes 16 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 CKIO Address RD Data DACK WAIT CS T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 RD WR BS Figure 7 30 Burst ROM Access Bus Width 8 Bits Access Size 32 Bits Number of Burst 4 Access Wait for the 1st Time 2 Access Wait for 2nd Time and after 1 ...

Page 279: ...al space interface The read access timing differs from that for the normal space interface in the WEn timing and a byte selection signal is output from the WEn pin The basic access timing is shown in figure 7 31 Note that in a write cycle data is written in accordance with the byte selection pin WEn timing Check the data sheet of the memory to be used for the actual timing CKIO A25 to A0 CSn WEn R...

Page 280: ...E WE I O15 I O0 UB LB This LSI 64k 16 bit SRAM WE3 WE2 WE1 WE2 Figure 7 32 Example of Connection with 32 Bit Data Width Byte Selection SRAM This LSI A16 A1 CSn RD RD WR D15 D0 WE1 WE0 A15 A0 CS OE WE I O 15 I O 0 UB LB 64k 16 bit SRAM Figure 7 33 Example of Connection with 16 Bit Data Width Byte Selection SRAM ...

Page 281: ...d by any type of access DMAIWA 1 7 12 Bus Arbitration This LSI supports bus arbitration This LSI has bus mastership in the normal state and releases bus mastership after receiving a bus request from another device To prevent device malfunction while the bus mastership is transferred between master and slave the LSI negates all of the bus control signals before bus release When the bus mastership i...

Page 282: ...on of the bus cycle in progress when an external bus request BREQ is asserted low level and a bus acknowledge signal BACK is asserted low level Bus use is resumed when a negation high level of BREQ which shows that the slave has released the bus has been received SDRAM issues all bank pre charge commands PALLs when active banks exist and releases the bus after completion of a PALL command The bus ...

Page 283: ...mlines the system design 7 13 Others Reset The bus state controller BSC can be initialized completely only at power on reset At power on reset all signals are negated and output buffers are turned off regardless of the bus cycle state All control registers are initialized In standby sleep and manual reset control registers of the bus state controller are not initialized At manual reset the current...

Page 284: ...Rev 2 00 09 03 page 238 of 690 ...

Page 285: ...mode can be selected Transfer requests External request on chip peripheral module request or auto request can be selected The following modules can issue an on chip peripheral module request SCIF0 SCIF2 CMT USB and A D converter Bus modes Cycle steal mode normal mode and intermittent mode 16 64 or burst mode can be selected Selectable channel priority levels The channel priority levels are selecta...

Page 286: ...ler Request priority control Start up control Register control Transfer count control SAR_n DAR_n DMATCR_n CHCR_n DMAOR DMARS0 1 Legend DMAOR DMA operation register SARn DMA source address register DARn DMA destination address register DMATCRn DMA transfer count register CHCRn DMA channel control register DMARS0 1 DMA extension resource selector DEIn DMA transfer end interrupt request to the CPU n...

Page 287: ...fer end output in channel 0 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device 8 3 Register Descriptions The DMAC has the following registers See section 24 List of Registers for the addresses of these registers and the states of them in each p...

Page 288: ...ress mode SAR is ignored To transfer data in 16 bits or in 32 bits specify the address with 16 bit or 32 bit address boundary When transferring data in 16 byte units a 16 byte boundary must be set for the source address value The initial value is undefined The SAR retains the current value in software standby or module standby mode 8 3 2 DMA Destination Address Registers DAR DAR are 32 bit readabl...

Page 289: ...2 bit readable writable registers that control the DMA transfer mode Bit Bit Name Initial Value R W Descriptions 31 to 24 0 R Reserved These bits are always read as 0 The write value should always be 0 23 DO 0 R W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1 This bit is valid only in CHCR_0 and CHCR_1 This bit is always read as 0 in CHCR_2 and CHCR_3 The write value sh...

Page 290: ...it is valid only in CHCR_0 and CHCR_1 This bit is always read as 0 in CHCR_2 and CHCR_3 The write value should always be 0 0 Low active output of DACK 1 High active output of DACK 15 14 DM1 DM0 0 0 R W R W Destination Address Mode Specify whether the DMA destination address is incremented decremented or left fixed In single address mode the DM1 and DM0 bits are ignored when data is transferred to ...

Page 291: ...W R W Resource Select Specifies which transfer requests will be sent to the DMAC The changing of transfer request source should be done in the state that the DMA enable bit DE is set to 0 0000 External request dual address mode 0001 Setting prohibited 0010 External request single address mode External address space external device with DACK 0011 External request single address mode External device...

Page 292: ...ted in high level 11 DREQ detected at rising edge 5 TB 0 R W Transfer Bus Mode Specifies the bus mode when DMA transfers data 0 Cycle steal mode 1 Burst mode 4 3 TS1 TS0 0 0 R W R W Transfer Size Specify the size of data to be transferred Select the size of data to be transferred when the source or destination is an on chip peripheral module register of which transfer size is specified 00 Byte siz...

Page 293: ...fer or DMA transfer has been aborted Clearing conditions Writing 0 after reading TE 1 Power on reset Manual reset 1 Data transfer ends by the specified count DMATCR 0 0 DE 0 R W DMA Enable Enables or disables the DMA transfer In auto request mode DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1 In this time all of the bits TE NMIF in DMAOR and AE must be 0 In an external request...

Page 294: ... bus modes are set to cycle steal mode to make valid intermittent mode 00 Normal mode 01 Setting prohibited 10 Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock 11 Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock 11 10 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PR1 PR0 0 ...

Page 295: ... DMAOR are set to 1 This bit can only be cleared by writing 0 after reading 1 When the NMI is input the DMA transfer in progress can be done in one transfer unit When the DMAC is not in operation the NMIF bit is set to 1 even if the NMI interrupt was input 0 No NMI interrupt Clearing conditions Writing 0 after reading NMIF 1 Power on reset Manual reset 1 NMI input DMA transfer disabled Setting con...

Page 296: ... RS0 has been set to B 1000 for CHCR_0 to CHCR_3 Otherwise even if DMARS has been set transfer request source is not accepted DMARS0 Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 1 MID See table 8 2 9 8 C1RID1 C1RID0 0 0 R W R W Transfer request res...

Page 297: ...e table 8 2 7 to 2 C2MID5 to C2MID0 0 R W Transfer request resource module ID5 to ID0 for DMA channel 2 MID See table 8 2 1 0 C2RID1 C2RID0 0 0 R W R W Transfer request resource register ID1 and ID0 for DMA channel 2 RID See table 8 2 Table 8 2 Transfer Request Sources Peripheral Module Setting Value for One Channel MID RID MID RID Function H 21 B 01 Transmit SCIF0 H 22 B 001000 B 10 Receive H 29 ...

Page 298: ...set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 2 When a transfer request is generated and transfer is enabled the DMAC transfers 1 transfer unit of data depending on the TS0 and TS1 settings For an auto request the transfer begins automatically when the DE bit and DME bit are set to 1 The DMATCR value will be decr...

Page 299: ...quest when IE 1 TE 1 No Yes No Yes No Yes Yes No Yes No 3 2 Start Transfer aborted DMATCR 0 Transfer request occurs 1 DE DME 1 and NMIF AE TE 0 NMIF 1 or AE 1 or DE 0 or DME 0 Transfer end Notes 1 In auto request mode transfer begins when NMIF AE and TE bits are 0 and the DE and DME bits are set to 1 2 DREQ level detection in burst mode external request or cycle steal mode 3 DREQ edge detection in...

Page 300: ...HCR and the DME bit in DMAOR are set to 1 the transfer begins so long as the AE and NMIF bits in DMAOR are 0 External Request Mode In this mode a transfer is performed at the request signals DREQ0 and DREQ1 of an external device This mode is valid only in channels 0 and 1 Choose one of the modes shown in table 8 3 according to the application system When this mode is selected if the DMA transfer i...

Page 301: ... again becomes request accept enabled state When DREQ is used for level detection there are the following two cases depending on the timing to detect the next DREQ after outputting DACK A case wherein transfer is aborted after the same number of transfers has been performed as requests overrun 0 and wherein another transfer is aborted after transfers have been performed for the number of requests ...

Page 302: ...s also apply to the USB Any address can be specified for data source and destination when transfer request is generated by the CMT Table 8 6 Selecting On Chip Peripheral Module Request Modes with RS3 to RS0 Bits RS3 RS2 RS1 RS0 DMA Transfer Request Source DMA Transfer Request Signal Source Destination Bus Mode 1 1 1 0 ADC AD conversion end request ADDR Any Cycle steal 1 1 1 1 CMT Compare match tra...

Page 303: ...etermined priority order Two modes fixed mode and round robin mode are selected by bits PR1 and PR0 in the DMA operation register DMAOR Fixed Mode In these modes the priority levels among the channels remain fixed There are two kinds of fixed modes as follows CH0 CH1 CH2 CH3 CH0 CH2 CH3 CH1 These are selected by the PR1 and the PR0 bits in the DMA operation register DMAOR ...

Page 304: ...nitial priority order Initial priority order Initial priority order Initial priority order Priority order after transfer Priority order does not change Channel 2 becomes bottom priority The priority of channels 0 and 1 which were higher than channel 2 are also shifted If immediately after there is a request to transfer channel 1 only channel 1 becomes bottom priority and the priority of channels 3...

Page 305: ...riority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 becomes lowest priority 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority Transfer request Waiting channel s DMAC o...

Page 306: ... 8 Supported DMA Transfers Destination Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Dual single Dual single Not available External memory Dual single Dual Dual Dual Memory mapped external device Dual single Dual Dual Dual On chip peripheral module Not available Dual Dual Dual Notes 1 Dual Dual addre...

Page 307: ...ffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR The SAR value is an address data is read from the transfer source module and the data is temporarily stored in the DMAC The DAR value is an address and the value stored in the data buffer in the DMAC is writte...

Page 308: ...s mode either the transfer source or transfer destination peripheral device is accessed selected by means of the DACK signal and the other device is accessed by address In this mode the DMAC performs one DMA transfer in one bus cycle accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it and at the same time outputting an address to the other device ...

Page 309: ...ing in single address mode Address output to external memory space Select signal to external memory space Select signal to external memory space Data output from external device with DACK DACK signal active low to external device with DACK Write strobe signal to external memory space Address output to external memory space Data output from external memory space DACK signal active low to external d...

Page 310: ...level detection CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU DREQ Bus cycle Bus right returned to CPU once Read Write Read Write Figure 8 9 DMA Transfer Example in Cycle Steal Normal Mode Dual Address DREQ Low Level Detection Intermittent Mode 16 and Intermittent Mode 64 In intermittent mode of cycle steal DMAC returns the bus right to other bus master whenever a unit of transfer byte word longword or ...

Page 311: ...he transfer is performed continuously until the transfer end condition is satisfied In external request mode with low level detection of the DREQ pin however when the DREQ pin is driven high the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends even if the transfer end conditions have not been satisfied Burst mode cannot be used for other than t...

Page 312: ...5 Single External device with DACK and external memory External B C 8 16 32 0 1 External device with DACK and memory mapped external device External B C 8 16 32 0 1 B Burst C Cycle steal Notes 1 External requests auto requests and on chip peripheral module requests are all available In the case of on chip peripheral module requests however the CMT is only available 2 External requests auto request...

Page 313: ... CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 CPU CH0 CH1 CH0 Cycle steal mode between DMAC CH0 and CH1 DMAC CH1 burst mode CPU CPU Priority CH0 CH1 CH0 Cycle steal mode CH1 Burst mode DMAC CH1 burst mode Figure 8 12 Bus State when Multiple Channels are Operating Cycle steal mode channels and burst mode channels should not be mixed in round robin mode Doing so runs the risk that priority changes may not be...

Page 314: ...Non sensitive period 1st acceptance 2nd acceptance Acceptance start Acceptance start 1st acceptance 2nd acceptance Non sensitive period Figure 8 14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection CKIO Bus cycle DREQ Rising DACK Active high CPU CPU DMAC DMAC Non sensitive period Busrst acceptance Figure 8 15 Example of DREQ Input Detection in Burst Mode Edge Detection ...

Page 315: ...h CPU CPU DMAC DMAC 2nd acceptance Acceptance start Acceptance start Acceptance start Non sensitive Non sensitive 1st acceptance 2nd acceptance 3rd acceptance Figure 8 16 Example of DREQ Input Detection in Burst Mode Level Detection CKIO Bus cycle DACK DREQ TEND CPU CPU CPU DMAC Last DMA transfer DMAC Figure 8 17 Example of DMA Transfer End Signal in Cycle Steal Level Detection ...

Page 316: ...SC Ordinary Memory Access No Wait Idle Cycle 1 Longword Access to 16 Bit Device 8 5 Precautions 8 5 1 Precautions when Mixing Cycle Steal Mode Channels and Burst Mode Channels Transfer mode settings should not fulfill conditions 1 and 2 below at the same time 1 DMA transfer takes place using multiple channels some of which operate in the burst mode and some in the cycle steal mode 2 A channel that...

Page 317: ...nerated independently An internal clock for the CPU and cache Iφ a peripheral clock Pφ for the peripheral modules a bus clock Bφ CKIO for the external bus interface Frequency change function Internal and peripheral clock frequencies can be changed independently using the phase locked loop PLL circuit and divider circuit within the CPG Frequencies are changed by software using the frequency control...

Page 318: ...TBCR STBCR2 STBCR3 UCLKCR Frequency control register Standby control register Standby control register 2 Standby control register 3 USB clock control register Peripheral clock Pφ Bus clock Bφ CKIO XTAL EXTAL MD2 MD1 MD0 FRQCR UCLKCR STBCR STBCR2 STBCR3 CPG control unit USB clock Clock frequency control circuit Standby control circuit Divider 1 Crystal Oscillator Figure 9 1 Block Diagram of Clock P...

Page 319: ...enerates a clock at the operating frequency used by the internal or peripheral clock The operating frequency can be 1 1 2 1 3 or 1 4 times the output frequency of PLL circuit 1 as long as it stays at or above the clock frequency of the CKIO pin The division ratio is set in the frequency control register 5 Clock Frequency Control Circuit The clock frequency control circuit controls the clock freque...

Page 320: ...rystal resonator Crystal oscillator pins for system clock clock input pins EXTAL I Connects a crystal resonator Also used to input an external clock Clock I O pin CKIO I O Inputs or outputs an external clock XTAL_USB O Connects a crystal resonator for the USB Crystal oscillator pins for USB clock input pins EXTAL_USB I Connects a crystal resonator for the USB Also used to input an external clock N...

Page 321: ...utes waveform shaping by PLL circuit 2 before being supplied inside this LSI Mode 1 An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside this LSI allowing a low frequency external clock to be used Mode 2 The on chip crystal oscillator operates with the oscillation frequency being multiplied by 4 by PLL circuit 2 before bei...

Page 322: ... 34 MHz 26 70 MHz to 33 34 MHz H 1303 ON 4 ON 1 4 1 1 20 00 MHz to 33 34 MHz 20 00 MHz to 33 34 MHz H 1313 ON 4 ON 1 2 1 1 20 00 MHz to 33 34 MHz 20 00 MHz to 33 34 MHz 0 H 1333 ON 4 ON 1 1 1 1 20 00 MHz to 33 34 MHz 20 00 MHz to 33 34 MHz H 1001 ON 1 ON 4 4 4 2 10 00 MHz to 16 67 MHz 40 00 MHz to 66 67 MHz H 1003 ON 1 ON 4 4 4 1 10 00 MHz to 16 67 MHz 40 00 MHz to 66 67 MHz H 1103 ON 2 ON 4 8 4 2...

Page 323: ... 16 67 MHz 20 00 MHz to 33 33 MHz H 1313 ON 4 ON 2 4 2 2 10 00 MHz to 16 67 MHz 20 00 MHz to 33 33 MHz 5 H 1333 ON 4 ON 2 2 2 2 10 00 MHz to 16 67 MHz 20 00 MHz to 33 34 MHz H 1000 ON 1 ON 2 2 2 2 10 00 MHz to 16 67 MHz 20 00 MHz to 33 34 MHz H 1001 ON 1 ON 2 2 2 1 10 00 MHz to 33 34 MHz 20 00 MHz to 66 67 MHz H 1003 ON 1 ON 2 2 2 1 2 10 00 MHz to 33 34 MHz 20 00 MHz to 66 67 MHz H 1101 ON 2 ON 2 ...

Page 324: ... 00 MHz to 33 34 MHz Notes 1 This LSI cannot operate in an FRQCR value other than that listed in table 9 3 2 Taking input clock frequency ratio as 1 Cautions 1 The input to divider 1 is the output of the PLL circuit 1 2 The frequency of the internal clock Iφ is The product of the frequency of the CKIO pin the frequency multiplication ratio of PLL circuit 1 and the division ratio of divider 1 Do no...

Page 325: ...te refer to table 9 3 The combinations listed in table 9 3 should only be set on FRQCR Bit Bit Name Initial Value R W Description 15 to 13 0 R Reserved These bits are always read as 0 The write value should always be 0 12 CKOEN 1 R W Clock Output Enable Specifies to output a clock from the CKIO pin or to fix the CKIO pin low when software standby is canceled after an interrupt before STATUS1 becom...

Page 326: ...k Frequency Division Ratio Specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1 00 1 time 01 1 2 time 10 1 3 time 11 1 4 time 3 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PFC1 PFC0 1 1 R W R W Peripheral Clock Frequency Division Ratio Specify the frequency division ratio of the peripheral clock w...

Page 327: ...lator 0 USB on chip oscillator stopped 1 USB on chip oscillator operates 4 to 0 0 R Reserved These bits are always read as 0 The write value should always be 0 9 4 3 Usage Notes Note the following when using the USB If these are used incorrectly the correct clocks may not be generated causing faulty operation of the USB 1 UCLKCR is used only for generation of the USB clocks When the USB is not use...

Page 328: ...STC 1 0 bits The division ratio can also be set in the IFC 1 0 bits and PFC 1 0 bits 4 The processor pauses internally and the WDT starts incrementing The internal and peripheral clocks both stop and the WDT is supplied with the clock The clock will continue to be output at the CKIO pin 5 Supply of the clock that has been set begins at WDT count overflow and the processor begins operating again Th...

Page 329: ...s As far as possible insert a laminated ceramic capacitor of 0 1 to 1 µF as a passive capacitor for each VSS VSSQ and VCC VCCQ pair Mount the passive capacitors as close as possible to the chip s power supply pins and use components with a frequency characteristic suitable for the chip s operating frequency as well as a suitable capacitance value Digital system VSS VSSQ and VCC VCCQ pairs 2 5 17 1...

Page 330: ...s Power supply Figure 9 3 Points for Attention when Using PLL Oscillator Circuit Notes on Wiring Power Supply Pins To avoid crossing signal lines wire VCC PLL1 VCC PLL2 VSS PLL1 and VSS PLL2 as three patterns from the power supply source on the board so that they are independent of digital VCC and VSS ...

Page 331: ...ed as a conventional watchdog timer or an interval timer 10 1 Features Can be used to ensure the clock settling time Use the WDT to clear software standby mode and the temporary standbys which occur when the clock frequency is changed Can switch between watchdog timer mode and interval timer mode Generates internal resets in watchdog timer mode Internal resets occur after counter overflow Power on...

Page 332: ...gisters for the details of the addresses of these registers and the state of registers in each operating mode Watchdog timer counter WTCNT Watchdog timer control status register WTCSR 10 2 1 Watchdog Timer Counter WTCNT The watchdog timer counter WTCNT is an 8 bit readable writable register that increments on the selected clock When an overflow occurs it generates a reset in watchdog timer mode an...

Page 333: ...for the count overflow flags and enable bits WTCSR holds its value in an internal reset due to the WDT overflow WTCSR is initialized to H 00 only by a power on reset using the RESETP pin When used to count the clock settling time for canceling a software standby it retains its value after counter overflow Use a word access to write to the WTCSR counter with H A5 in the upper byte Use a byte access...

Page 334: ...te If WT IT is modified when the WDT is running the up count may not be performed correctly 5 RSTS 0 R W Reset Select Selects the type of reset when WTCNT overflows in watchdog timer mode In interval timer mode this setting is ignored 0 Power on reset 1 Manual reset 4 WOVF 0 R W Watchdog Timer Overflow Indicates that WTCNT has overflowed in watchdog timer mode This bit is not set in interval timer...

Page 335: ...equency division ratio of 1 16 1 32 1 64 1 256 1 1 024 or 1 4 096 is selected using bits CKS2 to CKS0 and a watchdog timer counter overflow occurs resulting in a manual reset the LSI will generate two manual resets in succession This will not affect its operation but will cause change in the state of the STATUS pin 10 2 3 Notes on Register Access The watchdog timer counter WTCNT and watchdog timer...

Page 336: ...t the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter These values should ensure that the time till count overflow is longer than the clock oscillation settling time 3 Move to software standby mode by executing a SLEEP instruction after that clock stops 4 The WDT starts counting by detecting the edge change of the NMI signal 5 ...

Page 337: ... of the frequency change instruction always confirm that the value of WTCNT is H 00 by reading WTCNT 10 3 3 Using Watchdog Timer Mode 1 Set the WT IT bit in WTCSR to 1 set the reset type in the RSTS bit set the type of count clock in the CKS2 to CKS0 bits and set the initial value of the counter in the WTCNT counter 2 Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode 3 While ...

Page 338: ...Rev 2 00 09 03 page 292 of 690 ...

Page 339: ...11 1 Features This LSI has the following power down modes and function 1 Sleep mode 2 Software standby mode 3 Module standby function Cache TLB UBC DMAC UDI and on chip peripheral module 4 Hardware standby mode Table 11 1 shows the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral module states in each mode and the procedures for cancel...

Page 340: ...STBY bit set to 1 in STBCR Halt Halt Held Halt 1 3 Self refresh 1 Interrupt 2 Reset Module standby function Set MSTP bit of STBCR STBCR2 and STBCR3 to 1 Run Run Held Specified module halts 2 Refresh 1 Clear MSTP bit to 0 2 Power on reset Hardware standby mode Drive CA pin low Halt Halt Held Halt 1 4 Power on reset Notes 1 The RTC still runs if the START bit in RCR2 is set to 1 see section 15 Realt...

Page 341: ...P I Reset input signal Power on reset occurs at low level Manual reset RESETM I Reset input signal Manual reset occurs at low level Hardware standby CA I Normal operation at high level and hardware standby mode is entered at low level 11 3 Register Descriptions There are following five registers used for the power down modes Refer to section 24 List of Registers for the details of the addresses of...

Page 342: ...d always be 0 4 STBXTL 0 R W Standby Crystal Specifies stop start of the crystal oscillator in standby mode 0 Crystal oscillator stops in standby mode 1 Crystal oscillator continues operation in standby mode 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 MSTP2 0 R W Module Stop 2 Specifies halting the clock supply to the TMU when the MSTP2 bit has been set to 1 0 ...

Page 343: ...set to 1 the clock supply to the UBC is halted 0 UBC runs 1 Clock supply to UBC is halted 5 MSTP8 0 R W Module Stop Bit 8 When the MSTP8 bit is set to 1 the clock supply to the DMAC is halted 0 DMAC runs 1 Clock supply to DMAC is halted 4 0 R Reserved This bit is always read as 0 The write value should always be 0 3 MSTP6 0 R W Module Stop Bit 6 When the MSTP6 bit is set to 1 the clock supply to t...

Page 344: ...set to 1 the clock supply to the USB is halted 0 USB runs 1 Clock supply to USB is halted 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 MSTP35 0 R W Module Stop Bit 35 When the MSTP35 bit is set to 1 the clock supply to the CMT is halted 0 CMT runs 1 Clock supply to CMT is halted 4 MSTP34 0 R W Module Stop Bit 34 When the MSTP34 bit is set to 1 the clock supply t...

Page 345: ...de Although the CPU halts immediately after executing the SLEEP instruction the contents of its internal registers remain unchanged The on chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO pin In sleep mode the STATUS1 pin is set high and the STATUS0 pin low 11 4 2 Canceling Sleep Mode Sleep mode is canceled by an interrupt NMI IRQ IRL PINT and ...

Page 346: ...put goes low and the STATUS0 pin output goes high 11 5 2 Canceling Software Standby Mode Software standby mode is canceled by an interrupt NMI IRQ IRL PINT or RTC or a reset Canceling with an Interrupt The on chip WDT can be used for hot starts When the chip detects an NMI IRQ 1 IRL 1 PINT 1 or RTC 1 interrupt the clock will be supplied to the entire chip and software standby mode canceled after t...

Page 347: ... by a reset power on or manual Keep the RESETP or RESETM pins low until the clock oscillation settles The internal clock will continue to be output to the CKIO pin 11 6 Module Standby Function 11 6 1 Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on chip peripheral modules This function can be used to reduce...

Page 348: ...When the CA pin is driven low the LSI enters hardware standby mode in the following procedure depending on the state of CPG During Software Standby Mode The LSI enters the hardware standby state with the clock halted An interrupt or manual reset cannot be accepted During WDT Operation for Canceling Software Standby Mode by an Interrupt The CPU restarts the operation after software standby mode is ...

Page 349: ...t HH STATUS1 high STATUS0 high 2 Normal LL STATUS1 low STATUS0 low 3 Bcyc Bus clock cycle Figure 11 2 Power On Reset STATUS Output b Manual reset CKIO RESETM STATUS Normal 3 Normal 3 Reset 2 0 Bcyc or more 1 4 0 to 30 Bcyc 4 During manual reset STATUS becomes HH reset and the internal reset begins after waiting for the executing bus cycle to end Reset HH STATUS1 high STATUS0 high Normal LL STATUS1...

Page 350: ...t STATUS Output b Canceling software standby by power on reset CKIO STATUS Normal 5 Normal 5 Oscillation stops Standby 4 2 0 to 10 Bcyc 6 0 to 30 Bcyc 6 Reset Reset 3 RESETP 1 1 When software standby mode is cleared with a power on reset the WDT does not count Keep RESETP low during the PLL s oscillation settling time 2 Undefined 3 Reset HH STATUS1 high STATUS0 high 4 Standby LH STATUS1 low STATUS...

Page 351: ...the PLL s oscillation settling time 2 Reset HH STATUS1 high STATUS0 high 3 Standby LH STATUS1 low STATUS0 high 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle Figure 11 6 Canceling Software Standby by Manual Reset STATUS Output In Case of Canceling Sleep a Canceling sleep to interrupt CKIO STATUS Normal 2 Normal 2 Sleep 1 Interrupt request Notes 1 Sleep HL STATUS1 high STATUS0 low 2 Nor...

Page 352: ...0 to 80 Bcyc 5 0 to 30 Bcyc 5 Reset STATUS Normal 4 Normal 4 Sleep 3 Reset 2 RESETM 1 Notes 1 Keep RESETM low until STATUS becomes reset 2 Reset HH STATUS1 high STATUS0 high 3 Sleep HL STATUS1 high STATUS0 low 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle Figure 11 9 Canceling Sleep by Manual Reset STATUS Output In Case of Hardware Standby Figures 11 10 and 11 11 show examples of pin ...

Page 353: ... cycle Figure 11 10 Hardware Standby Mode When CA Goes Low in Normal Operation b Canceling software standby during WDT operation to hardware standby Normal 3 STATUS CA CKIO Standby 2 Reset 1 RESETP Undefined 2 Rcyc or more 5 0 10 Bcyc 4 Standby WDT operation Notes 1 Reset HH STATUS1 high STATUS0 high 2 Standby LH STATUS1 low STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus clock cycle 5...

Page 354: ...Rev 2 00 09 03 page 308 of 690 ...

Page 355: ...er All channels are provided with 32 bit constant registers and 32 bit down counters for an auto reload function that can be read or written to at any time All channels generate interrupt requests when the 32 bit down counter underflows H 00000000 H FFFFFFFF Only channel 2 is provided with an input capture function Allows selection among five counter input clocks External clock TCLK Pφ 4 Pφ 16 Pφ ...

Page 356: ...nterface Ch 0 Interrupt controller Interrupt controller Interrupt controller Counter controller Counter controller TUNI1 TUNI2 TICPI2 TCR_2 TCPR_2 TCNT_2 TCOR_2 TMU Ch 1 Ch 2 Clock controller TSTR TCR_n Timer start register TCNT_n TCOR_n TCPR_2 32 bit timer counter 32 bit timer constant register 32 bit input capture register Timer control register n 0 1 2 Legend Figure 12 1 TMU Block Diagram ...

Page 357: ...or more details of the addresses of these registers and state of these registers in each processing state For the register name for each channel TCOR for channel 0 is noted as TCOR_0 1 Common Timer start register TSTR 2 Channel 0 Timer constant register_0 TCOR_0 Timer counter_0 TCNT_0 Timer control register_0 TCR_0 3 Channel 1 Timer constant register_1 TCOR_1 Timer counter_1 TCNT_1 Timer control r...

Page 358: ...g the MSTP2 bit in STBCR to 1 Bit Bit Name Initial Value R W Description 7 to 3 0 R Reserved These bits are always read as 0 The write value should always be 0 2 STR2 0 R W Counter Start 2 Selects whether to run or halt timer counter 2 TCNT_2 0 TCNT_2 count halted 1 TCNT_2 counts 1 STR1 0 R W Counter Start 1 Selects whether to run or halt timer counter 1 TCNT_1 0 TCNT_1 count halted 1 TCNT_1 count...

Page 359: ...apture TCR_0 and TCR_1 Bit Bit Name Initial Value R W Description 15 to 9 0 R Reserved These bits are always read as 0 The write value should always be 0 8 UNF 0 R W Underflow Flag Status flag that indicates occurrence of a TCNT underflow 0 TCNT has not underflowed Clearing condition 0 is written to UNF 1 TCNT has underflowed Setting condition TCNT underflows 7 6 0 R Reserved These bits are always...

Page 360: ...ing edge 1X Count on both rising and falling edges Note X Don t care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R W R W R W Timer Prescaler Select the TCNT count clock 000 Count on Pφ 4 001 Count on Pφ 16 010 Count on Pφ 64 011 Count on Pφ 256 100 Setting prohibited 101 Count on TCLK pin input 110 Setting prohibited 111 Setting prohibited Note Only 0 can be written for clearing the flags If 1 is written to thi...

Page 361: ...nput capture is requested via the TCLK pin 0 No input capture request has been issued Clearing condition 0 is written to ICPF 1 Input capture has been requested via the TCLK pin Setting condition When an input capture is requested via the TCLK pin 8 UNF 0 R W Underflow Flag Status flag that indicates occurrence of a TCNT_2 underflow 0 TCNT_2 has not underflowed Clearing condition 0 is written to U...

Page 362: ...d Interrupt due to ICPF TICPI2 are not enabled 11 Input capture function is used Interrupt due to ICPF TICPI2 are enabled 5 UNIE 0 R W Underflow Interrupt Control Controls enabling of interrupt generation when the status flag UNF indicating TCNT_2 underflow has been set to 1 0 Interrupt due to UNF TUNI2 is not enabled 1 Interrupt due to UNF TUNI2 is enabled 4 3 CKEG1 CKEG0 0 0 R W R W Clock Edge S...

Page 363: ... TCNT TCNT counts down upon input of a clock The clock input is selected using the TPSC2 to TPSC0 bits in the timer control register TCR When a TCNT countdown results in an underflow H 00000000 H FFFFFFFF the underflow flag UNF in the timer control register TCR of the relevant channel is set The TCOR value is simultaneously set in TCNT itself and the countdown continues from that value Initial val...

Page 364: ...derflow interrupt generation Set timer constant register Initialize timer counter Start counting 1 2 4 5 6 Set input capture interrupt generation When using input capture function 3 Note When an interrupt has been generated clear the flag in the interrupt handler that caused it If interrupts are enabled without clearing the flag another interrupt will be generated Select the counter clock with the...

Page 365: ...Figure 12 3 Auto Reload Count Operation TCNT Count Timing 1 Internal Clock Operation Set the TPSC2 to TPSC0 bits in TCR to select whether one of the four internal clocks created by dividing the peripheral module clock is used Pφ 4 Pφ 16 Pφ 64 Pφ 256 Figure 12 4 shows the timing Pφ Internal clock Timer counter input clock TCNT N 1 N N 1 Figure 12 4 Count Timing when Internal Clock Is Operating ...

Page 366: ...ating Both Edges Detected 12 4 2 Input Capture Function Channel 2 has an input capture function When using the input capture function set the timer operation clock to internal clock with the TPSC2 to TPSC0 bits in TCR_2 Also specifies use of the input capture function and whether to generate interrupts on using it with the ICPE1 to ICPE0 bits in TCR_2 and specifies the use of either the rising or ...

Page 367: ...t Timing The UNF bit is set to 1 when the TCNT underflows Figure 12 7 shows the timing Pφ TCNT Underflow signal UNF TUNI TCOR value H 00000000 Figure 12 7 UNF Set Timing 12 5 2 Status Flag Clear Timing The status flag can be cleared by writing 0 from the CPU Figure 12 8 shows the timing Pφ Peripheral address bus UNF ICPF TCR address T1 T2 TCR write cycle T3 Figure 12 8 Status Flag Clear Timing ...

Page 368: ... 12 2 lists TMU interrupt sources Table 12 2 TMU Interrupt Sources Channel Interrupt Source Description Priority 0 TUNI0 Underflow interrupt 0 High 1 TUNI1 Underflow interrupt 1 TUNI2 Underflow interrupt 2 2 TICPI2 Input capture interrupt 2 Low 12 6 Usage Notes 12 6 1 Writing to Registers Synchronization processing is not performed for timer counting during register writes When writing to register...

Page 369: ...ected Generates a DMA transfer request when compare match occurs The CPU interrupt is not supported When the CMT is not used the operation can be halted by stopping the clock supply to the CMT so that the power consumption can be reduced Internal bus Bus interface Control circuit Clock selection CMSTR CMCSR CMCOR Comparator CMCNT Module bus CMT Pφ 4 Pφ 8 Pφ 16 Pφ 64 CMSTR CMCSR CMCOR CMCNT Compare...

Page 370: ...R Compare match counter CMCNT Compare match constant register CMCOR 13 2 1 Compare Match Timer Start Register CMSTR CMSTR is a 16 bit register that selects whether to operate or halt the counter CMCNT Bit Bit Name Initial Value R W Description 15 to 1 0 R Reserved These bits are always read as 0 The write value should always be 0 0 STR 0 R W Count Start Selects whether to operate or halt the compa...

Page 371: ...hed Clearing condition Write 0 to CMF after reading CMF 1 1 CMCNT and CMCOR values have matched 6 5 0 R Reserved These bits are always read as 0 The write value should always be 0 4 CMR 0 R W Compare Match Request 0 Disables a DMA transfer request 1 Enables a DMA transfer request 3 2 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Sel...

Page 372: ...Constant Register CMCOR CMCOR is a 16 bit register that sets the compare match period with CMCNT The initial value of CMCOR is H FFFF 13 3 Operation 13 3 1 Period Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1 CMCNT begins incrementing with the selected clock When the CMCNT value matches that of CMCOR CMCNT is cleared to...

Page 373: ...re Match Flag Set Timing The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and CMCNT match The compare match signal is generated upon the final state of the match timing at which the CMCNT matching count value is updated to H 0000 Consequently after CMCOR and CMCNT match a compare match signal will not be generated until a CMCNT clock is input Figure 13 4 shows the ...

Page 374: ...Rev 2 00 09 03 page 328 of 690 ...

Page 375: ...ring registers TGRC and TGRD can also be used as buffer registers Selection of four counter input clocks for channels 0 to 3 The following operations can be set for each channel Waveform output at compare match Selection of 0 1 or toggle output Counter clear operation Counter clearing possible by compare match PWM mode Any PWM output duty cycle can be set Maximum of 4 phase PWM output possible Buf...

Page 376: ...TGR2A TGR2B TGR3A TGR3B General registers buffer registers TGR0C TGR0D TGR1C TGR1D TGR2C TGR2D TGR3C TGR3D Output pins TO0 TO1 TO2 TO3 Counter clear function TGR compare match TGR compare match TGR compare match TGR compare match 0 output 1 output Compare match output Toggle output PWM mode Buffer operation Interrupt sources 5 sources Compare match Overflow 5 sources Compare match Overflow 5 sourc...

Page 377: ...ut control Channel 0 Channel 2 Channel 1 Same as channel 0 Channel 3 Same as channel 2 clear TGRA Pφ TO0 TO2 TO1 TO3 Pφ 1 Pφ 4 Pφ 16 Pφ 64 TGRB TGRC TGRD Selector Clock selection Edge selection Comparator Buffer Counter up Output control clear TGRA TGRB TGRC TGRD Selector Figure 14 1 Block Diagram of TPU ...

Page 378: ... to section 24 List of Registers for more details of the addresses of these registers and state of these registers in each processing state For the register name for each channel TCR for channel 0 is noted as TCR_0 1 Channel 0 Timer control register_0 TCR_0 Timer mode register_0 TMDR_0 Timer I O control register_0 TIOR_0 Timer interrupt enable register_0 TIER_0 Timer status register_0 TSR_0 Timer ...

Page 379: ...us register 2 TSR_2 Timer counter_2 TCNT_2 Timer general register A_2 TGRA_2 Timer general register B_2 TGRB_2 Timer general register C_2 TGRC_2 Timer general register D_2 TGRD_2 4 Channel 3 Timer control register_3 TCR_3 Timer mode register_3 TMDR_3 Timer I O control register_3 TIOR_3 Timer interrupt enable register_3 TIER_3 Timer status register_3 TSR_3 Timer counter_3 TCNT_3 Timer general regis...

Page 380: ...RC compare match 110 TCNT cleared by TGRD compare match 111 Setting prohibited 4 3 CKEG1 CKEG0 0 0 R W R W Clock Edge Select the input clock edge When the internal clock is counted using both edges the input clock period is halved e g Pφ 4 both edges Pφ 2 rising edge 00 Count at rising edge 01 Count at falling edge 1X Count at both edges Legend X Don t care Note Internal clock edge selection is va...

Page 381: ...tion 0 0 0 0 Internal clock counts on Pφ 1 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts on Pφ 64 1 X X Setting prohibited Note X Don t care Table 14 4 TPSC2 to TPSC0 2 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock counts on Pφ 1 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts o...

Page 382: ... Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts on Pφ 64 1 X X Setting prohibited Note X Don t care Table 14 4 TPSC2 to TPSC0 4 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock counts on Pφ 1 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts on Pφ 64 1 X X Setting prohibited Note X Don t care ...

Page 383: ... compare match of each register 1 TGRA and TGRB are rewritten in counter clearing 5 BFB 0 R W Buffer Operation B Specifies whether TGRB is to operate in the normal way or TGRB and TGRD are to be used together for buffer operation 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation 4 BFA 0 R W Buffer Operation A Specifies whether TGRA is to operate in the normal way or TGRA ...

Page 384: ...A1 IOA0 0 0 0 R W R W R W I O Control Bits IOA2 to IOA0 specify the functions of TGRA and the TO pin For details refer to table 14 5 Table 14 5 IOA2 to IOA0 Bit 2 Bit 1 Bit 0 Channel IOA2 IOA1 IOA0 Description 0 Always 0 output 0 1 0 output at TGRA compare match 0 1 output at TGRA compare match 0 1 1 Initial output is 0 output for TO pin Toggle output at TGRA compare match 0 Always 1 output 0 1 0 ...

Page 385: ... bit in TSR is set to 1 TCNT and TGRD compare match 0 Interrupt requests by TGFD disabled 1 Interrupt requests by TGFD enabled 2 TGIEC 0 R W TGR Interrupt Enable C Enables or disables interrupt requests by the TGFC bit when the TGFC bit in TSR is set to 1 TCNT and TGRC compare match 0 Interrupt requests by TGFC disabled 1 Interrupt requests by TGFC enabled 1 TGIEB 0 R W TGR Interrupt Enable B Enab...

Page 386: ...lue overflows changes from H FFFF to H 0000 3 TGFD 0 R W Output Compare Flag D Status flag that indicates the occurrence of TGRD compare match Clearing condition When 0 is written to TGFD after reading TGFD 1 Setting condition When TCNT TGRD 2 TGFC 0 R W Output Compare Flag C Status flag that indicates the occurrence of TGRC compare match Clearing condition When 0 is written to TGFC after reading ...

Page 387: ... TGR TGR are 16 bit registers TGRC and TGRD can also be designated for operation as buffer registers The initial value of TGR is H FFFF Note TGR buffer register combinations are TGRA TGRC and TGRB TGRD 14 3 8 Timer Start Register TSTR TSTR is a 16 bit readable writable register that selects TCNT operation stoppage for channels 0 to 3 Bit Bit Name Initial Value R W Description 15 to 4 0 R Reserved ...

Page 388: ...ing Buffer Operation When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR For update timing from a buffer register rewriting on compare match occurrence or on counter clearing can be selected PWM Mode In this mode a PWM waveform is output The output level can be set by means of TIOR A PWM waveform with a duty cycle of between 0 and 100 can be ...

Page 389: ...ter 1 2 4 3 6 Free running counter Start count Free running counter 6 Set external pin function 5 1 2 3 4 5 6 Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGRA to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR Design...

Page 390: ... match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR After the settings have been made TCNT starts up count operation as a periodic counter when the correspo...

Page 391: ...s output at the TO pin until the first compare match occurs 2 Set the timing for compare match generation in TGRA 3 Set the external pin function in pin function controller PFC 4 Set the CST bit in TSTR to 1 to start the count operation Figure 14 5 Example of Setting Procedure for Waveform Output by Compare Match Examples of waveform output operation Figure 14 6 shows an example of 0 output 1 outp...

Page 392: ...d TGRD to be used as buffer registers Table 14 6 shows the register combinations used in buffer operation Table 14 6 Register Combinations in Buffer Operation Timer General Register Buffer Register TGRA TGRC TGRB TGRD When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register For update timing from a buffer register rewri...

Page 393: ...er Operation Setting Procedure Example of Buffer Operation Figure 14 10 shows an operation example in which PWM mode has been designated for channel 0 and buffer operation has been designated for TGRA and TGRC The settings used in this example are TCNT clearing by compare match B 1 output at compare match A and 0 output at counter clearing Rewriting timing from the buffer register is set at counte...

Page 394: ...WM output is generated from the TO pin using TGRB as the period register and TGRA as duty cycle registers The output specified in TIOR is performed by means of compare matches Upon counter clearing by a period register compare match the output value of each pin is the initial value set in TIOR Set TIOR so that the initial output and an output value by compare match are different If the same levels...

Page 395: ...ck with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR 2 Use bits CCLR2 to CCLR0 in TCR to select the TGRB to be used as the TCNT clearing source 3 Use TIOR to select the initial value and output value 4 Set the period in TGRB and set the duty in TGRA 5 Select the PWM mode with bits MD2 to MD0 in TMDR 6 Set the external pin function in pin ...

Page 396: ... output value by TGRA compare match In this case the value set in TGRB is used as the period and the value set in TGRA as the duty TCNT value TGRB H 0000 TO Time TGRA Counter cleared by TGRB compare match Figure 14 12 Example of PWM Mode Operation 1 Figure 14 13 shows examples of PWM waveform output with 0 duty and 100 duty in PWM mode TCNT TGRA 1 TGRA 2 TGRA 3 Rewrite timing for TGRA Period TGRB ...

Page 397: ...tes hours date day of the week month and year 1 Hz to 64 Hz timer binary format Start stop function 30 second adjust function Alarm interrupt frame comparison of seconds minutes hours date day of the week month and year can be used as conditions for the alarm interrupt Periodic interrupts the interrupt cycle may be 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second or 2 seconds Ca...

Page 398: ...rcuit Oscillator circuit Prescaler 128 RYRAR RMONAR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR 64 Hz counter Second counter Minute counter Hour counter Day of the week counter Date counter Month counter Year counter Second alarm register RHRAR RMINAR RWKAR RDAYAR RMONAR RYRAR RCR1 RCR2 RCR3 Minute alarm register Hour alarm register Day of the week alarm register Date alarm ...

Page 399: ...L2 open when the RTC is not used 15 3 Register Descriptions The RTC has the following registers Refer to section 24 List of Registers for more detail of the address and access size 64 Hz counter R64CNT Second counter RSECCNT Minute counter RMINCNT Hour counter RHRCNT Day of week counter RWKCNT Date counter RDAYCNT Month counter RMONCNT Year counter RYRCNT Second alarm register RSECAR Minute alarm ...

Page 400: ...bit bits 6 to 0 indicates the state of the RTC divider circuit between 64 Hz and 1 Hz Bit Frequency 6 1 Hz 5 2 Hz 4 4 Hz 3 8 Hz 2 16 Hz 1 32 Hz 0 64 Hz 15 3 2 Second Counter RSECCNT The second counter RSECCNT is an 8 bit readable writable register used for setting counting in the BCD coded second section The count operation is performed by a carry for each second of the 64 Hz counter The range of ...

Page 401: ...nt operation with the START bit in RCR2 RMINCNT is not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 R W 10 unit of the minute counter in the BCD code The range that can be set is 0 to 5 decimal 3 to 0 R W 1 unit of the minute counter in the BCD code...

Page 402: ... week section The count operation is performed by a carry for each day of the date counter The range for day of the week that can be set is 0 to 6 decimal Errant operation will result if any other value is set Carry out write processing after stopping the count operation with the START bit in RCR2 RWKCNT is not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial...

Page 403: ...e BCD code The range that can be set is 0 to 3 decimal 3 to 0 R W 1 unit of the date counter in the BCD code The range that can be set is 0 to 9 decimal 15 3 7 Month Counter RMONCNT The month counter RMONCNT is an 8 bit readable writable register used for setting counting in the BCD coded month section The count operation is performed by a carry for each month of the date counter The range of mont...

Page 404: ...e year counter in the BCD code The range that can be set is 0 to 9 decimal 7 to 4 R W 10 unit of the year counter in the BCD code The range that can be set is 0 to 9 decimal 3 to 0 R W 1 unit of the year counter in the BCD code The range that can be set is 0 to 9 decimal 15 3 9 Second Alarm Register RSECAR The second alarm register RSECAR is an 8 bit readable writable register and an alarm registe...

Page 405: ...arison with the corresponding counter value is performed for those whose ENB bit is set to 1 and for RCR3 a comparison is performed when the YAEN bit is set to 1 If all of those match an RTC alarm interrupt is generated The range of minute alarm that can be set is 00 to 59 decimal Errant operation will result if any other value is set The ENB bit in RMINAR is initialized by a power on reset and it...

Page 406: ...e of hour alarm that can be set is 00 to 23 decimal Errant operation will result if any other value is set The ENB bit in RHRAR is initialized by a power on reset and it is not initialized by manual reset and standby mode The remaining RHRAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 ENB 0 R W Hour Alarm Enable Spe...

Page 407: ...ated The range of day of the week alarm that can be set is 0 to 6 decimal Errant operation will result if any other value is set The ENB bit in RWKAR is initialized by a power on reset and it is not initialized by manual reset and standby mode The remaining RWKAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 ENB 0 R W...

Page 408: ...nt operation will result if any other value is set The RDAYCNT range that can be set changes with some months and in leap years Please confirm the correct setting The ENB bit in RDAYAR is initialized by a power on reset and it is not initialized by manual reset and standby mode The remaining RDAYAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initi...

Page 409: ...of month alarm that can be set is 01 to 12 decimal Errant operation will result if any other value is set The ENB bit in RMONAR is initialized by a power on reset and it is not initialized by manual reset and standby mode The remaining RMONAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 ENB 0 R W Month Alarm Enable S...

Page 410: ...all of those match an RTC alarm interrupt is generated The range of year alarm that can be set is 0000 to 9999 decimal Errant operation will result if any other value is set The RYRAR contents are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 15 to 12 R W 1000 unit of year alarm setting in the BCD code The range that can be set is...

Page 411: ...ed CF is set to 1 when R64CNT or RSECCNT is read during a carry occurrence by R64CNT or RSECCNT A count register value read at this time cannot be guaranteed another read is required 0 No carry by R64CNT or RSECCNT Clearing condition When 0 is written to CF 1 Setting condition When R64CNT or RSECCNT is read during a carry occurrence by R64CNT or RSECCNT or 1 is written to CF 6 5 0 R Reserved These...

Page 412: ...ENB bit and YAEN bit is 1 15 3 17 RTC Control Register 2 RCR2 The RTC control register 2 RCR2 is an 8 bit readable writable register for periodic interrupt control 30 second adjustment ADJ divider circuit RESET and RTC count start stop control It is initialized to H 09 by a power on reset It is initialized except for RTCEN and START by a manual reset It is not initialized in standby mode and retai...

Page 413: ...iodic interrupt generated every 1 second 111 Periodic interrupt generated every 2 seconds 3 RTCEN 1 R W Controls the operation of the crystal oscillator for the RTC 0 Halts the crystal oscillator for the RTC 1 Runs the crystal oscillator for the RTC 2 ADJ 0 R W 30 Second Adjustment When 1 is written to the ADJ bit times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to ...

Page 414: ...comparison between the BCD coded year section counter RYRCNT of the RTC and the year alarm register RYRAR Bit Bit Name Initial Value R W Description 7 YAEN 0 R W Year Alarm Enable When this bit is set to 1 the year alarm register RYRAR is compared with the year counter RYRCNT For alarm registers RSECAR RMINAR RHRAR RWKAR RDAYAR and RMONAR a comparison with the corresponding counter value is perfor...

Page 415: ...ower is turned on 15 4 2 Setting Time Figure 15 2 shows how to set the time when the clock is stopped Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write 1 to START in the RCR2 register Set seconds minutes hour day day of the week month and year Stop clock reset divider circuit Start clock Figure 15 2 Setting Time ...

Page 416: ...uld normally be used Write 0 to CF in RCR1 Note Set AF to 1 so that alarm flag is not cleared Read RCR1 and check CF Write 0 to CIE in RCR1 Carry flag 1 No Yes Clear the carry flag Disable the carry interrupt Read counter register Write 1 to CIE in RCR1 and write 0 to CF in RCR1 Note Set AF in RCR1 to 1 so that alarm flag is not cleared Interrupt generated No Yes Enable the carry interrupt Clear t...

Page 417: ... 0 When the clock and alarm times match 1 is set in the AF bit in RCR1 Alarm detection can be checked by reading this bit but normally it is done by interrupt If 1 is placed in the AIE bit in RCR1 an interrupt is generated when an alarm occurs Disable interrupt to prevent erroneous interruption AIE bit in RCR1 is cleared Then write 1 Clock running Set alarm time Cancel alarm interrupt Always clear...

Page 418: ...f Typ value 10 MΩ RD Typ value 400 kΩ 3 Cin and Cout values include stray capacitance due to the wiring Take care when using a ground plane 4 The crystal oscillation settling time depends on the mounted circuit constants stray capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as p...

Page 419: ...nterval bits PES0 to PES2 in RCR2 When the time set by the PES0 to PES2 bits has elapsed the PEF bit is set to 1 The PEF is cleared to 0 upon periodic interrupt generation when the periodic interrupt interval bits PES0 to PES2 is set Periodic interrupt generation can be confirmed by reading this bit but normally the interrupt function is used Set PES0 to PES2 and clear PEF to 0 in RCR2 Clear PEF t...

Page 420: ...Rev 2 00 09 03 page 374 of 690 ...

Page 421: ...ight serial data communication formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none LSB first transfer Receive error detection Parity framing and overrun errors Break detection If a framing error is followed by at least one frame at the space 0 low level a break is detected Clock synchronous mode Serial data communication is synchronized with a clock Serial data communi...

Page 422: ...activated to execute a data transfer in the event of a transmit FIFO data empty transmit data stop or receive FIFO data full interrupt The DMAC requests of transmit FIFO data empty and transmit data stop interrupts are the same On chip modem control functions CTS and RTS On chip transmit data stop functions only in asynchronous mode When not in use the SCIF can be stopped by halting its clock supp...

Page 423: ...y check External clock Pφ Pφ 4 Pφ 16 Pφ 64 SCIF Bus interface Peripheral bus SCRSR Receive shift register SCFRDR Receive FIFO data register SCTSR Transmit shift register SCFTDR Transmit FIFO data register SCSMR Serial mode register SCSCR Serial control register SCFER FIFO error count register SCSSR Serial status register SCBRR Bit rate register SCFCR FIFO control register SCFDR FIFO data count reg...

Page 424: ...nput Transmission possible Modem control RTS0 RTS Output Transmit request 2 Serial clock SCK2 SCK Input output Clock input output Receive data RxD2 RxD 2 Input Receive data input Transmit data TxD2 TxD 2 Output Transmit data output Modem control CTS2 CTS Input Transmission possible Modem control RTS2 RTS Output Transmit request Notes 1 The pins are collectively called SCK RxD TxD CTS and RTS witho...

Page 425: ...IFO error count register 0 SCFER_0 Serial status register 0 SCSSR_0 FIFO control register 0 SCFCR_0 FIFO data count register 0 SCFDR_0 Transmit FIFO data register 0 SCFTDR_0 Receive FIFO data register 0 SCFRDR_0 2 Channel 2 Serial mode register 2 SCSMR_2 Bit rate register 2 SCBRR_2 Serial control register 2 SCSCR_2 Transmit data stop register 2 SCTDSR_2 FIFO error count register 2 SCFER_2 Serial s...

Page 426: ...cutive receive operations can be performed until the receive FIFO data register is full 64 data bytes SCFRDR is a read only register and cannot be written to by the CPU If a read is performed when there is no receive data in the receive FIFO data register an undefined value will be returned When the receive FIFO data register is full of receive data subsequent serial data is lost Bit Bit Name Init...

Page 427: ...al transmission SCFTDR is a write only register and cannot be read by the CPU The next data cannot be written when SCFTDR is filled with 64 bytes of transmit data Data written in this case is ignored Bit Bit Name Initial Value R W Description 7 to 0 SCFTD7 to SCFTD0 Undefined W Serial Transmit Data FIFO 16 3 5 Serial Mode Register SCSMR SCSMR is a 16 bit readable writable register used to set the ...

Page 428: ... 100 Sampling rate 1 29 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited 7 C A 0 R W Communication Mode Selects whether the SCI operates in the asynchronous or clock synchronous mode 0 Asynchronous mode 1 Clock synchronous mode 6 CHR 0 R W Character Length Selects seven or eight bits as the data length This setting is only valid in asynchronous mode In clock synchronous mode th...

Page 429: ...her even or odd parity for use in parity addition and checking The O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking The O E bit setting is invalid when parity addition and checking is disabled in asynchronous and clock synchronous mode 0 Even parity 1 1 Odd parity 2 Notes 1 When even parity is set parity bit addition is performed in transmission s...

Page 430: ...mode this setting is invalid since stop bits are not added 0 One stop bit 1 1 Two stop bits 2 Notes 1 In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sent 2 In transmission two 1 bits stop bits are added to the end of a transmit character before it is sent 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0...

Page 431: ... data stop interrupt when the TSE bit in SCFCR is enabled and the TSF flag in SCSSR is set to 1 0 Transmit data stop interrupt disabled 1 Transmit data stop interrupt enabled Note The interrupt request is cleared by clearing the TSF flag to 0 after reading 1 from it or clearing the TSIE bit to 0 10 ERIE 0 R W Receive Error Interrupt Enable Enables or disables generation of a receive error framing ...

Page 432: ...0 after reading 1 from it or clearing the DRIE bit to 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables generation of a transmit FIFO data empty interrupt request when the TDFE flag in SCSSR is set to 1 0 Transmit FIFO data empty interrupt request disabled 1 Transmit FIFO data empty interrupt request enabled Note The interrupt request is cleared by writing transmit data exceeding the tra...

Page 433: ...it FIFO reset before the TE bit is set to 1 4 RE 0 R W Receive Enable Enables or disables the start of serial reception by the SCIF 0 Reception disabled 1 1 Reception enabled 2 Notes 1 Clearing the RE bit to 0 does not affect the DR ER BRK RDF FER PER and ORER flags which retain their state 2 The serial mode register SCSMR and FIFO control register SCFCR settings must be made the receive format de...

Page 434: ...ut 2 11 External clock SCK pin functions as clock input 2 When data is sampled by the on chip baud rate generator set bits CKE1 and CKE0 to B 00 internal clock SCK pin functions as input pin input signal ignored When using the SCK pin as a port set bits CKE1 and CKE0 to B 00 Notes 1 In synchronous mode a clock with a frequency equal to the bit rate is output 2 In asynchronous mode a clock with a s...

Page 435: ...e After setting the ER bit in SCSSR the value of bits 13 to 8 indicates the number of parity error generated data When all 64 bytes of receive data in SCFRDR have parity errors the PER5 to PER0 bits indicate 0 7 6 0 R Reserved These bits are always read as 0 The write value should always be 0 5 to 0 FER5 to FER0 0 R Framing Error Count Indicates the number of data in which framing errors are gener...

Page 436: ... ORER 0 R W Overrun Error Indicates that an overrun error occurred during reception This bit is only valid in asynchronous mode 0 Reception in progress or reception has ended successfully 1 Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 2 Setting condition When serial reception is completed while receiv...

Page 437: ...ten to ER after reading ER 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 2 When in reception the number of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SCSMR Notes 1 The...

Page 438: ...and TTRG0 in the FIFO control register SCFCR and new transmit data can be written to SCFTDR 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR Clearing condition When transmit data exceeding the transmit trigger set number is written to SCFTDR and 0 is written to TDFE after reading TDFE 1 1 The number of transmit data bytes in SCFTDR does not ex...

Page 439: ...evel low level for at least one frame length Note 1 When a break is detected the receive data H 00 following detection is not transferred to SCFRDR When the break ends and the receive signal returns to mark 1 receive data transfer is resumed 3 FER 0 R Framing Error Indicates a framing error in the data read from SCFRDR in asynchronous mode 0 There is no framing error in the receive data read from ...

Page 440: ...ceive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register SCFCR 0 The number of receive data bytes in SCFRDR is less than the receive trigger set number Clearing conditions Power on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number and 0 is written to RDF after reading RDF 1 1 The number of rece...

Page 441: ...ion When SCFRDR contains fewer than the receive trigger set number of receive data bytes and no further data will arrive 1 Note 1 The DR bit is set 15 etu after the last data is received at a sampling rate of 1 16 regardless of the setting of the sampling control bits in SCSMR etu Elementary time unit time for transfer of one bit Note Only 0 can be written for clearing the flags 16 3 9 Bit Rate Re...

Page 442: ... 106 1 5 When sampling rate is 1 29 N Pφ 58 22n 1 B 106 1 Clock Synchronous Mode N Pφ 4 22n 1 B 106 1 Where B Bit rate bits s N SCBRR setting for baud rate generator Asynchronous mode 0 N 255 Clock synchronous mode 1 N 255 Pφ Peripheral module operating frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SCSMR Setting n Clock CKS1 C...

Page 443: ...When sampling rate is 1 16 Error Pφ 106 1 N B 32 22n 1 1 100 2 When sampling rate is 1 5 Error Pφ 106 1 N B 10 22n 1 1 100 3 When sampling rate is 1 11 Error Pφ 106 1 N B 22 22n 1 1 100 4 When sampling rate is 1 13 Error Pφ 106 1 N B 26 22n 1 1 100 5 When sampling rate is 1 27 Error Pφ 106 1 N B 58 22n 1 1 100 ...

Page 444: ...nous mode 0 Transmit data stop function disabled 1 Transmit data stop function enabled 14 TCRST 0 R W Transmit Count Reset Clears the transmit count to 0 This bit is valid only when the transmit data stop function is used 0 Transmit count reset disabled 1 Transmit count reset enabled clearing to 0 Note The transmit count is reset clearing to 0 is performed in power on reset or manual reset 13 to 1...

Page 445: ...ng transmit data bytes that sets the transmit FIFO data register empty TDFE flag in the serial status register SCSSR The TDFE flag is set when as the result of a transmit operation the number of transmit data bytes in the transmit FIFO data register SCFTDR falls to or below the trigger set number shown in below 00 32 32 01 16 48 10 2 62 11 0 64 Note The values in parentheses are the number of empt...

Page 446: ...ent of a power on reset or manual reset 1 RFRST 0 R W Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state 0 Reset operation disabled 1 Reset operation enabled Note A reset operation is performed in the event of a power on reset or manual reset 0 LOOP 0 R W Loopback Test Internally connects the transmit output pin TxD and ...

Page 447: ... is no transmit data and a value of H 40 means that SCFTDR is full of transmit data 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 0 R6 to R0 0 R These bits show the number of receive data bytes in SCFRDR A value of H 00 means that there is no receive data and a value of H 40 means that SCFRDR is full of receive data 16 3 12 Transmit Data Stop Register SCTDSR S...

Page 448: ...control register SCSCR Data length Choice of seven or eight bits Choice of parity addition and addition of one or two stop bits the combination of these parameters determines the transfer format and character length Detection of framing errors parity errors overrun errors receive FIFO data full state receive data ready state and breaks during reception Indication of the number of data bytes stored...

Page 449: ...mat Selection SCSMR Settings SCIF Transfer Format Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Multiprocessor Bit Parity Bit Stop Bit Length 0 0 0 Asynchronous mode 8 bit data None No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 1 0 0 7 bit data No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits ...

Page 450: ...be selected according to the SCSMR settings Table 16 3 Serial Transfer Formats SCSMR Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 1 S 8 bit data STOP STOP 1 0 S 8 bit data P STOP 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 S 7 bit data STOP STOP 1 0 S 7 bit data P STOP 1 S 7 bit data P STOP STOP S Start bit STOP Stop bit P...

Page 451: ...ed below When the transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure When the TE bit is cleared to 0 the transmit shift register SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the contents of SCSSR SCFTDR or SCFRDR The TE bit should be cleared to 0 after all transmit data has been sent and t...

Page 452: ...ts cleared to 0 1 Set the clock selection in SCSCR Be sure to clear bits RIE TIE TE and RE to 0 2 Set the transmit and receive format in SCSMR 3 Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit and RE bits in SCSCR to 1 Also set the RIE and TIE bits Setting the TE and RE bits enables the TxD and R...

Page 453: ... to 0 The number of data bytes that can be written is 64 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR and then clear the TDFE bit to 0 3 Break output at the end of serial transmission To output a break in serial transmission set the port SC data regist...

Page 454: ...egister SCTDSR is matched transmit operation is stopped and the TSF flag in the serial status register SCSSR is set If the TSIE bit in the serial control register SCSCR is set to 1 a transmit data stop interrupt TDI request is generated The vectors of transmit FIFO data empty and transmit data stop interrupts are the same The serial transmit data is sent from the TxD pin in the following order a S...

Page 455: ...I interrupt request Figure 16 4 Example of Transmit Operation Example with 8 Bit Data Parity One Stop Bit Transmit Data Stop Function When a value in the SCTDSR register is matched with the number of transmit data bytes this function stops the transmit operation Interrupts can be generated and the DMAC can be activated by setting the TSIE bit interrupt enable bit Figure 16 5 shows an example of op...

Page 456: ... an interrupt is enabled also set the TSIE bit to 1 2 If the TSF bit in SCSSR is set to 1 clear it to 0 after reading 1 When transmit data is written to SCFTDR in this state transmit operation is started 3 If the TSF bit is set to 1 transmit data stop number is matched with transmit data number transmit operation is stopped If the TSIE bit is set to 1 an interrupt is generated Serial transmission ...

Page 457: ...reak can also be detected by reading the value of the RxD pin 2 SCIF status check and receive data read Read SCSSR and check that RDF 1 then read the receive data in SCFRDR read 1 from the RDF flag and then clear the RDF flag to 0 The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt 3 Serial reception continuation procedure To continue serial reception read at leas...

Page 458: ...eive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR 2 When a break signal is received receive data is not transferred to SCFRDR while the BRK flag is set However note that the last data in SCFRDR is H 00 and the break data in which a framing error occurred is stored Error handling End ER 1 No Yes BRK 1 No Yes DR 1 No Yes 1 2 Figure 16 8 Sample Serial Reception Flowchar...

Page 459: ...lag is 0 indicating that the break state is not set If all the above checks are passed the receive data is stored in SCFRDR Note Reception continues when a receive error a framing error or parity error occurs 4 If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1 a receive FIFO data full interrupt RXI request is generated If the ERIE bit in SCSCR is set to 1 when the ER flag changes ...

Page 460: ...F Receive Operation Example with 8 Bit Data Parity One Stop Bit Modem Function When using a modem function transmission can be stopped and started again according to the CTS input value When the CTS is set to 1 during transmission the data enters a mark state after transmitting one frame When CTS is set to 0 the next transmit data is output starting with a start bit Figure 16 10 shows an example o...

Page 461: ...re provided for both transmission and reception reducing the CPU overhead and enabling fast continuous communication to be performed The operating clock source is selected using the serial mode register SCSMR The SCIF clock source is determined by the CKE1 and CKE0 bits in the serial control register SCSCR Transmit receive format Fixed 8 bit data Indication of the number of data bytes stored in th...

Page 462: ... data format is used No parity or multiprocessor bits are added 2 Clock An internal clock generated by the on chip baud rate generator or an external clock input through the SCK pin can be selected as the serial clock for the SCIF according to the setting of the CKE1 and CKE0 bits in SCSCR Eight serial clock pulses are output in the transfer of one character and when no transmission reception is p...

Page 463: ...ote that clearing the TE and RE bits to 0 does not change the contents of SCSSR SCFTDR or SCFRDR The TE bit should be cleared to 0 after all transmit data has been sent and the TEND bit in SCSSR has been set to 1 The TE bit should not be cleared to 0 during transmission if attempted the TxD pin will go to the high impedance state Before setting TE to 1 again to start transmission the TFRST bit in ...

Page 464: ...cleared to 0 Set C A bit in SCSMR to 1 Set CKS1 and CKS0 bits Set value in SCBRR Clear TFRST bit to 0 1 Be sure to set the TFRST bit in SCFCR to 1 to reset the FIFOs 2 Set the clock selection in SCSCR Be sure to clear bits RIE TIE TE and RE to 0 3 Set the clock source selection in SCSMR 4 Write a value corresponding to the bit rate into SCBRR 5 Clear the TFRST bit in SCFCR to 0 6 Set the transmit ...

Page 465: ... corresponding to the bit rate into SCBRR 5 Clear the RFRST bit in SCFCR to 0 6 Wait one bit interval Initialization Clear TE and RE bits in SCSCR to 0 Set RFRST bit in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR leaving TE and RE bits cleared to 0 Set C A bit in SCSMR to 1 Set CKS1 and CKS0 bits Set value in SCBRR Clear RFRST bit in SCFCR to 0 1 bit interval elapsed End 1 2 3 4 5 6 Figure 16 13 Sa...

Page 466: ...ber and clear the TDFE flag to 0 after reading it 7 Wait one bit interval Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR leaving TE and RE bits cleared to 0 Set C A bit in SCSMR to 1 Set CKS1 and CKS0 bits Set value in SCBRR Clear TFRST and RFRST bits to 0 Set transmit trigger number in TTRG1 and TTRG0 in SCFCR write transmi...

Page 467: ...ion after Initialization No Yes No Wait Yes 1 Set the transmit trigger number in SCFCR 2 Write transmit data to SCFTDR and clear the TDFE flag to 0 after reading 1 from it 3 Wait for one bit interval 4 Transmission is started when the TE bit in SCSCR is set to 1 5 After the end of transmission clear the TE bit to 0 Start of transmission Set transmit trigger number in TTRG1 and TTRG0 in SCFCR Write...

Page 468: ...e data while the RDF bit is 1 4 After the end of reception clear the RE bit to 0 Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR Set RE bit in SCSCR When using receive FIFO data interrupt set RIE bit to 1 RDF 1 Read receive trigger number of receive data bytes from SCFRDR Clear RE bit in SCSCR to 0 End of reception 1 2 3 4 Figure 16 15 Sample Serial Reception Flowchart 1 ...

Page 469: ... reception clear the RE bit to 0 Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR Set RFRST bit in SCFCR to 1 Clear RFRST bit in SCFCR to 0 1 bit interval elapsed Set RE bit in SCSCR When using receive FIFO data interrupt set RIE bit to 1 RDF 1 Read receive trigger number of receive data bytes from SCFRDR Clear RE bit in SCSCR to 0 End of reception 1 2 3 4 5 6 Figure 16 15...

Page 470: ... set simultaneously 4 After the end of transmission reception clear the TE and RE bits to 0 Start of simultaneous transmission reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR Write remaining transmit data to SCFTDR Read TDFE and RDF bits in SCSSR TDFE 1 RDF 1 Write 0 to TDFE and RDF bits in SCSSR after reading 1 from them Set TE and RE bits in SCSCR simultaneously When using trans...

Page 471: ...art of simultaneous transmission reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR and set transmit trigger number in TTRG1 and TTRG0 Set TFRST and RFRST bits in SCFCR to 1 Clear TFRST and RFRST bits in SCFCR to 0 Write transmit data to SCFTDR Read TDFE and RDF bits in SCSSR TDFE 1 RDF 1 Write 0 to TDFE and RDF bits in SCSSR after reading 1 from them 1 bit interval elapsed Set TE an...

Page 472: ...eration of TXI and TDI interrupt requests The DMAC requests of TXI and TDI are assigned to the same vector When the RDF flag in SCSSR is set to 1 an RXI interrupt request is generated The DMAC can be activated and data transfer performed on generation of an RXI interrupt request When using the DMAC for transmission reception set and enable the DMAC before making SCIF settings See section 8 Direct ...

Page 473: ...smit FIFO data empty flag TDFE or transmit data stop flag TSF Possible 2 Notes 1 The DMAC can be activated only by a receive FIFO data full interrupt request 2 The DMAC can be activated by a transmit FIFO data empty TDFE or transmit data stop TSF interrupt request When the DMAC is activated by the TSF interrupt it is cleared by either of two cases listed below 1 The TSF flag is read by the CPU 2 T...

Page 474: ...d the RDF Flag The RDF flag in the serial status register SCSSR is set when the number of receive data bytes in the receive FIFO data register SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register SCFCR After RDF is set receive data equivalent to the trigger number can be read from SCFRDR allowing efficient continuous recepti...

Page 475: ...latched at the rising edge of the fourth base clock pulse The receive margin can therefore be expressed as shown in equation 1 M 0 5 1 2N D 0 5 N L 0 5 F 1 F 100 1 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equati...

Page 476: ...Rev 2 00 09 03 page 430 of 690 ...

Page 477: ...nforms to the IrDA 1 0 system Asynchronous serial communication Data length 8 bits Stop bit length 1 bit Parity bit None On chip 64 stage FIFO buffers for both transmit and receive operations On chip baud rate generator with selectable bit rates Guard functions to protect the receiver during transmission Clock supply halted to reduce power consumption when not using the IrDA interface Figure 17 1 ...

Page 478: ...t be set in IrDA mode 17 3 Register Description The IrDA has the following internal registers For details on register addresses and register states in each processing state refer to section 24 List of Registers IrDA mode register SCSMR_Ir 17 3 1 IrDA Mode Register SCSMR_Ir SCSMR_Ir is a 16 bit register that selects IrDA or SCIF mode and selects the IrDA output pulse width This module operates as I...

Page 479: ... to generate the IRCLK clock pulse to be used for IrDA IRCLK is obtained as follows IRCLK 1 2N 2 Pφ N Value set by ICK3 to ICK0 2 PSEL 0 R W Output Pulse Width Select PSEL selects an IrDA output pulse width that is 3 16 of the bit length for 115 kbps or 3 16 of the bit length for the selected baud rate 0 Pulse width is 3 16 of the bit length 1 Pulse width is 3 16 of 115 kbps bit length for the bau...

Page 480: ...ation for infrared communication In the IrDA 1 0 specification communication is first performed at a speed of 9600 bps and the communication speed is changed However the communication rate cannot be automatically changed in this module so the communication speed should be confirmed and the appropriate speed set for this module by software 17 4 2 Transmitting The waveforms of a serial output signal...

Page 481: ...4 4 Data Format Specification The data format of UART frames used for IrDA communication must be specified by the SCIF0 registers The UART frame has eight data bits no parity bit and one stop bit IrDA communication is performed in asynchronous mode and this mode must also be specified by the SCIF0 registers The sampling rate must be set to 1 16 The internal clock must be selected for the SCIF0 ope...

Page 482: ...Rev 2 00 09 03 page 436 of 690 ...

Page 483: ...nt 2 EP2 Bulk in 64 128 Possible Endpoint 3 EP3 Interrupt 8 8 Configuration 1 Interface 0 Alternate Setting 0 Endpoint 1 Endpoint 2 Endpoint 3 Interrupt requests Generates various interrupt signals necessary for USB transmission reception Clock External input 48 MHz Refer to section 9 4 1 Frequency Control Register FRQCR and section 9 4 2 USB Clock Frequency Control Register UCLKCR Power down mode...

Page 484: ... shows the block diagram of the USB Peripheral bus Interrupt requests DMA transfer requests Status and control registers FIFO UDC Transceiver USB function module D D Clock 48 MHz UDC USB device controller Legend Figure 18 1 Block Diagram of USB ...

Page 485: ...able pin 1 VBUS Input USB cable connection monitor pin 1 or 0 SUSPND Output Transceiver suspend state output pin 1 EXTAL_USB Input USB clock input pin external clock input crystal resonator connect XTAL_USB Output USB clock pin crystal resonator connect D I O USB internal transceiver D D I O USB internal transceiver D Vcc USB Input Power supply for USB Vss USB Input Ground for USB Note The USB can...

Page 486: ...t register 0 ISR0 Interrupt select register 1 ISR1 Interrupt enable register 0 IER0 Interrupt enable register 1 IER1 EP0i data register EPDR0i EP0o data register EPDR0o EP0s data register EPDR0s EP1 data register EPDR1 EP2 data register EPDR2 EP3 data register EPDR3 EP0o receive data size register EPSZ0o EP1 receive data size register EPSZ1 Trigger register TRG Data status register DASTS FIFO clea...

Page 487: ...olds a value of 1 as long as there is valid data in the FIFO buffer This is a status bit and cannot be cleared 5 EP2TR 0 R W EP2 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled 4 EP2EMPT...

Page 488: ...with interrupt enable register 1 IER1 Clearing is performed by writing 0 to the bit to be cleared and 1 to the other bits Bit Bit Name Initial Value R W Description 7 to 4 0 R Reserved These bits are always read as 0 The write value should always be 0 3 VBUSMN 0 R This is a status bit which monitors the state of the VBUS pin This bit reflects the state of the VBUS pin 2 EP3TR 0 R W EP3 Transfer Re...

Page 489: ...pty 3 SETUPTS 0 R W Setup Command Receive Complete 2 EP0oTS 0 R W EP0o Receive Complete 1 EP0iTR 0 R W EP0i Transfer Request 0 EP0iTS 0 R W EP0i Transmit Complete 18 3 4 Interrupt Select Register 1 ISR1 ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 IFR1 If the USB issues an interrupt request to the INTC when a bit in ISR1 is cleared to 0 the inter...

Page 490: ...pty 3 SETUPTS 0 R W Setup Command Receive Complete 2 EP0oTS 0 R W EP0o Receive Complete 1 EP0iTR 0 R W EP0i Transfer Request 0 EP0iTS 0 R W EP0i Transmit Complete 18 3 6 Interrupt Enable Register 1 IER1 IER1 enables the interrupt requests of interrupt flag register 1 IFR1 When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1 an interrupt request is sent to th...

Page 491: ...0o receive data size register After the data has been read setting EP0oRDFN in the trigger register enables the next packet to be received This FIFO buffer can be initialized by means of BP0oCLR in the FCLR register Bit Bit Name Initial Value R W Description 7 to 0 D7 to D0 Undefined R Data register for control out transfer 18 3 9 EP0s Data Register EPDR0s EPDR0s is an 8 byte FIFO buffer specifica...

Page 492: ... configuration and has a capacity of twice the maximum packet size When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set one packet of transmit data is fixed and the dual FIFO buffer is switched over The transmit data for this FIFO buffer can be transferred by DMA This FIFO buffer can be initialized by means of EP2CLR in the FCLR register Bit Bit Name Initial...

Page 493: ...ndpoint 0 18 3 14 EP1 Receive Data Size Register EPSZ1 EPSZ1 is a receive data size resister for endpoint 1 EPSZ1 indicates the number of bytes received from the host The FIFO for endpoint 1 has a dual buffer configuration The size of the received data indicated by this register is the size of the currently selected side can be read by CPU Bit Bit Name Initial Value R W Description 7 to 0 0 R Numb...

Page 494: ...E Undefined W EP2 Packet Enable After one packet of data has been written to the endpoint 2 transmit FIFO buffer the transmit data is fixed by writing 1 to this bit 3 Undefined Reserved The write value should always be 0 2 EP0sRDFN Undefined W EP0s Read Complete Write 1 to this bit after data for the EP0s command FIFO has been read Writing 1 to this bit enables transfer of data in the following da...

Page 495: ...er contains valid data 3 to 1 0 R Reserved This bit is always read as 0 0 EP0iDE 0 R EP0i Data Present This bit is set when the endpoint 0 FIFO buffer contains valid data 18 3 17 FIFO Clear Register FCLR FCLR is a register to initialize the FIFO buffers for each endpoint Writing 1 to a bit clears all the data in the corresponding FIFO buffer Note that the corresponding interrupt flag is not cleare...

Page 496: ...iCLR Undefined W EP0i Clear Writing 1 to this bit initializes the endpoint 0 transmit FIFO buffer 18 3 18 DMA Transfer Setting Register DMAR DMA transfer can be carried out between the endpoint 1 and 2 data registers and memory by means of the on chip direct memory access controller DMA Dual address transfer is performed in bytes To start DMA transfer DMAC settings must be made in addition to the ...

Page 497: ...if there is still space in the other of the two FIFOs a transfer request is asserted for the DMAC again However if the size of the data packet to be transmitted is less than 64 bytes the EP2 packet enable bit is not set automatically and so should be set by the CPU with a DMA transfer end interrupt As EP2 related interrupt requests to the CPU are not automatically masked interrupt requests should ...

Page 498: ... the FIFO buffer a transfer request is asserted for the DMAC In DMA transfer when all the received data is read EP1 is read automatically and the completion trigger operates EP1 related interrupt requests to the CPU are not automatically masked Operating procedure 1 Write of 1 to the EP1 DMAE bit in DMAR 2 Transfer count setting in the DMAC 3 DMAC activation 4 DMA transfer 5 DMA transfer end inter...

Page 499: ...ite value should always be 0 3 EP3STL 0 R W EP3 Stall When this bit is set to 1 endpoint 3 is placed in the stall state 2 EP2STL 0 R W EP2 Stall When this bit is set to 1 endpoint 2 is placed in the stall state 1 EP1STL 0 R W EP1 Stall When this bit is set to 1 endpoint 1 is placed in the stall state 0 EP0STL 0 R W EP0 Stall When this bit is set to 1 endpoint 0 is placed in the stall state 18 3 20...

Page 500: ...leted enable D pull up in general output port Clear VBUS flag IFR1 VBUS Firmware preparations for start of USB communication Clear bus reset flag IFR0 BRST Clear FIFOs EP0 EP1 EP2 EP3 Yes No Initial settings Wait for setup command reception complete interrupt Interrupt request Interrupt request Figure 18 2 Cable Connection Operation The above flowchart shows the operation in the case of in section...

Page 501: ...y 18 4 3 Control Transfer Control transfer consists of three stages setup data not always included and status figure 18 4 The data stage comprises a number of bus transactions Operation flowcharts for each stage are shown below Control in Setup stage Data stage Status stage Control out No data SETUP 0 DATA0 SETUP 0 DATA0 SETUP 0 DATA0 IN 1 DATA1 OUT 1 DATA1 IN 0 DATA0 OUT 0 DATA0 IN 0 1 DATA0 1 OU...

Page 502: ...1 to EP0s read complete bit TRG EP0s RDFN 1 To control in data stage To control out data stage Command to be processed by application Interrupt request Yes No Notes 1 In the setup stage the application analyzes command data from the host requiring processing by the application and determines the subsequent processing for example data stage direction etc 2 When the transfer direction is control out...

Page 503: ...rmines the subsequent data stage direction If the result of command data analysis is that the data stage is in transfer one packet of data to be sent to the host is written to the FIFO If there is more data to be sent this data is written to the FIFO after the data written first has been sent to the host EP0iTS bit in IFR0 1 The end of the data stage is identified when the host transmits an OUT to...

Page 504: ...CK NACK ACK No Yes No Yes Interrupt request Figure 18 7 Data Stage Control Out Operation The application first analyzes command data from the host in the setup stage and determines the subsequent data stage direction If the result of command data analysis is that the data stage is out transfer the application waits for data from the host and after data is received EP0oTS bit in IFR0 1 reads data f...

Page 505: ...tion complete flag IFR0 EP0o TS 1 Clear EP0o reception complete flag IFR0 EP0o TS 0 Write 1 to EP0o read complete bit TRG EP0o RDFN 1 End of control transfer ACK Interrupt request Figure 18 8 Status Stage Control In Operation The control in status stage starts with an OUT token from the host The application receives 0 byte data from the host and ends control transfer ...

Page 506: ...l Out Operation The control out status stage starts with an IN token from the host When an IN token is received at the start of the status stage there is not yet any data in the EP0i FIFO and so an EP0i transfer request interrupt is generated The application recognizes from this interrupt that the status stage has started Next in order to transmit 0 byte data to the host 1 is written to the EP0i p...

Page 507: ...k Out Transfer Operation EP1 has two 64 byte FIFOs but the user can receive data and read receive data without being aware of this dual FIFO configuration When one FIFO is full after reception is completed the EP1FULL bit in IFR0 is set After the first receive operation into one of the FIFOs when both FIFOs are empty the other FIFO is empty and so the next packet can be received immediately When b...

Page 508: ...erformed for one FIFO For example even if both FIFOs are empty it is not possible to perform EP2PKTE at one time after consecutively writing 128 bytes of data EP2PKTE must be performed for each 64 byte write When performing bulk in transfer as there is no valid data in the FIFOs on reception of the first IN token an EP2TR bit interrupt in IFR0 is requested With this interrupt 1 is written to the E...

Page 509: ...a register EPDR3 Write 1 to EP3 packet enable bit TRG EP3 PKTE 1 Clear EP3 transmission complete flag IFR1 EP3 TS 0 Write data to EP3 data register EPDR3 Write 1 to EP3 packet enable bit TRG EP3 PKTE 1 Valid data in EP3FIFO Is there data for transmission to host Is there data for transmission to host No Yes No Yes No Yes NACK ACK Note This flowchart shows just one example of interrupt transfer pro...

Page 510: ...ress Set Configuration Set Feature Set Interface Get Descriptor Class Vendor command Set Descriptor Sync Frame If decoding is not necessary on the application side command decoding and data stage and status stage processing are performed automatically No processing is necessary by the user An interrupt is not generated in this case If decoding is necessary on the application side this module store...

Page 511: ...s bits are not changed at this time When a transaction is sent from the host for the endpoint for which the EPSTL bit was set the USB function module references the internal status bit and if this is not set references the corresponding bit in EPSTL 1 2 in figure 18 13 If the corresponding bit in EPSTL is set the USB function module sets the internal status bit and returns a stall handshake to the...

Page 512: ... EPSTL referenced 1 Transmission of STALL handshake 1 Internal status bit cleared to 0 1 Internal status bit cleared to 0 2 EPSTL not changed 1 1 set in EPSTL 2 Internal status bit set to 1 3 Transmission of STALL handshake 1 EPSTL cleared to 0 by application 2 IN OUT token received from host 3 Internal status bit already set to 1 4 EPSTL not referenced 5 Internal status bit not changed To 1 2 Int...

Page 513: ...therefore the internal status bit must be cleared with a Clear Feature command 3 1 in figure 18 14 If set by the application EPSTL should also be cleared 2 1 in figure 18 14 1 Transition from normal operation to stall 1 1 2 When transaction is performed when internal status bit is set and Clear Feature is sent 2 1 STALL handshake Transaction request STALL handshake 2 2 Clear Feature command 3 When...

Page 514: ...FO the FIFO automatically enters the FULL state and the data in the FIFO can be transmitted see figures 18 15 and 18 16 18 7 2 DMA Transfer for Endpoint 1 When the data received at EP1 is transferred by the DMAC the USB function module automatically performs the same processing as writing 1 to the RDFN bit in TRG if the currently selected FIFO becomes empty Accordingly in DMA transfer do not write...

Page 515: ...e host In this case internal processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed twice This internal processing is performed when the currently selected data FIFO becomes full Accordingly this processing is automatically performed only when 64 byte data is sent When the last 22 bytes are sent the internal processing for writing 1 to the PKTE bit is not perfo...

Page 516: ...ub side and the USB module will mistakenly identify this as reception of a USB bus reset from the host Therefore the D pull up control signal and VBUS pin input signal should be controlled using a general output port and the USB cable VBUS AND circuit as shown in figure 18 17 The UDC core in this LSI maintains the powered state when the VBUS pin is low regardless of the D D state 3 Detection of US...

Page 517: ...off IC allowing voltage application when system LSI power is off USB connector USB cable Note Operation is not guaranteed with this sample circuit If external surge and ESD noise countermeasures are required for the system a protective diode or the noise canceler should be used for this purpose Figure 18 17 Example of USB Function Module External Circuitry Internal Transceiver ...

Page 518: ...stem LSI power is off IC allowing voltage application when system LSI power is off USB connector USB cable Note Operation is not guaranteed with this sample circuit If external surge and ESD noise countermeasures are required for the system a protective diode or the noise canceler should be used for this purpose This LSI EXTAL_USB 48 MHz Figure 18 18 Example of USB Function Module External Circuit...

Page 519: ...ta it must not be cleared 18 9 3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module 1 Receive data registers The receive data registers must not be read exceeding the valid amount of receive data that is the number of bytes indicated by the receive data size register Even for EPDR1 which has double FIFO buffers the maximum da...

Page 520: ...rupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host However at the timing shown in figure 18 19 multiple TR interrupts occur successively Take appropriate measures against malfunction in such a case Note This module determines whether to return NAK if the FIFO of the target EP has no data when receiving the IN token but the TR interrupt flag is se...

Page 521: ...t output BSC A PTA1 input output port PINT1 input INTC D17 input output BSC A PTA0 input output port PINT0 input INTC D16 input output BSC B PTB7 input output port PINT15 input INTC D31 input output BSC B PTB6 input output port PINT14 input INTC D30 input output BSC B PTB5 input output port PINT13 input INTC D29 input output BSC B PTB4 input output port PINT12 input INTC D28 input output BSC B PTB...

Page 522: ...E2 input output port IRQ5 input INTC E PTE1 input output port DACK1 output DMAC E PTE0 input output port DACK0 output DMAC F PTF7 input output port ASEMD0 input F PTF6 input output port ASEBRKAK output F PTF5 input output port TDO output UDI F PTF4 input output port AUDSYNC output AUD F PTF3 input output port AUDATA3 output AUD TO3 output TPU F PTF2 input output port AUDATA2 output AUD TO2 output ...

Page 523: ...TJ4 output port NF 1 J PTJ3 output port NF 1 J PTJ2 output port NF 1 J PTJ1 output port NF 1 J PTJ0 output port NF 1 K PTK7 input output port A25 output BSC K PTK6 input output port A24 output BSC K PTK5 input output port A23 output BSC K PTK4 input output port A22 output BSC K PTK3 input output port A21 output BSC K PTK2 input output port A20 output BSC K PTK1 input output port A19 output BSC K P...

Page 524: ...PT0 input port 2 RXD0 input SCIF0 IrRX input IrDA SCPT SCPT0 output port 2 TXD0 output SCIF0 IrTX output IrDA Notes 1 The initial functions of NF No Function pins are not assigned after power on reset Specifies the functions with Pin Function Controller PFC PTD5 and PTM4 must be pulled up PTJ 7 0 must be open except for the pins specified as port output pins The values of PTJ6 PTJ1 and PTJ0 differ...

Page 525: ... C control register PCCR Port D control register PDCR Port E control register PECR Port E control register 2 PECR2 Port F control register PFCR Port F control register 2 PFCR2 Port G control register PGCR Port H control register PHCR Port J control register PJCR Port K control register PKCR Port L control register PLCR Port M control register PMCR Port N control register PNCR Port N control regist...

Page 526: ...6MD0 0 0 R W R W PTA6 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 PA5MD1 PA5MD0 0 0 R W R W PTA5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PA4MD1 PA4MD0 0 0 R W R W PTA4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS ...

Page 527: ... PTA0 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 19 2 2 Port B Control Register PBCR PBCR is a 16 bit readable writable register that selects the pin function and input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 PB7MD1 PB7MD0 0 0 R W R W PTB7 Mode 00 Other functions see table 19 1 01 Port output 10 Port...

Page 528: ...1 PB3MD0 0 0 R W R W PTB3 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 5 4 PB2MD1 PB2MD0 0 0 R W R W PTB2 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 3 2 PB1MD1 PB1MD0 0 0 R W R W PTB1 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MO...

Page 529: ...6MD0 1 1 R W R W PTC6 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 PC5MD1 PC5MD0 0 0 R W R W PTC5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PC4MD1 PC4MD0 0 0 R W R W PTC4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS ...

Page 530: ...tput 10 Port input pull up MOS On 11 Port input pull up MOS Off 3 2 PC1MD1 PC1MD0 0 0 R W R W PTC1 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 1 0 PC0MD1 PC0MD0 0 0 R W R W PTC0 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off ...

Page 531: ...2 PD6MD1 PD6MD0 1 1 R W R W PTD6 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 PD5MD1 PD5MD0 0 0 R W R W PTD5 Mode 00 NF 01 Setting prohibited 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PD4MD1 PD4MD0 0 0 R W R W PTD4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port...

Page 532: ...tput 10 Port input pull up MOS On 11 Port input pull up MOS Off 3 2 PD1MD1 PD1MD0 1 1 R W R W PTD1 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 1 0 PD0MD1 PD0MD0 0 0 R W R W PTD0 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off ...

Page 533: ...ort input pull up MOS On 11 Port input pull up MOS Off 11 10 PE5MD1 PE5MD0 0 0 R W R W PTE5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PE4MD1 PE4MD0 0 0 R W R W PTE4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 7 6 PE3MD1 PE3MD0 1 0 R W R W PTE3 Mode 00 Othe...

Page 534: ... Control Register 2 PECR2 PECR2 is an 8 bit readable writable register that selects the pin function Bit Bit Name Initial Value R W Description 7 6 0 R Reserved These bits are always read as 0 The write value should always be 0 5 PE5MD2 0 R W PE5 Mode 2 This bit is valid when the PE5MD 1 0 bits in PECR are set to B 00 other functions 0 STATUS1 CPG 1 CTS0 SCIF0 4 PE4MD2 0 R W PE4 Mode 2 This bit is...

Page 535: ... 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 PF5MD1 PF5MD0 0 0 R W R W PTF5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PF4MD1 PF4MD0 1 1 0 R W R W PTF4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 7 6 PF3MD1 PF3MD0 1 1 0 R W R W PTF3 Mod...

Page 536: ...hen ASEMD0 1 When ASEMD0 0 the relevant bit becomes 0 and other functions is selected 2 Pull up MOS on 19 2 8 Port F Control Register 2 PFCR2 PFCR2 is an 8 bit readable writable register that selects the pin function Bit Bit Name Initial Value R W Description 7 to 4 0 R Reserved These bits are always read as 0 The write value should always be 0 3 PF3MD2 0 R W PTF3 Mode 2 This bit is valid when the...

Page 537: ... 16 bit readable writable register that selects the pin function and input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 PG7MD1 PG7MD0 0 0 R W R W PTG7 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 13 12 PG6MD1 PG6MD0 0 0 R W R W PTG6 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up...

Page 538: ...MD1 PG2MD0 0 0 R W R W PTG2 Mode 00 Other functions 2 see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 3 2 PG1MD1 PG1MD0 0 0 R W R W PTG1 Mode 00 Other functions 2 see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 1 0 PG0MD1 PG0MD0 0 0 R W R W PTG0 Mode 00 Other functions 2 see table 19 1 01 Port output 10 Port input pu...

Page 539: ...11 Port input pull up MOS Off 11 10 PH5MD1 PH5MD0 1 1 R W R W PTH5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PH4MD1 PH4MD0 0 0 R W R W PTH4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 7 6 PH3MD1 PH3MD0 0 0 R W R W PTH3 Mode 00 Other functions see table 19 ...

Page 540: ...put pull up MOS On 11 Port input pull up MOS Off 19 2 11 Port J Control Register PJCR PJCR is a 16 bit readable writable register that selects the pin function Bit Bit Name Initial Value R W Description 15 14 PJ7MD1 PJ7MD0 0 0 R W R W PTJ7 Mode 00 NF 01 Port output 10 Setting prohibited 11 Setting prohibited 13 12 PJ6MD1 PJ6MD0 0 0 R W R W PTJ6 Mode 00 NF 01 Port output 10 Setting prohibited 11 Se...

Page 541: ... 0 R W R W PTJ3 Mode 00 NF 01 Port output 10 Setting prohibited 11 Setting prohibited 5 4 PJ2MD1 PJ2MD0 0 0 R W R W PTJ2 Mode 00 NF 01 Port output 10 Setting prohibited 11 Setting prohibited 3 2 PJ1MD1 PJ1MD0 0 0 R W R W PTJ1 Mode 00 NF 01 Port output 10 Setting prohibited 11 Setting prohibited 1 0 PJ0MD1 PJ0MD0 0 0 R W R W PTJ0 Mode 00 NF 01 Port output 10 Setting prohibited 11 Setting prohibited...

Page 542: ...ut 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 PK5MD1 PK5MD0 0 0 R W R W PTK5 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 9 8 PK4MD1 PK4MD0 0 0 R W R W PTK4 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 7 6 PK3MD1 PK3MD0 0 0 R W R W PTK3 Mode ...

Page 543: ... PK1MD0 0 0 R W R W PTK1 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 1 0 PK0MD1 PK0MD0 0 0 R W R W PTK0 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off ...

Page 544: ... see table 19 1 01 Setting prohibited 10 Setting prohibited 11 Port input pull up MOS Off 5 4 PL2MD1 PL2MD0 0 0 R W R W PTL2 Mode 00 Other functions see table 19 1 01 Setting prohibited 10 Setting prohibited 11 Port input pull up MOS Off 3 2 PL1MD1 PL1MD0 0 0 R W R W PTL1 Mode 00 Other functions see table 19 1 01 Setting prohibited 10 Setting prohibited 11 Port input pull up MOS Off 1 0 PL0MD1 PL0...

Page 545: ...able 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 11 10 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PM4MD1 PM4MD0 0 0 R W R W PTM4 Mode 00 NF 01 Setting prohibited 10 Port input pull up MOS On 11 Port input pull up MOS Off 7 6 PM3MD1 PM3MD0 1 0 R W R W PTM3 Mode 00 Setting prohibited 01 Port output 10 Port input pull up MOS ...

Page 546: ...PNCR is a 16 bit readable writable register that selects the pin function and input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 PN7MD1 PN7MD0 1 0 R W R W PTN7 Mode 00 Setting prohibited 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 13 12 PN6MD1 PN6MD0 1 0 R W R W PTN6 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MO...

Page 547: ...tput 10 Port input pull up MOS On 11 Port input pull up MOS Off 5 4 PN2MD1 PN2MD0 1 0 R W R W PTN2 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 3 2 PN1MD1 PN1MD0 1 0 R W R W PTN1 Mode 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off 1 0 PN0MD1 PN0MD0 1 0 R W R W PTN0 Mode ...

Page 548: ...rohibited 1 DPLS USB 5 PN5MD2 0 R W PTN5 Mode 2 This bit is valid when the PN5MD 1 0 bits in PNCR are set to B 00 other functions 0 Setting prohibited 1 DMNS USB 4 PN4MD2 0 R W PTN4 Mode 2 This bit is valid when the PN4MD 1 0 bits in PNCR are set to B 00 other functions 0 Setting prohibited 1 TXDPLS USB 3 PN3MD2 0 R W PTN3 Mode 2 This bit is valid when the PN3MD 1 0 bits in PNCR are set to B 00 ot...

Page 549: ... become valid only when transmission reception operation is disabled by the settings of SCSCR in the on chip serial communication interface SCIF When the TE bit in SCSCR_0 or SCSCR_2 of the SCIF is set to 1 the output status of other functions TxD0 or TxD2 has priority for the setting of SCPCR Similarly when the RE bit in SCSCR_0 or SCSCR_2 is set to 1 the input status of other functions RxD0 or R...

Page 550: ...function and input pull up MOS control When TE 0 and RE 0 in SCSCR_2 operation is as follows 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off When TE 1 in SCSCR_2 the SCPT2 TxD2 pin functions as TxD2 When RE 1 in SCSCR_2 the SCPT2 RxD2 pin functions as RxD2 Note Since two pins TxD2 and RxD2 are used to access one bit SCPT2 there is no comb...

Page 551: ...E 0 and RE 0 in SCSCR_0 operation is as follows 00 Other functions see table 19 1 01 Port output 10 Port input pull up MOS On 11 Port input pull up MOS Off When TE 1 in SCSCR_0 the SCPT0 TxD0 pin functions as TxD0 When RE 1 in SCSCR_0 the SCPT0 RxD0 pin functions as RxD0 Note Since two pins TxD0 and RxD0 are used to access one bit SCPT0 there is no combination of simultaneous input output of SCPT0...

Page 552: ...Rev 2 00 09 03 page 506 of 690 ...

Page 553: ...up MOS which is controlled by the port A control register PACR in the PFC Port A PTA7 input output D23 input output PINT7 input PTA6 input output D22 input output PINT6 input PTA5 input output D21 input output PINT5 input PTA4 input output D20 input output PINT4 input PTA3 input output D19 input output PINT3 input PTA2 input output D18 input output PINT2 input PTA1 input output D17 input output PI...

Page 554: ...o PADR but no effect on pin state 1 Output PADR value Written data is output from the pin 1 0 Input Pull up MOS on Pin state Data can be written to PADR but no effect on pin state 1 Input Pull up MOS off Pin state Data can be written to PADR but no effect on pin state Note n 0 to 7 20 2 Port B Port B is an 8 bit input output port with the pin configuration shown in figure 20 2 Each pin has an inpu...

Page 555: ...DR bit is returned directly When the function is general input port if the port is read the corresponding pin level is read Bit Bit Name Initial Value R W Description 7 to 0 PB7DT to PB0DT 0 R W Table 20 2 shows the function of PBDR Table 20 2 Port B Data Register PBDR Read Write Operations PBCR State PBnMD1 PBnMD0 Pin State Read Write 0 0 Other function PBDR value Data can be written to PBDR but ...

Page 556: ... output Figure 20 3 Port C 20 3 1 Register Description Port C has the following register For details on the register address and access size see section 24 List of Registers Port C data register PCDR 20 3 2 Port C Data Register PCDR PCDR is an 8 bit readable writable register that stores data for pins PTC7 to PTC0 Bits PC7DT to PC0DT correspond to pins PTC7 to PTC0 When the pin function is general...

Page 557: ... register PDCR in the PFC Port D PTD7 input output CS6B output PTD6 input output CS5B output PTD5 input NF input PTD4 input output CKE output PTD3 input output CASU output PTD2 input output CASL output PTD1 input output RASU output PTD0 input output RASL output Figure 20 4 Port D 20 4 1 Register Description Port D has the following register For details on the register address and access size see s...

Page 558: ...itten data is output from the pin 1 0 Input Pull up MOS on Pin state Data can be written to PDDR but no effect on pin state 1 Input Pull up MOS off Pin state Data can be written to PDDR but no effect on pin state Note n 0 to 4 6 and 7 PDCR State PD5MD1 PD5MD0 Pin State Read Write 0 0 NF PDDR value Data can be written to PDDR but no effect on pin state 1 Setting Prohibited 1 0 Input Pull up MOS on ...

Page 559: ...ut Figure 20 5 Port E 20 5 1 Register Description Port E has the following register For details on the register address and access size see section 24 List of Registers Port E data register PEDR 20 5 2 Port E Data Register PEDR PEDR is an 8 bit readable writable register that stores data for pins PTE7 to PTE0 Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0 When the pin function is general outp...

Page 560: ...put output ASEMD0 input PTF6 input output ASEBRKAK output PTF5 input output TDO output PTF4 input output AUDSYNC output PTF3 input output AUDATA3 output TO3 output PTF2 input output AUDATA2 output TO2 output PTF1 input output AUDATA1 output TO1 output PTF0 input output AUDATA0 output TO0 output Figure 20 6 Port F 20 6 1 Register Description Port F has the following register For details on the regi...

Page 561: ... Pin state Data can be written to PFDR but no effect on pin state Note n 0 to 7 20 7 Port G Port G is an 8 bit input port with the pin configuration shown in figure 20 7 Each pin has an input pull up MOS which is controlled by the port G control register PGCR in the PFC Port G PTG5 input output BACK output PTG4 input output AUDCK output PTG3 input output TRST input PTG2 input output TMS input PTG1...

Page 562: ...tate Read Write 0 0 Other function PGDR value Data can be written to PGDR but no effect on pin state 1 Output PGDR value Written data is output from the pin 1 0 Input Pull up MOS on Pin state Data can be written to PGDR but no effect on pin state 1 Input Pull up MOS off Pin state Data can be written to PGDR but no effect on pin state Note n 0 to 7 20 8 Port H Port H is a 7 bit input output port wi...

Page 563: ...nction is general input port if the port is read the corresponding pin level is read Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 0 PH6DT to PH0DT 0 R W Table 20 8 shows the function of PHDR Table 20 8 Port H Data Register PHDR Read Write Operations PHCR State PHnMD1 PHnMD0 Pin State Read Write 0 0 Other function PHD...

Page 564: ...on Port J has the following register For details on the register address and access size see section 24 List of Registers Port J data register PJDR 20 9 2 Port J Data Register PJDR PJDR is an 8 bit readable writable register that stores data for pins PTJ7 to PTJ0 Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0 When the pin function is general output port if the port is read the value of the co...

Page 565: ...tput A24 output PTK5 input output A23 output PTK4 input output A22 output PTK3 input output A21 output PTK2 input output A20 output PTK1 input output A19 output PTK0 input output A0 output Figure 20 10 Port K 20 10 1 Register Description Port K has the following register For details on the register address and access size see section 24 List of Registers Port K data register PKDR 20 10 2 Port K Da...

Page 566: ...om the pin 1 0 Input Pull up MOS on Pin state Data can be written to PKDR but no effect on pin state 1 Input Pull up MOS off Pin state Data can be written to PKDR but no effect on pin state Note n 0 to 7 20 11 Port L Port L is a 4 bit input port with the pin configuration shown in figure 20 11 Port L PTL3 input AN3 input PTL2 input AN2 input PTL1 input AN1 input PTL0 input AN0 input Figure 20 11 P...

Page 567: ...Port L Data Register PLDR Read Write Operation PLCR State PLnMD1 PLnMD0 Pin State Read Write 0 0 Other function Read as 0 Invalid no effect on pin state 1 Setting prohibited 0 Setting prohibited 1 1 Input Pull up MOS off Pin state Invalid no effect on pin state Note n 0 to 3 20 12 Port M Port M is a 6 bit input output port with the pin configuration shown in figure 20 12 Each pin has an input pull...

Page 568: ...rresponding pin level is read Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 PM6DT 0 R W Table 20 12 shows the function of PMDR 5 0 R Reserved This bit is always read as 0 The write value should always be 0 4 to 0 PM4DT to PM0DT 0 R W Table 20 12 shows the function of PMDR Table 20 12 Port M Data Register PMDR Read Write ...

Page 569: ...nput output PTN6 input output DPLS input PTN5 input output DMNS input PTN4 input output TXDPLS output PTN3 input output TXDMNS output PTN2 input output XVDATA input PTN1 input output TXENL output PTN0 input output SUSPND output Figure 20 13 Port N 20 13 1 Register Description Port N has the following register For details on the register address and access size see section 24 List of Registers Port...

Page 570: ...up MOS off Pin state Data can be written to PNDR but no effect on pin state Note n 0 to 7 20 14 SC Port The SC port is an 8 bit input output port with the pin configuration shown in figure 20 14 Each pin has an input pull up MOS which is controlled by the SC port control register SCPCR in the PFC SC Port SCPT5 input output CTS2 input SCPT4 input output RTS2 output SCPT3 input output SCK2 input out...

Page 571: ...e serial communication interface with FIFO SCIF is set to 1 the RxD2 and RxD0 pins become input pins and their states can be read regardless of the setting of SCPCR Bit Bit Name Initial Value R W Description 7 6 0 R Reserved These bits are always read as 0 The write value should always be 0 5 to 0 SCP5DT to SCP0DT 0 R W Table 20 14 shows the function of SCPDR Table 20 14 SC Port Data Register SCPD...

Page 572: ... value Written data is output on TxD pin 1 0 TxD Output high impedance RxD Input Pull up MOS on RxD pin state Data can be written to SCPDR but no effect on pin state 1 TxD Output high impedance RxD Input Pull up MOS off RxD pin state Data can be written to SCPDR but no effect on pin state Note n 0 and 2 The operations are not guaranteed when read and write operations are prohibited ...

Page 573: ...annel Pφ 33 MHz operation Three conversion modes Single mode A D conversion on one channel Multi mode A D conversion on one to four channels Scan mode Continuous A D conversion on one to four channels Four 16 bit data registers A D conversion results are transferred for storage into 16 bit data registers corresponding to the channels Sample and hold function Interrupt source At the end of A D conv...

Page 574: ...r Control circuit Successive approxi mation register Comparator Sample and hold circuit ADI interrupt signal AVSS AN0 AN1 AN2 AN3 Pφ 8 Pφ 16 ADCSR Pφ 4 AVCC ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D Legend Internal data bus ADDRC Figure 21 1 Block Diagram of A D Converter ...

Page 575: ...ce voltage for A D conversion Analog ground AVss Input Analog ground and reference voltage for A D conversion Analog input 0 AN0 Input Analog input 0 Analog input 1 AN1 Input Analog input 1 Analog input 2 AN2 Input Analog input 2 Analog input 3 AN3 Input Analog input 3 21 3 Register Descriptions The A D converter has the following registers For more information on addresses of registers and regist...

Page 576: ...to H 0000 Table 21 2 Analog Input Channels and A D Data Registers Analog Input Channel A D Data Register that Store Results of A D Conversion AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD 21 3 2 A D Control Status Registers ADCSR ADCSR is a 16 bit readable writable register that selects the mode and controls the A D converter Bit Bit Name Initial Value R W Description 15 ADF 0 R W A D End Flag Indicates...

Page 577: ...ST is automatically cleared to 0 when conversion ends on selected channels Multi mode A D conversion starts when conversion is completed cycling through the selected channels ADST is automatically cleared Scan mode A D conversion starts and continues A D conversion is continuously performed until ADST is cleared to 0 by software by a reset or by a transition to standby mode 12 DMASL 0 R W DMAC Sel...

Page 578: ...mum conversion time is not satisfied lack of accuracy or abnormal operation may occur 5 4 MULTI1 MULTI0 0 0 R W R W Mode Select Selects single mode multi mode or scan mode 00 Single mode 01 Setting prohibited 10 Multi mode 11 Scan mode 3 2 0 0 R R Reserved These bits are always read as 0 The write value should always be 0 1 0 CH1 CH0 0 0 R W R W Channel Select These bits and the MULTI bit select t...

Page 579: ... completed the ADST bit is cleared to 0 and the A D converter becomes idle When the ADST bit is cleared to 0 during A D conversion the conversion is halted and the A D converter becomes idle To clear the ADF flag to 0 first read ADF then write 0 to ADF 21 4 2 Multi Mode Multi mode should be selected when performing A D conversions on one or more channels 1 When the ADST bit is set to 1 by software...

Page 580: ...the ADST bit is set to 1 steps 2 and 3 above are repeated When the ADST bit is cleared to 0 the conversion is halted and the A D converter becomes idle To clear the ADF flag to 0 first read ADF then write 0 to ADF 21 4 4 Input Sampling and A D Conversion Time The A D converter has a built in sample and hold circuit The A D converter samples the analog input at an A D conversion start delay time tD...

Page 581: ...d A D conversion ended Figure 21 2 A D Conversion Timing Table 21 3 A D Conversion Time Single Mode CKS1 1 CKS0 0 CKS1 0 CKS0 1 CKS1 0 CKS0 0 Symbol Min Typ Max Min Typ Max Min Typ Max A D conversion start delay tD 18 21 10 13 6 9 Input sampling time tSPL 129 65 33 A D conversion time tCONV 535 545 275 285 141 151 Note Values in the table are numbers of states for Pφ Table 21 4 A D Conversion Time...

Page 582: ... bits of the A D converter have been simplified to 3 bits Resolution Digital output code number of the A D converter Quantization error Intrinsic error of the A D converter and is expressed as 1 2 LSB figure 21 3 Offset error Deviation between analog input voltage and ideal A D conversion characteristics when the digital output value changes from the minimum zero voltage 0000000000 H 00 000 in fig...

Page 583: ...ation error Ideal A D conversion characteristic Digital output Figure 21 3 Definitions of A D Conversion Accuracy Nonlinearity error Ideal A D conversion characteristic Actual A D conversion characteristic Full scale error Digital output Analog input voltage Offset error FS Figure 21 4 Definitions of A D Conversion Accuracy ...

Page 584: ...a low pass filter figure 21 5 When converting high speed analog signals or converting in scan mode insert a low impedance buffer 21 7 2 Influence to Absolute Accuracy By adding capacitance absolute accuracy may be degraded if noise is on GND because there is coupling with GND Therefore connect electrically stable GND such as AVcc to prevent absolute accuracy from being degraded A filter circuit mu...

Page 585: ...a protective circuit between AVcc and AVss as shown in figure 21 6 to prevent damage of analog input pins AN0 to AN3 due to abnormal voltage such as excessive serge Connect a bypass capacitor that is connected to AVcc and a capacitor for a filter that is connected to AN0 to AN3 to AVss When a capacitor for a filter is connected input currents of AN0 to AN3 are averaged may causing errors If A D co...

Page 586: ...le 21 6 Analog Input Pin Ratings Item Min Max Unit Analog input capacitance 20 pF Allowable signal source impedance 5 kΩ 20 pF AN0to AN3 3 kΩ To A D converter Note Values are for reference Figure 21 7 Analog Input Pin Equivalent Circuit ...

Page 587: ...tch with break conditions but not in the same bus cycle Address Compares 40 bits configured of the ASID and addresses 32 bits the ASID can be selected either all bit comparison or all bit mask Comparison bits for the address are maskable in 1 bit units user can mask addresses at lower 12 bits 4 k page lower 10 bits 1 k page or any size of page etc One of the two address buses L bus address LAB and...

Page 588: ... Break bus cycle register A BARA Break address register A BAMRA Break address mask register A BASRA Break ASID register A BBRB Break bus cycle register B BARB Break address register B BAMRB Break address mask register B BASRB Break ASID register B BDRB Break data register B BDMRB Break data mask register B BETR Break execution times register BRSR Branch source register BRDR Branch destination regi...

Page 589: ...s cycle register B BBRB Break data register B BDRB Break data mask register B BDMRB Break control register BRCR Execution times break register BETR Branch source register BRSR Branch destination register BRDR Break ASID register A BASRA Break ASID register B BASRB 22 2 1 Break Address Register A BARA BARA is a 32 bit readable writable register BARA specifies the address used as a break condition i...

Page 590: ...the break condition Note n 31 to 0 22 2 3 Break Bus Cycle Register A BBRA BBRA is a 16 bit readable writable register which specifies 1 L bus cycle or I bus cycle 2 instruction fetch or data access 3 read or write and 4 operand size in the break conditions of channel A Bit Bit Name Initial Value R W Description 15 to 8 0 R Reserved These bits are always read as 0 The write value should always be 0...

Page 591: ...n comparison is not performed 01 The break condition is the read cycle 10 The break condition is the write cycle 11 The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R W R W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition 00 The break condition does not include operand size 01 The break condition is byte access 10 The break cond...

Page 592: ... break condition 1 Break address BABn of channel B is masked and is not included in the break condition Note n 31 to 0 22 2 6 Break Data Register B BDRB BDRB is a 32 bit readable writable register Bit Bit Name Initial Value R W Description 31 to 0 BDB31 to BDB0 0 R W Break Data Bit B Stores data which specifies a break condition in channel B BDRB specifies the break data on LDB or IDB Notes 1 Spec...

Page 593: ... is not included in the break condition Note n 31 to 0 Notes 1 Specify an operand size when including the value of the data bus in the break condition 2 When the byte size is selected as a break condition the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB 22 2 8 Break Bus Cycle Register B BBRB BBRB is a 16 bit readable writable register which specifie...

Page 594: ...erformed 01 The break condition is the instruction fetch cycle 10 The break condition is the data access cycle 11 The break condition is the instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R W R W Read Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition 00 Condition comparison is not performed 01 The break condition is the read cycle...

Page 595: ...s Bit Bit Name Initial Value R W Description 31 to 22 0 R Reserved These bits are always read as 0 The write value should always be 0 21 BASMA 0 R W Break ASID Mask A Specifies whether bits in channel A break ASID7 to ASID0 BASA7 to BASA0 which are set in BASRA are masked or not 0 All BASRA bits are included in the break conditions and the ASID is checked 1 All BASRA bits are not included in the b...

Page 596: ... Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied this flag is set to 1 In order to clear this flag write 0 into this bit 0 The I bus cycle condition for channel A does not match 1 The I bus cycle condition for channel A matches 12 SCMFDB 0 R W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set f...

Page 597: ...struction execution 5 4 0 R Reserved These bits are always read as 0 The write value should always be 0 3 SEQ 0 R W Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions 0 Channels A and B are compared under independent conditions 1 Channels A and B are compared under sequential conditions channel A then channel B 2 1 0 R Reserved These bits a...

Page 598: ...nd any of the instructions below perform breaks BETR is not decremented when the first break occurs The decremented values are listed below Instruction Value Decremented Instruction Value Decremented RTE 4 LDC L Rm SR 6 DMULS L Rm Rn 2 LDC L Rm GBR 4 DMULU L Rm Rn 2 LDC L Rm VBR 4 MAC L Rm Rn 2 LDC L Rm SSR 4 MAC W Rm Rn 2 LDC L Rm SPC 4 MUL L Rm Rn 3 LDC L Rm R0_BANK 4 AND B imm R0 GBR 3 LDC L Rm...

Page 599: ...alized by a power on reset The eight BRSR registers have a queue structure and a stored register is shifted at every branch Bit Bit Name Initial Value R W Description 31 SVF 0 R BRSR Valid Flag Indicates whether the branch source address is stored When a branch source address is fetched this flag is set to 1 This flag is cleared to 0 by reading from BRSR 0 The value of BRSR register is invalid 1 T...

Page 600: ...cription 31 DVF 0 R BRDR Valid Flag Indicates whether a branch destination address is stored When a branch destination address is fetched this flag is set to 1 This flag is cleared to 0 by reading BRDR 0 The value of BRDR register is invalid 1 The value of BRDR register is valid 30 to 28 0 R Reserved These bits are always read as 0 27 to 0 BDA27 to BDA0 Undefined R Branch Destination Address Store...

Page 601: ...le registers BBRA and BBRB Three groups of BBRA and BBRB L bus cycle I bus cycle select instruction fetch data access select and read write select are each set No user break will be generated if even one of these groups is set with 00 The respective conditions are set in the bits of the break control register BRCR Make sure to set all registers related to breaks before setting BBRA BBRB 2 When the...

Page 602: ...ess to be cached and a cache miss occurs its bus cycle is issued as a cache fill cycle on the I bus In this case it is issued in longwords and its address is rounded to match longword boundaries However note that cache fill is not performed for a write miss in write through mode In this case the bus cycle is issued with the data size specified on the L bus and its address is not rounded In write b...

Page 603: ... of break is set for the delay slot of a delayed branch instruction the break is generated prior to execution of the delayed branch instruction Note If a branch does not occur at a delayed conditional branch instruction the subsequent instruction is not recognized as a delay slot 3 When the condition is specified to be occurred after execution the instruction set with the break condition is execut...

Page 604: ...e in which the break condition is satisfied is as follows where other conditions are met Longword access at H 00001000 Word access at H 00001002 Byte access at H 00001003 3 When the data value is included in the break conditions on channel B When the data value is included in the break conditions either longword word or byte is specified as the operand size of the break bus cycle register B BBRB W...

Page 605: ...yet occurred in a sequential break specification clear the SEQ bit in BRCR to 0 2 In sequential break specification the L or I bus can be selected and the execution times break condition can be also specified For example when the execution times break condition is specified the break condition is satisfied when a channel B condition matches with BETR H 0001 after a channel A condition has matched ...

Page 606: ...in the SPC 3 When data access address only is specified as a break condition The address of the instruction immediately after the instruction that matched the break condition is saved in the SPC The instruction that matches the condition is executed and the break occurs before the next instruction is executed However when a delay slot instruction matches the condition the branch destination addres...

Page 607: ...uction is saved in BRSR and the address of the branch destination instruction is saved in BRDR If a branch occurs due to an interrupt or exception the value saved in SPC due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR 3 BRSR and BRDR have eight pairs of queue structures The top of queues is read first when the address stored in ...

Page 608: ...luded in the condition The ASID check is not included A user break occurs after an instruction of address H 00000404 is executed or before instructions of addresses H 00008010 to H 00008016 are executed 2 Register specifications BARA H 00037226 BAMRA H 00000000 BBRA H 0056 BARB H 0003722E BAMRB H 00000000 BBRB H 0056 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000008 BASRA H 80 BASRB H 70 Specified ...

Page 609: ...n channel A no user break occurs since instruction fetch is not a write cycle On channel B no user break occurs since instruction fetch is performed for an even address 4 Register specifications BARA H 00037226 BAMRA H 00000000 BBRA H 005A BARB H 0003722E BAMRB H 00000000 BBRB H 0056 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000008 BASRA H 80 BASRB H 70 Specified conditions Channel A channel B seq...

Page 610: ...ed On channel B a user break occurs after the instruction of address H 00001000 are executed four times and before the fifth time 6 Register specifications BARA H 00008404 BAMRA H 00000FFF BBRA H 0054 BARB H 00008010 BAMRB H 00000006 BBRB H 0054 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000400 BASRA H 80 BASRB H 70 Specified conditions Channel A channel B independent mode Channel A Address H 00008...

Page 611: ...ddress H 00123456 On channel B a user break occurs when word H A512 is written in ASID H 70 and addresses H 000ABC00 to H 000ABCFE Break Condition Specified for an I Bus Data Access Cycle Register specifications BARA H 00314156 BAMRA H 00000000 BBRA H 0094 BARB H 00055555 BAMRB H 00000000 BBRB H 00A9 BDRB H 00007878 BDMRB H 00000F0F BRCR H 00000080 BASRA H 80 BASRB H 70 Specified conditions Channe...

Page 612: ...break occurs simultaneously with a re execution type exception including pre execution break that has higher priority the re execution type exception is accepted and the condition match flag is not set see the exception in the following note The break will occur and the condition match flag will be set only after the exception source of the re execution type exception has been cleared by the excep...

Page 613: ...User Debugging Interface is a serial I O interface which supports with JTAG Joint Test Action Group IEEE Standard 1149 1 and IEEE Standard Test Access Port and Boundary Scan Architecture specifications The UDI in this LSI supports a boundary scan mode and is also used for emulator connection When using an emulator UDI functions should not be used Refer to the emulator manual for the method of conn...

Page 614: ...RESETP pin the TRST pin should be driven low at the power on reset state and driven high after the power on reset state is released This is different from the JTAG standard See section 23 4 2 Reset Configuration for more information TDI Input Serial Data Input Pin Data transfer to the UDI is executed by changing this signal in synchronization with TCK TDO Output Serial Data Output Pin Data read fr...

Page 615: ... SDIR Boundary scan register SDBSR ID register SDID 23 3 1 Bypass Register SDBPR SDBPR is a 1 bit register that cannot be accessed by the CPU When SDIR is set to the bypass mode SDBPR is connected between UDI pins TDI and TDO The initial value is undefined but SDBPR is initialized when the TAP enters the Capture DR state 23 3 2 Instruction Register SDIR SDIR is a 16 bit read only register The regi...

Page 616: ...tion 0 0 0 0 JTAG EXTEST 0 0 1 0 JTAG CLAMP 0 0 1 1 JTAG HIGHZ 0 1 0 0 JTAG SAMPLE PRELOAD 0 1 1 0 UDI reset negate 0 1 1 1 UDI reset assert 1 0 1 UDI interrupt 1 1 1 0 JTAG IDCODE Initial value 1 1 1 1 JTAG BYPASS Other than the above Reserved 23 3 3 Boundary Scan Register SDBSR SDBSR is a 385 bit shift register located on the PAD for controlling the input output pins of this LSI The initial valu...

Page 617: ... OUT 375 D24 PTB0 PINT8 IN 343 D25 PTB1 PINT9 OUT 374 D23 PTA7 PINT7 IN 342 D24 PTB0 PINT8 OUT 373 D22 PTA6 PINT6 IN 341 D23 PTA7 PINT7 OUT 372 D21 PTA5 PINT5 IN 340 D22 PTA6 PINT6 OUT 371 D20 PTA4 PINT4 IN 339 D21 PTA5 PINT5 OUT 370 D19 PTA3 PINT3 IN 338 D20 PTA4 PINT4 OUT 369 D18 PTA2 PINT2 IN 337 D19 PTA3 PINT3 OUT 368 D17 PTA1 PINT1 IN 336 D18 PTA2 PINT2 OUT 367 D16 PTA0 PINT0 IN 335 D17 PTA1 ...

Page 618: ... Control 276 BS PTC0 IN 308 D23 PTA7 PINT7 Control 275 WE2 DQMUL PTC1 IN 307 D22 PTA6 PINT6 Control 274 WE3 DQMUU AH PTC2 IN 306 D21 PTA5 PINT5 Control 273 CS2 PTC3 IN 305 D20 PTA4 PINT4 Control 272 CS3 PTC4 IN 304 D19 PTA3 PINT3 Control 271 CS4 PTC5 IN 303 D18 PTA2 PINT2 Control 270 CS5A PTC6 IN 302 D17 PTA1 PINT1 Control 269 CS5B PTD6 IN 301 D16 PTA0 PINT0 Control 268 CS6A PTC7 IN 300 D15 Contro...

Page 619: ...22 PTK4 OUT 208 A11 Control 240 A23 PTK5 OUT 207 A12 Control 239 A24 PTK6 OUT 206 A13 Control 238 A25 PTK7 OUT 205 A14 Control 237 BS PTC0 OUT 204 A15 Control 236 RD OUT 203 A16 Control 235 WE0 DQMLL OUT 202 A17 Control 234 WE1 DQMLU OUT 201 A18 Control 233 WE2 DQMUL PTC1 OUT 200 A19 PTK1 Control 232 WE3 DQMUU AH PTC2 OUT 199 A20 PTK2 Control 231 RD WR OUT 198 A21 PTK3 Control 230 CS0 OUT 197 A22 ...

Page 620: ...PTD2 Control 143 CASU PTD3 OUT 175 CASU PTD3 IN 142 CKE PTD4 OUT 174 CKE PTD4 IN 141 PTD5 NF OUT 173 PTD5 NF IN 140 BACK PTG5 OUT 172 BACK PTG5 IN 139 BREQ PTG6 OUT 171 BREQ PTG6 IN 138 WAIT PTG7 OUT 170 WAIT PTG7 IN 137 DACK0 PTE0 OUT 169 DACK0 PTE0 IN 136 DACK1 PTE1 OUT 168 DACK1 PTE1 IN 135 TEND0 PTE3 OUT 167 TEND0 PTE3 IN 134 AUDSYNC PTF4 OUT 166 AUDSYNC PTF4 IN 133 AUDATA0 PTF0 TO0 OUT 165 AU...

Page 621: ...rol 77 TCLK PTE6 IN 109 DACK0 PTE0 Control 76 PTE7 IN 108 DACK1 PTE1 Control 75 SCK0 SCPT1 IN 107 TEND0 PTE3 Control 74 SCK2 SCPT3 IN 106 AUDSYNC PTF4 Control 73 RTS2 SCPT4 IN 105 AUDATA0 PTF0 TO0 Control 72 RXD0 SCPT0 IrRX IN 104 AUDATA1 PTF1 TO1 Control 71 RXD2 SCPT2 IN 103 AUDATA2 PTF2 TO2 Control 70 CTS2 SCPT5 IN 102 AUDATA3 PTF3 TO3 Control 69 IRQ0 IRL0 PTH0 IN 101 NF PTJ0 Control 68 IRQ1 IRL...

Page 622: ...Control 44 PTN7 OUT 14 TXD0 SCPT0 IrTX Control 43 TCLK PTE6 OUT 13 SCK0 SCPT1 Control 42 PTE7 OUT 12 TxD2 SCPT2 Control 41 TXD0 SCPT0 IrTX OUT 11 SCK2 SCPT3 Control 40 SCK0 SCPT1 OUT 10 RTS2 SCPT4 Control 39 TXD2 SCPT2 OUT 9 CTS2 SCPT5 Control 38 SCK2 SCPT3 OUT 8 IRQ0 IRL0 PTH0 Control 37 RTS2 SCPT4 OUT 7 IRQ1 IRL1 PTH1 Control 36 CTS2 SCPT5 OUT 6 IRQ2 IRL2 PTH2 Control 35 IRQ0 IRL0 PTH0 OUT 5 IRQ...

Page 623: ...from the UDI pin This register can be read from the TDO when the TAP state is Shift DR Writing is disabled Bit Bit Name Initial Value R W Description 31 to 0 DID31 to DID0 Refer to description R Device ID31 to 0 Device ID register that is stipulated by JTAG H 001A200F initial value for this LSI Upper four bits may be changed by the chip version SDIDH corresponds to bits 31 to 16 SDIDL corresponds ...

Page 624: ... IR Exit1 IR Pause IR Exit2 IR Update IR Select IR scan 0 0 1 0 0 1 1 0 1 1 1 0 0 Figure 23 2 TAP Controller State Transitions Note The transition condition is the TMS value at the rising edge of TCK The TDI value is sampled at the rising edge of TCK shifting occurs at the falling edge of TCK For details on change timing of the TDO value see section 23 4 3 TDO Output Timing The TDO is at high impe...

Page 625: ... is driven high UDI operation is enabled but the CPU does not start up The reset hold state is canceled by the following Another RESETP assert power on reset TRST reassert 3 ASE mode is classified into two modes ASE break mode to execute the firm program of an emulator and ASE user mode to execute the user program 4 Make sure the TRST pin is low when the power is turned on 23 4 3 TDO Output Timing...

Page 626: ... UDI reset negate command is the same as time for keeping the RESETP pin low to apply a power on reset UDI reset assert UDI reset negate SDIR Chip internal reset CPU state Branch to H A0000000 Figure 23 4 UDI Reset 23 4 5 UDI Interrupt The UDI interrupt function generates an interrupt by setting a command from the UDI in the SDIR An UDI interrupt is a general exception interrupt operation resultin...

Page 627: ...his LSI s input pin signals are transmitted directly to the internal circuitry and internal circuit values are directly output externally from the output pins This LSI s system circuits are not affected by execution of this instruction The upper four bits of the instruction code are 0100 In a SAMPLE operation a snapshot of a value to be transferred from an input pin to the internal circuitry or a ...

Page 628: ...tipulated by JTAG When the UDI is initialized TRST is asserted or TAP is in the Test Logic Reset state the IDCODE mode is entered 5 CLAMP HIGHZ A command can be set in SDIR by the UDI pins to place the UDI pins in the CLAMP or HIGHZ mode stipulated by JTAG 23 5 2 Points for Attention 1 Boundary scan mode does not cover clock related signals EXTAL EXTAL2 XTAL XTAL2 EXTAL_USB XTAL_USB and CKIO 2 Bou...

Page 629: ...t chip operations is once set 2 Because chip operations are suspended in standby mode UDI commands are not accepted To keep the TAP state constant before and after standby mode TCK must be high during standby mode transition 3 The UDI is used for emulator connection Therefore UDI functions cannot be used when using an emulator 23 7 Advanced User Debugger AUD The AUD is a function only for an emula...

Page 630: ...Rev 2 00 09 03 page 584 of 690 ...

Page 631: ...e same order as the Register Addresses by functional module in order of the corresponding section numbers Reserved bits are indicated by in the bit name No entry in the bit name column indicates that the whole register is allocated as a counter or for holding data When registers consist of 16 or 32 bits bits are described from the MSB side The order in which bytes are described is on the presumpti...

Page 632: ...rol register 2 CCR2 32 H A400 00B0 32 Cache control register 3 CCR3 32 H A400 00B4 32 Interrupt event register 2 INTEVT2 32 H A400 0000 32 TRAPA exception register TRA 32 H FFFF FFD0 Exception handling 32 Exception event register EXPEVT 32 H FFFF FFD4 32 Interrupt event register INTEVT 32 H FFFF FFD8 32 TLB exception address register TEA 32 H FFFF FFFC 32 Interrupt priority level setting register ...

Page 633: ...14 32 Bus control register for CS5B space CS5BBCR 32 H A4FD 0018 32 Bus control register for CS6A space CS6ABCR 32 H A4FD 001C 32 Bus control register for CS6B space CS6BBCR 32 H A4FD 0020 32 Wait control register for CS0 space CS0WCR 32 H A4FD 0024 32 Wait control register for CS2 space CS2 WCR 32 H A4FD 0028 32 Wait control register for CS3 space CS3 WCR 32 H A4FD 002C 32 Wait control register f...

Page 634: ...nsfer count register_2 DMATCR_2 32 H A400 0048 16 32 DMA channel control register_2 CHCR_2 32 H A400 004C 8 16 32 DMA source address register_3 SAR_3 32 H A400 0050 16 32 DMA destination address register_3 DAR_3 32 H A400 0054 16 32 DMA transfer count register_3 DMATCR_3 32 H A400 0058 16 32 DMA channel control register_3 CHCR_3 32 H A400 005C 8 16 32 DMA operation register DMAOR 16 H A400 0060 8 ...

Page 635: ...ompare match timer control status register CMCSR 16 H A400 0074 16 Compare match timer counter CMCNT 16 H A400 0078 16 Compare match timer constant register CMCOR 16 H A400 007C 16 Timer start register TSTR 16 H A449 0000 TPU 16 Timer control register_0 TCR_0 16 H A449 0010 16 Timer mode register_0 TMDR_0 16 H A449 0014 16 Timer I O control register_0 TIOR_0 16 H A449 0018 16 Timer interrupt enabl...

Page 636: ...gister_2 TIER_2 16 H A449 009C 16 Timer status register_2 TSR_2 16 H A449 00A0 16 Timer counter_2 TCNT_2 16 H A449 00A4 16 Timer general register A_2 TGRA_2 16 H A449 00A8 16 Timer general register B_2 TGRB_2 16 H A449 00AC 16 Timer general register C_2 TGRC_2 16 H A449 00B0 16 Timer general register D_2 TGRD_2 16 H A449 00B4 16 Timer control register_3 TCR_3 16 H A449 00D0 16 Timer mode register_...

Page 637: ...ate alarm register RDAYAR 8 H FFFF FED8 8 Month alarm register RMONAR 8 H FFFF FEDA 8 RTC control register 1 RCR1 8 H FFFF FEDC 8 RTC control register 2 RCR2 8 H FFFF FEDE 8 Year alarm register RYRAR 16 H A413 FEE0 16 RTC control register 3 RCR3 8 H A413 FEE4 8 Serial mode register_0 SCSMR_0 16 H A440 0000 SCIF_0 16 Bit rate register_0 SCBRR_0 8 H A440 0004 Channel 0 8 Serial control register_0 SC...

Page 638: ...0i 8B H A448 0000 USB 8 EP0o data register EPDR0o 8B H A448 0004 8 EP0s data register EPDR0s 8B H A448 0008 8 EP1 data register EPDR1 128B H A448 000C 8 32 EP2 data register EPDR2 128B H A448 0010 8 32 EP3 data register EPDR3 8B H A448 0014 8 Interrupt flag register 0 IFR0 8 H A448 0018 8 Interrupt flag register 1 IFR1 8 H A448 001C 8 Trigger register TRG 8 H A448 0020 8 FIFO clear register FCLR 8...

Page 639: ...R 16 H A400 0112 16 Port L control register PLCR 16 H A400 0114 16 Port SC control register SCPCR 16 H A400 0116 16 Port M control register PMCR 16 H A400 0118 16 Port N control register PNCR 16 H A400 011A 16 Port N control register 2 PNCR2 8 H A405 015A 8 Port A data register PADR 8 H A400 0120 Port 8 Port B data register PBDR 8 H A400 0122 8 Port C data register PCDR 8 H A400 0124 8 Port D data...

Page 640: ...ister B BARB 32 H FFFF FFA0 32 Break address mask register B BAMRB 32 H FFFF FFA4 32 Break bus cycle register B BBRB 16 H FFFF FFA8 16 Branch source register BRSR 32 H FFFF FFAC 32 Break address register A BARA 32 H FFFF FFB0 32 Break address mask register A BAMRA 32 H FFFF FFB4 32 Break bus cycle register A BBRA 16 H FFFF FFB8 16 Branch destination register BRDR 32 H FFFF FFBC 32 Break ASID regis...

Page 641: ...ctively Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module MMUCR MMU SV RC1 RC0 TF IX AT PTEH VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN VPN ASID7 ASID6 ASID5 ASID4 ASID3 ASID2 ASID1 ASID0 PTEL PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN PPN P...

Page 642: ...t 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module CCR1 Cache CF CB WT CE CCR2 LE W3LOADW3LOCK W2LOADW2LOCK CCR3 CSIZE7 CSIZE6 CSIZE5 CSIZE4 CSIZE3 CSIZE2 CSIZE1 CSIZE0 INTEVT2 Exception handing TRA imm imm imm imm imm imm imm imm EXPEVT INTEVT ...

Page 643: ...IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPRF IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPRG IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPRH IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 ICR0 NMIL NMIE ICR1 MAI IRQLVL BLMSK IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ...

Page 644: ...IWRWS0 IWRRD1 IWRRD0 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS3BCR IWW1 IWW0 IWRWD1 IWRWD0 IWRWS1 IWRWS0 IWRRD1 IWRRD0 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS4BCR IWW1 IWW0 IWRWD1 IWRWD0 IWRWS1 IWRWS0 IWRRD1 IWRRD0 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS5ABCR IWW1 IWW0 IWRWD1 IWRWD0 IWRWS1 IWRWS0 IWRRD1 IWRRD0 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS5BBCR IWW1 IWW0 IWRWD1 IWRWD0 I...

Page 645: ...IWRWS1 IWRWS0 IWRRD1 IWRRD0 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 SW1 SW0 WR3 WR2 WR1 CS0WCR except burst ROM WR0 WM HW1 HW0 BW1 BW0 W3 W2 W1 CS0WCR burst ROM W0 WM WR3 WR2 WR1 CS2 WCR except SDRAM WR0 WM A2CL1 CS2 WCR SDRAM A2CL0 WR3 WR2 WR1 CS3 WCR except SDRAM WR0 WM TRP1 TRP0 TRCD1 TRCD0 A3CL1 CS3 WCR SDRAM A3CL0 TRWL1 TRWL0 TRC1 TRC0 WW2 WW1 WW0 SW1 SW0 WR3 WR2 WR1 CS4 WCR except burst RO...

Page 646: ...W1 SW0 W3 W2 W1 CS4 WCR burst ROM W0 WM HW1 HW0 CS5A WCR WW2 WW1 WW0 SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 CS5B WCR MPXW WW2 WW1 WW0 SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 CS6A WCR SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 CS6B WCR SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 SDCR A2ROW1 A2ROW0 A2COL1 A2COL0 SLOW RFSH RMODE BACTV A3ROW1 A3ROW0 A3COL1 A3COL0 RTCSR CMF CMIE CKS2 CKS1 CKS0 RRC2 RRC1 RRC0 RTCNT RTCOR ...

Page 647: ...1 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module SDMR2 BSC SDMR3 SAR_0 DMAC DAR_0 DMATCR_0 CHCR_0 DO TL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DL DS TB TS1 TS0 IE TE DE SAR_1 DAR_1 DMATCR_1 ...

Page 648: ...14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module CHCR_1 DMAC DO AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DL DS TB TS1 TS0 IE TE DE SAR_2 DAR_2 DMATCR_2 CHCR_2 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TB TS1 TS0 IE TE DE SAR_3 DAR_3 DMATCR_3 ...

Page 649: ... C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 DMARS1 C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 UCLKCR USSCS1 USSCS0 USBEN CPG FRQCR CKOEN STC1 STC0 IFC1 IFC0 PFC1 PFC0 WTCNT WTCSR TME WT IT RSTS WOVF IOVF CKS2 CKS1 CKS0 WDT STBCR STBY STBXTL MSTP2 MSTP1 STBCR2 MSTP10 MSTP9 MSTP8 MSTP6 MSTP5 STBCR3 MSTP37 MSTP35...

Page 650: ... 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module TCOR_1 TMU TCNT_1 TCR_1 UNF UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR_2 TCNT_2 TCR_2 ICPF UNF ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCPR_2 CMSTR CMT STR CMCSR CMF CMR CKS1 CKS0 CMCNT CMCOR ...

Page 651: ... CST1 CST0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 BFWT BFB BFA MD2 MD1 MD0 TIOR_0 IOA2 IOA1 IOA0 TIER_0 TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 BFWT BFB BFA MD2 MD1 MD0 TIOR_1 IOA2 IOA1 IOA0 TIER_1 TCIEV TGIED TGIEC TGIEB TGIEA TSR_1 TCFV TGFD TGFC TGFB TGFA ...

Page 652: ... 2 Bit 25 17 9 1 Bit 24 16 8 0 Module TCNT_1 TPU TGRA_1 TGRB_1 TGRC_1 TGRD_1 TCR_2 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 BFWT BFB BFA MD2 MD1 MD0 TIOR_2 IOA2 IOA1 IOA0 TIER_2 TCIEV TGIED TGIEC TGIEB TGIEA TSR_2 TCFV TGFD TGFC TGFB TGFA TCNT_2 TGRA_2 TGRB_2 TGRC_2 TGRD_2 TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ...

Page 653: ...5 17 9 1 Bit 24 16 8 0 Module TMDR_3 TPU BFWT BFB BFA MD2 MD1 MD0 TIOR_3 IOA2 IOA1 IOA0 TIER_3 TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 TCFV TGFD TGFC TGFB TGFA TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 R64CNT 1Hz 2Hz 4Hz 8Hz 16Hz 32Hz 64Hz RTC RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR ENB RMINAR ENB RHRAR ENB RWKAR ENB RDAYAR ENB RMONAR ENB ...

Page 654: ...FER1 FER0 SCSSR_0 ORER TSF ER TEND TDFE BRK FER PER RDF DR SCFCR_0 TSE TCRST RSTRG2 RSTRG1 RSTRG0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP SCFDR_0 T6 T5 T4 T3 T2 T1 T0 R6 R5 R4 R3 R2 R1 R0 SCFTDR_0 SCFTD7 SCFTD6 SCFTD5 SCFTD4 SCFTD3 SCFTD2 SCFTD1 SCFTD0 SCFRDR_0 SCFRD7 SCFRD6 SCFRD5 SCFRD4 SCFRD3 SCFRD2 SCFRD1 SCFRD0 SCSMR_2 SRC2 SRC1 SRC0 SCIF_2 C A CHR PE O E STOP CKS1 CKS0 SCBRR_2 SCBRD7 SC...

Page 655: ...ETUPTS EP0oTS EP0iTR EP0iTS IFR1 VBUSMN EP3TR EP3TS VBUS TRG EP3PKTE EP1RDFN EP2PKTE EP0sRDFN EP0oRDFN EP0iPKTE FCLR EP3CLR EP1CLR EP2CLR EP0oCLR EP0iCLR EPSZ0o D7 D6 D5 D4 D3 D2 D1 D0 DASTS EP3DE EP2DE EP0iDE EPSTL EP3STL EP2STL EP1STL EP0STL IER0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR EP0iTS IER1 EP3TR EP3TS VBUS EPSZ1 D7 D6 D5 D4 D3 D2 D1 D0 DMAR EP2DMAE EP1DMAE ISR0 BRST EP1FULL EP2...

Page 656: ...D1 PJ7MD0 PJ6MD1 PJ6MD0 PJ5MD1 PJ5MD0 PJ4MD1 PJ4MD0 PJ3MD1 PJ3MD0 PJ2MD1 PJ2MD0 PJ1MD1 PJ1MD0 PJ0MD1 PJ0MD0 PKCR PK7MD1 PK7MD0 PK6MD1 PK6MD0 PK5MD1 PK5MD0 PK4MD1 PK4MD0 PK3MD1 PK3MD0 PK2MD1 PK2MD0 PK1MD1 PK1MD0 PK0MD1 PK0MD0 PLCR PL3MD1 PL3MD0 PL2MD1 PL2MD0 PL1MD1 PL1MD0 PL0MD1 PL0MD0 SCPCR SCP5MD1 SCP5MD0 SCP4MD1 SCP4MD0 SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 SCP1MD1 SCP1MD0 SCP0MD1 SCP0MD0 PMCR PM6MD1 ...

Page 657: ...DT PN5DT PN4DT PN3DT PN2DT PN1DT PN0DT ADDRA ADC ADDRB ADDRC ADDRD ADCSR ADF ADIE ADST DMASL CKS1 CKS0 MULTI1 MULTI0 CH1 CH0 BDRB BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 UBC BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 BDMRB BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 B...

Page 658: ...A24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 BARA BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 BAMRA BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22...

Page 659: ...12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 SDIR UDI DID31 DID30 DID29 DID28 DID27 DID26 DID25 DID24 SDID SDIDH DID23 DID22 DID21 DID20 DID19 DID18 DID17 DID16 DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 SDIDL DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 ...

Page 660: ...d Retained Retained INTC IPRB Initialized Initialized Retained Retained Retained IPRC Initialized Initialized Retained Retained Retained IPRD Initialized Initialized Retained Retained Retained IPRE Initialized Initialized Retained Retained Retained IPRF Initialized Initialized Retained Retained Retained IPRG Initialized Initialized Retained Retained Retained IPRH Initialized Initialized Retained R...

Page 661: ...ined SDCR Initialized Retained Retained Retained Retained RTCSR Initialized Retained Retained Retained Retained RTCNT Initialized Retained Retained Retained Retained RTCOR Initialized Retained Retained Retained Retained SDMR2 SDMR3 SAR_0 Undefined Undefined Retained Retained Retained DMAC DAR_0 Undefined Undefined Retained Retained Retained DMATCR_0 Undefined Undefined Retained Retained Retained C...

Page 662: ...Retained STBCR3 Initialized Retained Retained Retained Retained Power down modes TSTR Initialized Initialized Initialized Initialized Retained TMU TCOR_0 Initialized Initialized Retained Retained Retained TCNT_0 Initialized Initialized Retained Retained Retained TCR_0 Initialized Initialized Retained Retained Retained TCOR_1 Initialized Initialized Retained Retained Retained TCNT_1 Initialized Ini...

Page 663: ...d Retained Retained TIOR_1 Initialized Initialized Retained Retained Retained TIER_1 Initialized Initialized Retained Retained Retained TSR_1 Initialized Initialized Retained Retained Retained TCNT_1 Initialized Initialized Retained Retained Retained TGRA_1 Initialized Initialized Retained Retained Retained TGRB_1 Initialized Initialized Retained Retained Retained TGRC_1 Initialized Initialized Re...

Page 664: ...eration continued Operation continued Operation continued Retained Operation continued RHRCNT Operation continued Operation continued Operation continued Retained Operation continued RWKCNT Operation continued Operation continued Operation continued Retained Operation continued RDAYCNT Operation continued Operation continued Operation continued Retained Operation continued RMONCNT Operation contin...

Page 665: ...tialized Initialized Retained Retained Retained SCFER_2 Initialized Initialized Retained Retained Retained SCSSR_2 Initialized Initialized Retained Retained Retained SCFCR_2 Initialized Initialized Retained Retained Retained SCFDR_2 Initialized Initialized Retained Retained Retained SCFTDR_2 Undefined Undefined Retained Retained Retained SCFRDR_2 Undefined Undefined Retained Retained Retained SCSM...

Page 666: ... Retained Retained PECR2 Initialized Retained Retained Retained Retained PFCR Initialized Retained Retained Retained Retained PFCR2 Initialized Retained Retained Retained Retained PGCR Initialized Retained Retained Retained Retained PHCR Initialized Retained Retained Retained Retained PJCR Initialized Retained Retained Retained Retained PKCR Initialized Retained Retained Retained Retained PLCR Ini...

Page 667: ...tained UBC BDMRB Initialized Retained Retained Retained Retained BRCR Initialized Retained Retained Retained Retained BETR Initialized Retained Retained Retained Retained BARB Initialized Retained Retained Retained Retained BAMRB Initialized Retained Retained Retained Retained BBRB Initialized Retained Retained Retained Retained BRSR Initialized 3 Retained Retained Retained Retained BARA Initializ...

Page 668: ...20 at a manual reset 8 The NMIL bit 1 when the NMI input is high and the NMIL bit 0 when the NMI input is low 9 The ENDIAN bit indicates the MD5 pin input sampled at a power on reset 10 At a power on reset this register is initialized to H 09 At a manual reset bits other than the RTCEN and START bits are initialized ...

Page 669: ...age temperature Tstg 55 to 125 C Caution Operating the chip in excess of the absolute maximum rating may result in permanent damage Order of turning on 1 5 V power Vcc Vcc PLL1 Vcc PLL2 and 3 3 V power VccQ Vcc RTC AVcc Vcc USB 1 The 3 3 V power and the 1 5 V power should be turned on simultaneously or the 3 3 V power should be tuned on first When the 3 3 V is turned on first turn on the 1 5 V pow...

Page 670: ... min attain time Vcc 1 5 V power Vcc min voltage Vcc 2 level voltage Normal operation term States undefined term Operation stopped Clock oscillation started Oscillation settling time Cancel the power on reset and go to normal operation tunc GND tpwd Figure 25 1 Power On Off Sequence Recommended Power On Off Times Item Symbol Max Permitted Value Unit VccQ to Vcc power on time interval tpwu 1 ms Vcc...

Page 671: ...1 5 V Iφ 133 MHz ICC 105 150 VCC 1 5 V Iφ 100 MHz Normal operation ICCQ 20 40 mA VCCQ 3 3 V Bφ 33 MHz ICC 25 40 mA In sleep mode ICCQ 10 20 Bφ 33 MHz ICC 150 500 µA ICCQ 10 30 Ta 25 C RTC on VCCQ 3 3 V VCC 1 5 V ICC 150 500 µA Current consumption In standby mode ICCQ 10 30 Ta 25 C RTC off VCCQ 3 3 V VCC 1 5 V Input leak current All input pins Iin 1 0 µA Vin 0 5 to VCCQ 0 5 V Three state leak curre...

Page 672: ...nsceiver pins D D and PTM3 to PTM0 C 10 pF USB transceiver pins D D and PTM3 to PTM0 CAN 20 pF Analog power supply voltage AD AVCC 3 0 3 3 3 6 V Analog power supply voltage USB VCC USB 3 0 3 3 3 6 V Analog power supply current AD During A D conversion AICC 0 8 2 mA Idle 0 01 5 0 µA Note No external bus cycles except refresh cycles ...

Page 673: ...AL CKIO CA VIH VCCQ 0 9 VCCQ 0 3 EXTAL2 When this pin is not connected to the crystal resonator this pin should be connected to the VCCQ pin pulled up Port L 2 0 AVCC 0 3 Other input pins 2 0 VCCQ 0 3 V Input low voltage RESETP RESETM NMI IRQ5 to IRQ0 PINT15 to PINT0 RXD0 MD6 to MD0 ASEMD0 TRST EXTAL CKIO CA VIL 0 3 VCCQ 0 1 EXTAL2 When this pin is not connected to the crystal resonator this pin s...

Page 674: ... not used connect AVCC to VCCQ and AVSS to VSSQ 3 Current consumption values are for VIHmin VCCQ 0 5 V and VILmax 0 5 V with all output pins unloaded Table 25 2 DC Characteristics 2 b USB Related Pins Condition Ta 20 to 75 C Item Symbol Min Typ Max Unit Measurement Conditions Power supply voltage VCCQ 3 0 3 3 3 6 V Input high voltage VIH 2 0 VCCQ 0 3 V Input low voltage VIL 0 3 VCCQ 0 2 V Input hi...

Page 675: ... D pins 2 VCC USB must satisfy the condition VCCQ VCC USB Even when the USB is not used power must be supplied between VCC USB and VSS USB Table 25 3 Permitted Output Current Values Conditions VCCQ VCC RTC VCC USB 3 0 to 3 6 V VCC VCC PLL1 VCC PLL2 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Output low level permissi...

Page 676: ...pecified Table 25 4 Maximum Operating Frequencies Conditions VCCQ VCC RTC VCC USB 3 0 to 3 6 V VCC VCC PLL1 VCC PLL2 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Remarks 133 34 133 MHz product CPU cache Iφ f 20 100 MHz 100 MHz product External bus Bφ 20 66 67 Operating frequency Peripheral module Pφ 5 33 34 ...

Page 677: ...Hz 25 3 CKIO clock input cycle time tCKICYC 15 50 ns CKIO clock input low pulse width tCKIL 3 ns CKIO clock input high pulse width tCKIH 3 ns CKIO clock input rise time tCKIR 4 ns CKIO clock input fall time tCKIF 4 ns CKIO clock output frequency tOP 20 66 67 MHz 25 4 CKIO clock output cycle time tcyc 15 50 ns CKIO clock output low pulse width tCKOL 3 ns CKIO clock output high pulse width tCKOH 3 n...

Page 678: ... standby mode tIRLSTB 100 µs 25 10 tEXH tEXf tEXr tEXL tEXcyc VIH VIH VIH 1 2 VCCQ 1 2 VCCQ VIL VIL EXTAL input Note The clock input from the EXTAL pin Figure 25 2 EXTAL Clock Input Timing tCKIH tCKIF tCKIR tCKIL tCKICYC VIH 1 2 VCCQ 1 2 VCCQ VIH VIL VIH VIL CKIO input Figure 25 3 CKIO Clock Input Timing tCKOH tCKOf tCKOr tCKOL tcyc VOH 1 2 VCCQ 1 2 VCCQ VOH VOH VOL VOL CKIO output Figure 25 4 CKI...

Page 679: ...ling Time CKIO internal clock Stable oscillation Standby tOSC2 tRESPW tRESMW RESETP RESETM Note Oscillation settling time when built in oscillator is used Figure 25 6 Oscillation Settling Time at Standby Return Return by Reset CKIO internal clock Stable oscillation Standby tOSC3 NMI Note Oscillation settling time when built in oscillator is used Figure 25 7 Oscillation Settling Time at Standby Ret...

Page 680: ...on Settling Time at Standby Return Return by IRQ5 to IRQ0 PINT15 to PINT0 and IRL3 to IRL0 EXTAL input CKIO input Stable input clock Reset or NMI interrupt request Stable input clock Normal Normal Standby PLL output CKIO output Internal clock STATUS 0 STATUS 1 PLL synchronization Note PLL oscillation settling time when clock is input from EXTAL pin tPLL1 PLL synchronization Figure 25 9 PLL Synchro...

Page 681: ...ck is input from EXTAL pin or CKIO pin in oscillation continuous mode tPLL1 PLL synchronization Standby PLL synchronization tIRLSTB Figure 25 10 PLL Synchronization Settling Time by IRQ IRL PINT Interrupts EXTAL input 1 CKIO input CKIO output 2 PLL output Internal clock Multiplication ratio modified tPLL2 Notes 1 CKIO input in clock mode 7 2 PLL output except in clock mode 7 Figure 25 11 PLL Synch...

Page 682: ... 1 2 tcyc 13 ns 25 14 STATUS1 STATUS0 delay time tSTD 18 ns 25 15 Bus tri state delay time 1 tBOFF1 0 30 ns 25 14 Bus tri state delay time 2 tBOFF2 0 30 ns 25 15 Bus buffer on time 1 tBON1 0 30 ns Bus buffer on time 2 tBON2 0 30 ns Notes tcyc is the external bus clock cycle B clock cycle 1 RESETP RESETM NMI and IRQ5 to IRQ0 are asynchronous Changes are detected at the clock rise when the setup sho...

Page 683: ...Reset Input Timing CKIO NMI tNMIH tNMIS VIH VIL IRQ5 to IRQ0 tIRQH tIRQS VIH VIL Figure 25 13 Interrupt Signal Input Timing CKIO BREQ BACK A25 to A0 D31 to D0 RD RD WR RASU L CASU L CSn WEn BS CKE BREQH t BREQS t BACKD t BACKD t BREQH t BREQS t BON1 t BOFF1 t BOFF2 t BON2 t Figure 25 14 Bus Release Timing ...

Page 684: ... Address delay time 1 tAD1 1 12 ns 25 16 to 25 38 Address delay time 2 tAD2 1 2 tcyc 12 ns 25 21 Address setup time tAS 0 ns 25 16 to 25 19 Address hold time tAH 0 ns 25 16 to 25 19 BS delay time tBSD 10 ns 25 16 to 25 35 CS delay time 1 tCSD1 1 10 ns 25 16 to 25 38 Read write delay time 1 tRWD1 1 10 ns 25 16 to 25 38 Read strobe delay time tRSD 1 2 tcyc 10 ns 25 16 to 25 21 Read data setup time 1...

Page 685: ... 26 to 25 29 25 33 to 25 35 Write data hold time 4 tWDH4 0 ns 25 16 to 25 19 WAIT setup time tWTS 1 2 tcyc 6 ns 25 17 to 25 21 WAIT hold time tWTH 1 2 tcyc 2 ns 25 17 to 25 21 RAS delay time 1 tRASD1 1 10 ns 25 22 to 25 38 CAS delay time 1 tCASD1 1 10 ns 25 22 to 25 38 DQM delay time 1 tDQMD1 1 10 ns 25 22 to 25 35 CKE delay time 1 tCKED1 1 10 ns 25 37 AH delay time tAHD 1 2 tcyc 1 2 tcyc 10 ns 25...

Page 686: ...SD tAH tAH tRDH1 tRDS1 tWED tWED tBSD tBSD tDACD tDACD tWDH1 tWDH4 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn 2 BS DACKn 1 D31 to D0 Read Write Notes 1 DACKn is a waveform when active low is specified 2 Output timing is the same when reading byte selection SRAM Figure 25 16 Basic Bus Cycle No Wait ...

Page 687: ...WED tAH tAH tBSD tBSD tWTH tWTS tDACD tDACD tWDH1 tWDH4 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn 2 BS WAIT DACKn 1 D31 to D0 Notes 1 DACKn is a waveform when active low is specified 2 Output timing is the same when reading byte selection SRAM Read Write Figure 25 17 Basic Bus Cycle One Software Wait ...

Page 688: ...ED tWED tBSD tBSD tWTH tWTH tWTS tWTS tDACD tDACD tWDH1 tWDH4 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn 2 BS WAIT DACKn 1 D31 to D0 Read Write Notes 1 DACKn is a waveform when active low is specified 2 Output timing is the same when reading byte selection SRAM Figure 25 18 Basic Bus Cycle One External Wait ...

Page 689: ...ACD tBSD tBSD tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tAS tAD1 tAD1 Tw T2 Tnop T1 Tw T2 Tnop DACKn 1 A25 to A0 D15 to D0 CSn RD WR RD WAIT D15 to D0 WEn 2 BS CKIO tWTH tWTS tWTH tWTS Read Write Notes 1 DACKn is a waveform when active low is specified 2 Output timing is the same when reading byte selection SRAM Figure 25 19 Basic Bus Cycle One Software Wait External Wait Enabled WM Bit 0 No Idle Cycle ...

Page 690: ... tBSD tBSD tWTH tWTS tAHD tAHD tWTH tWTS tDACD tDACD Address tWDH1 tMAH tMAD CKIO A25 to A0 CSn RD WR RD AH D15 to D0 WE0 1 BS WAIT DACKn D15 to D0 Address tMAH tMAD Read Write Note DACKn is a waveform when active low is specified Figure 25 20 Address Data Multiplex I O Bus Cycle Three Address Cycles One Software Wait One External Wait ...

Page 691: ...D tWTH tWTS tWTH tWTS tDACD tDACD tRDS3 tRDH3 tRDS3 tRDH3 CKIO A25 to A0 CSn RD WR RD WEn BS WAIT DACKn D31 to D0 Notes 1 tRDH3 is specified by earlier one of change of A25 to A0 or the RD rising edge 2 DACKn is a waveform when active low is specified Figure 25 21 Burst ROM Read Cycle One Access Wait One External Wait One Burst Wait Two Bursts ...

Page 692: ...A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address Read A command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 22 Synchronous DRAM Single Read Bus Cycle Auto Precharge CAS Latency 2 TRCD 1 Cycle TRP 1 Cycle ...

Page 693: ...1 to D0 tRASD1 tRASD1 RASU L Row address Read A command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 23 Synchronous DRAM Single Read Bus Cycle Auto Precharge CAS Latency 2 TRCD 2 Cycle TRP 2 Cycle ...

Page 694: ...SD1 RASU L Row address Read A command Read command Column address 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 tRDH2 tRDS2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 24 Synchronous DRAM Burst Read Bus Cycle Single Read 4 Auto Precharge CAS Latency 2 TRCD 1 Cycle TRP 2 Cycl...

Page 695: ...RASD1 RASU L Row address Read A command Read command Column address 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 tRDH2 tRDS2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 25 Synchronous DRAM Burst Read Bus Cycle Single Read 4 Auto Precharge CAS Latency 2 TRCD 2 Cycle TRP 1 Cy...

Page 696: ... D0 tRASD1 tRASD1 RASU L Row address Write A command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDD2 tWDH2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 26 Synchronous DRAM Single Write Bus Cycle Auto Precharge TRWL 2 Cycle ...

Page 697: ...tRASD1 RASU L Row address Write A command Column address CASU L tBSD tBSD High BS CKE tDQMD1 tRWD1 tRWD1 tRASD1 tRASD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 27 Synchronous DRAM Single Write Bus Cycle Auto Precharge TRCD 3 Cycle TRWL 2 Cycle ...

Page 698: ...1 RASU L Row address Write A command Write command Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDH2 tWDD2 tWDD2 tRASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 28 Synchronous DRAM Burst Write Bus Cycle Single Write 4 Auto Precharge TRCD 1 Cycle TRWL 2 Cycle ...

Page 699: ...SD1 RASU L Row address Write A command Write command Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDH2 tWDD2 tWDD2 tRASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 29 Synchronous DRAM Burst Write Bus Cycle Single Write 4 Auto Precharge TRCD 2 Cycle TRWL 2 Cycle ...

Page 700: ...D1 RASU L Row address Read command Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 tRDH2 tRDS2 tAD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 30 Synchronous DRAM Burst Read Bus Cycle Single Read 4 Bank Active Mode ACTV READ Commands CAS Latency 2 TRCD 1 Cycle ...

Page 701: ...nd Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 tRDH2 tRDS2 tAD1 tDQMD1 tDACD tBSD tCASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 31 Synchronous DRAM Burst Read Bus Cycle Single Read 4 Bank Active Mode READ Command Same Row Address CAS Latency 2 TRCD 1 Cycle...

Page 702: ...d command Column address Row address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 tRDH2 tRDS2 tCSD1 tRASD1 tCASD1 tDQMD1 tBSD tDACD Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 32 Synchronous DRAM Burst Read Bus Cycle Single Read 4 Bank Active Mode PRE ACTV READ Commands Differ...

Page 703: ... Row address Write command Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDH2 tWDD2 tWDD2 tRASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 33 Synchronous DRAM Burst Write Bus Cycle Single Write 4 Bank Active Mode ACTV WRITE Commands TRCD 1 Cycle TRWL 1 Cycle ...

Page 704: ...ommand Column address 1 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDH2 tWDD2 tWDD2 tRASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 34 Synchronous DRAM Burst Write Bus Cycle Single Write 4 Bank Active Mode WRITE Command Same Row Address TRCD 1 Cycle TRWL 1 Cycle ...

Page 705: ...U L Write command Row address 1 4 Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 tWDH2 tWDD2 tRASD1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 35 Synchronous DRAM Burst Write Bus Cycle Single Write 4 Bank Active Mode PRE ACTV WRITE Commands Different Row Address TRCD...

Page 706: ...RWD1 tRWD1 tRASD1 tRASD1 tRASD1 tRASD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 CASU L High Hi Z BS CKE DQMxx DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 36 Synchronous DRAM Auto Refresh Timing TRP 2 Cycle ...

Page 707: ...WD1 tRWD1 tRASD1 tRASD1 tRASD1 tRASD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 CASU L Hi Z BS CKE DQMxx DACKn 2 tCKED1 tCKED1 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 37 Synchronous DRAM Self Refresh Timing TRP 2 Cycle ...

Page 708: ... tRWD1 tRWD1 tRWD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 CASU L Hi Z BS CKE DQMxx DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 38 Synchronous DRAM Mode Register Write Timing TRP 2 Cycle ...

Page 709: ...delay time 2 tCSD2 1 2 tcyc 1 2 tcyc 10 ns 25 39 to 25 42 Read write delay time 2 tRWD2 1 2 tcyc 1 2 tcyc 10 ns 25 39 to 25 42 Read data setup time 4 tRDS4 1 2 tcyc 6 ns 25 39 Read data hold time 4 tRDH4 0 ns 25 39 Write data delay time 3 tWDD3 1 2 tcyc 12 ns 25 39 Write data hold time 3 tWDH3 1 2 tcyc ns 25 39 RAS delay time 2 tRASD2 1 2 tcyc 1 2 tcyc 10 ns 25 39 to 25 42 CAS delay time 2 tCASD2 ...

Page 710: ... RD WR A12 A11 1 D31 to D0 tRASD2 tRASD2 tRASD2 tRASD2 RASU L tCASD2 tCASD2 tCASD2 tCASD2 CASU L tBSD tBSD tBSD tRDS4 tRDH4 tBSD BS CKE tDQMD2 tDQMD2 tDQMD2 tDQMD2 DQMxx tDACD tDACD tDACD tDACD DACKn 2 tWDH3 tWDD3 Tw High Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 39 Access Timing in Low Frequency Mode Auto Precharge ...

Page 711: ... tRASD2 tRASD2 tRASD2 tRASD2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD2 tCASD2 CASU L High Hi Z BS CKE DQMxx DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 40 Synchronous DRAM Auto Refresh Timing TRP 2 Cycle Low Frequency Mode ...

Page 712: ... tRASD2 tRASD2 tRASD2 tRASD2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD2 tCASD2 CASU L Hi Z BS CKE DQMxx DACKn 2 tCKED2 tCKED2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 41 Synchronous DRAM Self Refresh Timing TRP 2 Cycle Low Frequency Mode ...

Page 713: ...D2 tRWD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 CASU L Hi Z BS CKE DQMxx DACKn 2 Notes 1 Address pin to be connected to A10 of SDRAM 2 DACKn is a waveform when active low is specified Figure 25 42 Synchronous DRAM Mode Register Write Timing TRP 2 Cycle Low Frequency Mode ...

Page 714: ... 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Module Item Symbol Min Max Unit Figure DMAC DREQ setup time tDRQS 10 ns 25 43 DREQ hold time tDRQH 3 DACK TEND delay time tDACD 10 25 44 tDRQS tDRQH CKIO DREQn Figure 25 43 DREQ Input Timing CKIO TEND0 DACKn tDACD tDACD Figure 25 44 DACK TEND Output Timing ...

Page 715: ... Min Max Unit Figure B P clock ratio 1 1 15 B P clock ratio 2 1 tcyc 15 TMU Timer input setup time B P clock ratio 4 1 tTCLKS 3 tcyc 15 ns 25 45 Timer clock input setup time tTCKS 15 25 46 Timer clock pulse width Edge specification tTCKWH L 2 0 tpcyc Both edge specification tTCKWH L 3 0 Note tpcyc indicates a peripheral clock Pφ cycle tTCLKS CKIO TCLK input Figure 25 45 TCLK Input Timing tTCKS tTC...

Page 716: ...VCC VCCmin tROSC RTC crystal oscillator Stable oscillation Figure 25 47 Oscillation Settling Time when RTC Crystal Oscillator Is Turned On 25 3 10 16 Bit Timer Pulse Unit TPU Signal Timing Table 25 12 16 Bit Timer Pulse Unit TPU Signal Timing Conditions VCCQ VCC RTC VCC USB 3 0 to 3 6 V VCC VCC PLL1 VCC PLL2 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 t...

Page 717: ...cyc 4 tpcyc 25 49 25 50 Input clock rise time tSCKr 1 5 25 49 Input clock fall time tSCKf 1 5 Input clock pulse width tSCKW 0 4 0 6 tscyc Transmission data delay time clock synchronization tTXD 3 tpcyc 50 ns 25 50 Receive data setup time clock synchronization tRXS 2 tpcyc Receive data hold time clock synchronization tRXH 2 tpcyc RTS delay time clock synchronization tRTSD 100 CTS setup time clock s...

Page 718: ...LL2 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure Frequency 48 MHz tFREQ 47 9 48 1 MHz 25 51 Clock rise time tR48 4 ns Clock fall time tF48 4 ns Duty tHIGH tLOW tDUTY 90 110 Oscillation settling time tUOSC 10 ms 25 52 Note When the USB is operated by supplying a clock to the EXTAL_USB pin from off chip the supplied ...

Page 719: ...p Max Unit Measurement Condition Rising time tr 4 20 ns CL 50pF Falling time tf 4 20 ns CL 50pF Rising falling time ratio tr tf 90 110 Output signal crossover voltage VCRS 1 3 2 0 V CL 50pF Note This transceiver complies with the full speed specifications tr tf 90 10 Crossover voltage DP DM Measured element Vcc USB DP DM Vcc VSS RS 33Ω RL 15kΩ RL 15kΩ CL CL RL 1 5kΩ RS 33Ω 1 tr and tf are judged b...

Page 720: ...to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Module Item Symbol Min Max Unit Figure Output data delay time tPORTD 17 B P clock ratio 1 1 15 B P clock ratio 2 1 tcyc 15 Input data setup time B P clock ratio 4 1 tPORTS 3 tcyc 15 Port Input data hold time tPORTH 8 ns 25 53 tPORTS CKIO tPORTH tPORTD Ports 7 to 0 read Ports 7 to 0 write Figure 25 53 I O Port Timing ...

Page 721: ...ime tTCKcyc 50 ns 25 54 25 56 TCK high pulse width tTCKH 12 ns 25 54 TCK low pulse width tTCKL 12 ns TCK rise fall time tTCKf 4 ns TRST setup time tTRSTS 12 ns 25 55 TRST hold time tTRSTH 50 tcyc TDI setup time tTDIS 10 ns 25 56 TDI hold time tTDIH 10 ns TMS setup time tTMSS 10 ns TMS hold time tTMSH 10 ns TDO delay time tTDOD 15 ns ASEMD0 setup time tASEMD0S 12 ns 25 57 ASEMD0 hold time tASEMD0H ...

Page 722: ...690 tTRSTS tTRSTH TRST RESETP Figure 25 55 TRST Input Timing Reset Hold tTMSS tTMSH tTDOD tTCKcyc tTDIH tTDIS TCK TDI TMS TDO Figure 25 56 UDI Data Transfer Timing tASEMD0H tASEMD0S RESETP ASEMD0 Figure 25 57 ASEMD0 Input Timing ...

Page 723: ...TM ASEMD0 NMI IRQ5 to IRQ0 CKIO and MD6 to MD0 are within VSSQ to VCCQ Input rise and fall times 1 ns IOL IOH CL VREF LSI output pin Reference voltage Notes CL is the total value that includes the capacitance of measurement instruments etc and is set as follows for each pin 30 pF CKIO RASU L CASU L CS0 CS2 to CS6B BACK 50 pF All other pins IOL 1 6 mA IOH 200µA 1 2 V Figure 25 58 Output Load Circui...

Page 724: ... V VCC VCC PLL1 VCC PLL2 1 4 to 1 6 V AVCC 3 0 to 3 6 V VSSQ VSS VSS RTC VSS USB VSS PLL1 VSS PLL2 AVSS 0 V Ta 20 to 75 C Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 8 5 µs Analog input capacitance 20 pF Permissible signal source impedance single source 5 kΩ Nonlinearity error 3 0 LSB Offset error 2 0 LSB Full scale error 2 0 LSB Quantization error 0 5 LSB Absolute accuracy 4 0 ...

Page 725: ...tem control RESETM I I I I I I Pull up BREQ PTG 6 Z i P 2 i K 3 I P 2 I I IO Pull up BACK PTG 5 O O P 2 O K 3 O P 2 L P 2 O IO Open MD6 I i Z i i I Pull down MD 2 0 I i i i i I Must be used MD 5 3 I i Z i i I Must be used CA I I I I I I Pull up STATUS0 PTE 4 RTS0 H H P 2 Z 6 H K 3 Z 6 L P 2 O L P 2 O O IO O Open STATUS1 PTE 5 CTS0 H H P 2 Z 6 L K 3 Z 7 H P 2 I L P 2 I O IO I Open Interrupt IRQ 3 0...

Page 726: ... O IO Pull up CS5B PTD 6 Z O P 2 ZH 6 K 3 O P 2 Z P 2 O IO Pull up CS6A PTC 7 Z O P 2 ZH 6 K 3 O P 2 Z P 2 O IO Pull up CS6B PTD 7 Z O P 2 ZH 6 K 3 O P 2 Z P 2 O IO Pull up BS PTC 0 H O P 2 ZH 6 K 3 O P 2 Z P 2 O IO Open RASL PTD 0 H O P 2 ZH 6 K 3 O P 2 ZH 6 P 2 O IO Open RASU PTD 1 Z O P 2 ZH 6 K 3 O P 2 ZH 6 P 2 O IO Pull up CASL PTD 2 H O P 2 ZH 6 K 3 O P 2 ZH 6 P 2 O IO Open CASU PTD 3 Z O P ...

Page 727: ...2 Z K 3 I P 2 I P 2 I IO Open SCIF RxD0 SCPT 0 IrRX Z Z I 4 Z I I I I I Pull up TxD0 SCPT 0 IrTX Z Z O 5 Z O 5 O O O O O Open SCK0 SCPT 1 Z Z P 2 Z K 3 IO P 2 IO P 2 IO IO Pull up RxD2 SCPT 2 Z Z I 4 Z I I I I Pull up TxD2 SCPT 2 Z Z O 5 Z O 5 O O O O Open SCK2 SCPT 3 Z Z P 2 Z K 3 IO P 2 IO P 2 IO IO Pull up RTS2 SCPT 4 V Z P 2 Z K 3 O P O P O IO Open CTS2 SCPT 5 Z Z P 2 Z K 3 I P 2 I P 2 I IO Pu...

Page 728: ...F PTJ 6 0 H 13 O O O O O O Open NF PTM 4 I I Z I I I I Pull up PTM 3 0 V P K P P IO Open PTN 7 V P K P P IO Open AUDSYNC PTF 4 V V 10 O P 2 O K 3 O P 2 O P 2 O IO Open AUDATA 3 0 PTF 3 0 TO 3 0 V V 10 O P 2 Z 8 O K 3 Z 8 O P 2 O P 2 O IO O Open Advanced user debugger AUDCK PTG 4 O V 10 O P 2 O K 3 O P 2 O P 2 O IO Open TDI PTG 0 I 11 I 11 P 2 i 11 K 3 I 11 P 2 I 11 P 2 I IO Open TCK PTG 1 I 11 I 1...

Page 729: ...put buffer off pull up on K The high level output or low level output input becomes high impedance P Input or output depending on the register settings Notes 1 Depends on clock mode 2 The state is P when the port function is used 3 The state is K when the port function is used 4 The state is I when the port function is used 5 The state is O when the port function is used 6 The state is Z or H depe...

Page 730: ...e 13 The values of PTJ6 PTJ1 and PTJ0 differ during power on reset and after the power on reset state is released They conform to the port J data register value after being switched to port status by the pin function controller PFC After Power On Reset Release During Power On Reset PTD5 NF 1 PTD5 NF 0 PTJ6 NF 1 0 1 PTJ1 NF 1 1 0 PTJ0 NF 1 0 1 Connect the pull up pins shown in table A 1 to 3 3 V po...

Page 731: ...EDEC JEITA Mass reference value FP 208C Conforms 2 7 g Dimension including the plating thickness Base material dimension 30 0 0 2 30 0 0 2 0 5 1 70 Max 0 8 0 17 0 05 156 105 104 52 1 157 208 53 0 22 0 05 0 08 M 0 08 1 40 0 5 0 1 1 0 28 0 10 0 05 1 25 0 20 0 04 0 15 0 04 Unit mm Figure B 1 Package Dimensions FP 208C ...

Page 732: ... C C 0 10 C 0 65 0 31 0 05 1 20Max B A D C F E H G K J M L P N T R U 17 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 0 20 C A 0 20 C B B C φ0 08 A B 208 φ0 40 0 05 M A Unit mm Package Code JEDEC JEITA Mass reference value TBP 208A 0 26 g Figure B 2 Package Dimensions TBP 208A ...

Page 733: ...ntroller 149 Byte selection SRAM interface 233 Clock Pulse Generator 271 Clock synchronous mode 396 Compare match counter operation 326 Compare match timer 323 Control Registers 29 Control transfer 455 Crystal resonator 273 Cycle Steal mode 264 Data stage 457 Data Array Read 105 Data Array Write 105 Delayed Branching 40 Direct memory access controller 239 Dual Address mode 261 Emulator 567 Excepti...

Page 734: ...B 546 594 612 621 BARA 543 594 612 621 BARB 545 594 612 621 BASRA 554 594 612 621 BASRB 555 594 612 621 BBRA 544 594 612 621 BBRB 547 594 612 621 BDMRB 547 594 611 621 BDRB 546 594 611 621 BETR 552 594 611 621 BRCR 549 594 611 621 BRDR 554 594 612 621 BRSR 553 594 612 621 CCR1 586 596 614 CCR2 586 596 614 CCR3 586 596 614 CHCR 243 588 601 615 CMCNT 326 589 604 616 CMCOR 326 589 604 616 CMCSR 325 5...

Page 735: ... 620 PLDR 521 593 611 621 PMCR 499 593 610 620 PMDR 522 593 611 621 PNCR 500 593 610 620 PNCR2 502 593 610 620 PNDR 523 593 611 621 PTEH 586 595 614 PTEL 586 595 614 R64CNT 354 591 607 618 RCR1 365 591 608 618 RCR2 366 591 608 618 RCR3 368 591 608 618 RDAYAR 362 591 607 618 RDAYCNT 357 591 607 618 RHRAR 360 591 607 618 RHRCNT 355 591 607 618 RMINAR 359 591 607 618 RMINCNT 355 591 607 618 RMONAR 36...

Page 736: ...WTCSR 287 588 603 616 XVERCR 453 592 609 620 Reset State 25 Round Robin mode 258 RTC crystal oscillator circuit 372 Save Program Counter SPC 36 Save Status Register SSR 36 Scan mode 534 SDRAM interface 198 Sequential break 559 Serial communication interface with FIFO 375 Setup stage 456 Shadow space 155 Signal Source impedance 538 Single Address mode 262 Single mode 533 Single Virtual Memory Mode ...

Page 737: ...er 2002 Rev 2 00 September 19 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd 2002 2003 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 738: ...acher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688 Fax 852 2375 6836 Renesas Technology Taiwan Co Ltd FL 10 99 Fu Hsing N Rd Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd 26 F Ruijin Building No 205 Maoming...

Page 739: ...SH7705 Group Hardware Manual REJ09B0082 0200O ...

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