Regulus uREG, User Manual

Page: 58 / 107

uREG User Manual
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
level-controlled RS flip-flop (non-volatile)

level-controlled SR flip-flop

Q-edge controlled RS flip-flop

Q-edge controlled SR flip-flop

QQ*-edge controlled SR flip-flop

Edge-controlled D flip-flop

Edge-controlled D flip-flop with reset

volatile SR flip-flop, released by positive edge with Q OR-AND output

volatile SR flip-flop, released by positive edge with Q AND-OR output

volatile RS flip-flop, released by positive edge with Q OR-AND output

volatile RS flip-flop, released by positive edge with Q AND-OR output

Time delays and pulse formation [15]:

pulse generator • N-cycle delay 1

pulse extender circuit type 0 no restart • N-cycle delay 2

pulse extender circuit type 1 with restart • delay type 12

pulse extender circuit type 2 with input logic sum

pulse extender circuit type 3 no restart

positive pulse delay type 4 OR

positive pulse delay type 5 AND

double-edge delay type 6

pulse release type 7 no restart with reset

pulse delay type 8 activated by negative edge

pulse release type 10 no restart AND

pulse delay type 11 XOR

Counters [6]:

2-bit counter with decoder • 3-bit counter with decoder

sequencer with conditions • SZR /ATS/ cycle counter

SPZ cycle counter • ZS cycle counter

Decoders [6]:

1-of-4 decoder

1-of-4 decoder (conditional)

1-of-8 decoder • 1-of-8 decoder (inverted)

demultiplexer (3 in 8) • 1-of-8 decoder (with prohibition input)

Markers [4]:

AND Report & Exit (defined be setting)

NAND Report & Exit (defined be setting)

NOR Report & Exit (defined be setting)

OR Report & Exit (defined be setting)

Functors of mimic boards /synoptics/ [10]:

SZR /ATS/ interlock No • SZR /ATS/ interlock Yes

SZR /ATS/ ready No • SZR /ATS/ ready Yes