Regulus uREG, User Manual

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uREG User Manual
54
9.1.
EDITING THE
Log CZIP
APPLICATION
Any application (project) is described using one or many program sheet(s). The number of
sheets to be used is unlimited and has no logic meaning. Dividing the project into sheets (and
their corresponding number) is associated with maintaining project readability, not formal
requirements. Also, the developer’s individual style of programming is important.
The sheets are given distinct names to make them distinguishable. Information relations
between the sheets (signals) are described (declared) using
labels .
The basic component of an application description is given by
a functor ,
which represents conditional computation and, in the simplest case, consists of two items:
- relevant functional block,
and
- logic gate to set the condition for functional block activation.
The binary computation state of the functional block is reproduced at the functor output to
reveal it to related following-type functors. The logic gate monitors binary states of preceding-
type functors associated with the gate. The binary high state on the functor output is called
‘activation state’.
Complex functors usually have a few logic outputs, but no more than eight. In this case, the
activation state of the logic output results from the state of partial computation relating to the
functor associated with the output. The outputs are numbered from zero to the maximum
number. For functors with a lower than eight number of logic outputs, the output states are
reproduced on several physical outputs (not visible graphically), in uniform groups, until the
group of eight outputs is used up.
The number of outputs is usually a multiple value of the base 2, hence: 1, 2, 4 or 8.
Similarly for many outputs, functors can generally have more than one conditioning gate on
the input. Then input gates set various partial conditions to initiate computation in the
functional block. The total number of inputs of all gates is always eight. The inputs are
numbered from zero to seven. Therefore, the gates share the input pool in logically uniform
groups with 1, 2, 4 or 8 inputs.
The number of logic outputs and conditional gates determine connecting capability of the
functor. As the number of outputs and gates increases, this capacity is reduced. The situation
results from optimization purposes since the possibility of relating the functor input with a
given number to a physical output with the same number in the preceding-type functor, which
serves for the signal source. The connecting capability can be fully restored if simple
intermediate functors (gates) are applied.
An example functor with two outputs and two gates on the input is shown in the following
figure. The top gate computes the logic sum of inputs 0 to 3, whereas the bottom gate, the
conjunction of states from inputs 4 to 7. The logic state 0 on the output is reproduced on
physical outputs 0 to 3 (not shown in the drawing), whereas the output state 1 is reproduced
on physical outputs 4 to 7.