LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-9
6.3.3 Switching of System Clock
The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the
frequency control registers (FCON0, FCON1).
Figure 6-6 shows the flow chart of system clock switching processing (HSCLK to LSCLK) and Figure 6-7 shows the flow
chart of system clock switching processing (LSCLK to HSCLK).
Figure 6-6 Flow of System Clock Switching Processing (HSCLK to LSCLK)
Note:
Immediately after the recovery from the STOP mode, if the system clock is switched from HSCLK to LSCLK, the
CPU becomes inactive until LSCLK starts clock supply to the peripheral circuits. Therefore, It is recommended to
switch to LSCLK after confirming that the LSCLK is oscillating by checking that the time base counter interrupt
request bit (Q128H) is “1”.
Figure 6-7 Flow of System Clock Switching Processing (LSCLK to HSCLK)
Note:
If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK)
starts oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits.
System clock switching
ENOSC
←
”1”
Wait the oscillation
stabilization time
(T
WAIT
)
SYSCLK
←
”1”
High-speed
operation mode
T
WAIT
=500 μ s
High-speed oscillation start
Switches the system clock (low-speed clock to high-speed clock)
Yes
No
Is high-speed
clock used?
Continue to use the low-speed clock (LSCLK).
System clock switching
SYSCLK
←
”0”
Low-speed
operation mode
Switches the system clock (high-speed clock to low-speed clock)
ENOSC
←
”0”
Stops high-speed oscillation
(* Not needed to stop in the case when the high-speed clock
is used by something other than the CPU)