LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 11 UART
11-1
11. UART
11.1 Overview
This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchronous serial
interface.
For the input clock, see Chapter 6, “Clock Generation Circuit”.
The use of UART requires setting of the secondary functions of Port 4. For the secondary functions of Port 4, see Chapter
15, “Port 4”.
11.1.1 Features
•
5-bit/6-bit/7-bit/8-bit data length selectable.
•
Odd parity, even parity, or no parity selectable.
•
1 stop bit or 2 stop bits selectable.
•
Provided with parity error flag, overrun error flag, framing error flag, and transmit buffer status flag.
•
Positive logic or negative logic selectable as communication logic.
•
LSB first or MSB first selectable as a communication direction.
•
Communication speed: Settable within the range of 200bps to 38400bps.
•
Built-in baud rate generator.
11.1.2 Configuration
Figure 11-1 shows the configuration of the UART.
UA0BUF : UART0 transmit/receive buffer
UA0BRTH,L : UART0 baud rate H and L are:
UA0CON : UART0 control register
UA0MOD0,1 : UART0 mode registers 0 and 1
UA0STAT : UART0 status register
Figure 11-1 Configuration of UART
P42/RXD0
UA0BUF
Shift Register
UA0INT
Band Rate
Generator
UA0CON
UA0MOD0,1
UA0STAT
UART
Controller
P43/TXD0
LSCLK
HSCLK
Data bus
UA0BRTH,L
LSCLK
×
2
P02/RXD0