LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
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(7) When (T23MFM bit == "1") and (TM23M16 bit == "1") and (T2RUN bit == "1"),
the count up starts with the falling of the 64Hz clock signal.
(8) The count-up stops at the falling edge of the next timer clock (HTBCLK) after 437C signal becomes “1”.
Also, at the same time, T2RUN bit and T2STAT bit become “0” and the interrupt signal TM3INT activates.
The 437C signal is the pulse signal that rises in 437/32768 seconds after the falling of the 64Hz signal.
(9) After checking T2STAT bit or TM3INT interrupt occurs, read out the data (N1) of TM2C register and TM3C
register.
For example of utilizing N1, 9600Hz timer interrupt is generated.
Assuming a low-accuracy high-speed clock (HTBCLK) is exactly 600kHz, then the count value N1 is:
N1 = 600000 × 437 / 32768
= 8001 (Decimal)
= 1F41 (Hexadecimal)
= 0001 1111 0100 0001 (Binary)
Because 437/32768 seconds are equivalent to 128 clocks at 9600 Hz (more precisely, 9598 Hz),
dividing the count value NI by 128 provides the frequency ratio (N2) between the HTBCLK and 9600 Hz.
Because 128 = 2^7, this calculation can be solved by truncating the right-hand seven digits of N1 (Binary), that is:
N2 = 8001(Decimal) / 128 (Decimal)
=0001 1111 0 (Binary)
=3E (Hexadecimal)
=62 (Decimal)
This indicates that 9600Hz is about 62 times the cycle of HTBCLK.
Therefore, for an operation in the timer mode where the timer data register is set to
3EH – 1 = 3DH to overflow the counter every 62 counts of the HTBCLK clock,
the TMnINT interrupt signal cycle tTMnINT is:
tTMnINT = 1 / 600000 × 62 = 0.10333ms(9677Hz)