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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
9-12
9.3 Description of Operation
9.3.1 Timer mode operation
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 2, Timer 3 control register 0 (TMnCON0) when the TnRUN bits of Timer
2, Timer 3 control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM2C, TM3C and the Timer 2, Timer 3 data register (TMnD) coincide, Timer 2, Timer 3
interrupt (TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting
continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 2, Timer 3 control register 1
(TMnCON1) is “0”.
When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous values.
To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (T
TMI
) is expressed by the following equation.
TMnD + 1
T
TMI
=
TnCK (Hz)
(n=2, 3)
TMnD: Timer 2, Timer 3 data register (TMnD) setting value (01H to 0FFH)
TnCK: Clock frequency selected by the Timer 2, Timer 3 control register 0 (TMnCON0)
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 9-2 shows the operation timing diagram of Timer 2, Timer 3.
Figure 9-2 Operation Timing Diagram of Timer 2, Timer 3
Note:
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the Timer 2, Timer 3 interrupt (TMnINT)
may occur.
TMnC
XX
00
88
TMnD
TMnINT
TnSTAT
Write TMnC
TnCK
TnRUN
01
02
87
88
00
62
5F
60
61
01
88
88
(n=
2,
3)
T
TMI
Summary of Contents for ML610472
Page 12: ...Chapter 1 Overview...
Page 38: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 48: ...Chapter 4 MCU Control Function...
Page 62: ...Chapter 5 Interrupts...
Page 82: ...Chapter 6 Clock Generation Circuit...
Page 94: ...Chapter 7 Time Base Counter...
Page 105: ...Chapter 8 Capture...
Page 114: ...Chapter 9 Timer...
Page 133: ...Chapter 10 Watchdog Timer...
Page 141: ...Chapter 11 UART...
Page 164: ...Chapter 12 Port 0...
Page 173: ...Chapter 13 Port 2...
Page 180: ...Chapter 14 Port 3...
Page 188: ...Chapter 15 Port 4...
Page 199: ...Chapter 16 Port 6...
Page 205: ...Chapter 17 RC Oscillation Type A D Converter...
Page 225: ...Chapter 18 LCD Drivers...
Page 243: ...Chapter 19 Power Supply Circuit...
Page 245: ...Chapter 20 uEASE Flash Writer System...
Page 249: ...Chapter 21 Software Development...
Page 258: ...Appendixes...
Page 280: ...Revision History...