LAPIS Semiconductor ML610472, User Manual

Page: 83 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-1
6. Clock Generation Circuit
6.1 Overview
The clock generation circuit generates and provides a low-speed clock (LSCLK), the low-speed double clock (LSCLK x
2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK,
LSCLK x 2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and
OUTCLK is a clock that is output from a port. OUTCLK is not available in 48-pin plastic TQFP.
For the OUTCLK output port, see Chapter 13, “Port 2”.
For the STOP mode described in this chapter, see Chapter 4, "MCU Control Function."
6.1.1 Features
•
Low-Speed Clock Generation Circuit: 32.768kHz crystal oscillation mode
- Capable of using the 32.768kHz double clock LSCLK x 2 (64kHz) for some peripherals
•
High-speed clock generation circuit
- 500kHz RC oscillation mode
500kHz RC oscillation
6.1.2 Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
Figure 6-1 Configuration of Clock Generation Circuit
Note:
This LSI starts operation with the low-speed clock after power-on or a system reset. At initialization by software, set the
FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a
condition where a low-speed clock is not supplied.
XT0
XT1
High-speed clock
generation circuit
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
System clock
(SYSCLK)
MPX
FCON0,FCON1
Data bus
Dividing selection
1/1,1/2,1/4,1/8
Dividing selection
1/1,1/2,1/4,1/8
High-speed output clock
(OUTCLK)
OSCLK
Low-Speed Clock
generation circuit
Low-speed double clock
(LSCLK x 2)