LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 4 MCU Control Function
4-10
4.3.3 STOP mode
The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral
circuits stop the operation.
When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value) to the
stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”, the
STOP mode is entered. When the STOP mode is set, the STOP code acceptor is disabled.
When any of the P00 to P03 interrupt requests occurs with the interrupt enabled (the interrupt enable flag is "1"), the
STP bit is set to "0", the STOP mode is released, and the mode is returned to the program run mode.
4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock
When the stop code acceptor is in the enabled state and the STP bit of SBYCON is set to “1”, the STOP mode is entered,
stopping low-speed oscillation and high-speed oscillation.
When any of the P00 to P03 interrupt request occurs with the interrupt enabled (interrupt enabled flag is "1") state, the
STP bit becomes "0" and the low-speed oscillation resumes. If the high-speed clock was oscillating before the STOP
mode is entered, the high-speed oscillation restarts. When the high-speed clock was not oscillating before the STOP
mode is entered, high-speed oscillation does not start.
When an interrupt request occurs, the STOP mode is released after the elapse of the low-speed oscillation start time
(T
XTL
) and the low-speed clock (LSCLK) oscillation stabilization time (8192-pulse count), the mode is returned to the
program run mode, and the low-speed clock (LSCLK) restarts supply to the peripheral circuits. If the high-speed clock
already started oscillation at this time, the high-speed clocks (OSCLK and HSCLK) also restart supply to the peripheral
circuits.
For the low-speed oscillation start time (T
XTL
), see Appendix C, “Electrical Characteristics”.
Figure 4-3 shows the operation waveforms in STOP mode when CPU operates with the low-speed clock.
Figure 4-3 Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock
Low-speed
oscillation waveform
oscillation
waveform
SYSCLK
oscillation waveform
oscillation waveform
High-speed oscillation
waveform
SBYCON.STP bit
LSCLK
HSCLK
HSCLK waveform
HSCLK
Program run mode STOP mode Program run mode
Interrupt
request
T
XTL
Low-speed
oscillation
8192 counts
High-speed
oscillation
16 counts
Hiz
High-speed
oscillation
Maximum 1
count