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LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual 
Chapter 7    Time Base Counter 

7-10

 

7.3.4

 

A signal generation for 16-bit timer 2-3 frequency measurement mode 

A signal (437C) used for 16-bit timer 0-1 frequency measurement mode is generated from the output clock of the 
low-speed time base counter. See Chapter 9, “Timer” for more detail about the frequency measurement mode. 

 
 

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参照元が見つかりません。

 

 

Figure 7-6    Configuration of Frequency Measurement Mode Clock (437c) Generation Circuit 

 
 

LSCLK

 

 
 
 

TBC

 

16KHz

8KHz

4KHz

2KHz

1KHz

512Hz

256Hz

128Hz

64Hz

 
 
 

Decoder

 

D Q

437c (supplied to Timers 2 and 3)

Summary of Contents for ML610472

Page 1: ...ML610471 ML610472 ML610473 ML610Q471 ML610Q472 ML610Q473 User s Manual Issue Date Jan 7 2013 FEUL610473 09...

Page 2: ...evices such as audio visual equipment office automation equipment communication devices electronic appliances and amusement devices The Products specified in this document are not designed to be radia...

Page 3: ...onverter and also on the specifications of the assembler language CCU8 User s Manual Description on the method of operating the compiler CCU8 Programming Guide Description on the method of programming...

Page 4: ...high voltage signal levels VIH and VOH as specified by the electrical characteristics L level 0 level Indicates low voltage signal levels VIL and VOL as specified by the electrical characteristics Re...

Page 5: ...1 3 1 9 Pin Layout of ML610473 Chip 1 14 1 3 1 10 Pin Layout of ML610Q471 Chip 1 15 1 3 1 11 Pin Layout of ML610Q472 Chip 1 16 1 3 1 12 Pin Layout of ML610Q473 Chip 1 17 1 3 1 13 Pad Coordinates of M...

Page 6: ...ble Register 1 IE1 5 3 5 2 3 Interrupt Enable Register 4 IE4 5 4 5 2 4 Interrupt Enable Register 5 IE5 5 5 5 2 5 Interrupt Enable Register 6 IE6 5 6 5 2 6 Interrupt Enable Register 7 IE7 5 7 5 2 7 Int...

Page 7: ...ounter 7 7 7 3 2 High Speed Time Base Counter 7 8 7 3 3 Low Speed Time Base Counter Frequency Adjustment Function 7 9 7 3 4 A signal generation for 16 bit timer 2 3 frequency measurement mode 7 10 Cha...

Page 8: ...10 5 10 3 1 Handling example when you do not want to use the watch dog timer 10 7 Chapter 11 11 UART 11 1 11 1 Overview 11 1 11 1 1 Features 11 1 11 1 2 Configuration 11 1 11 1 3 List of Pins 11 2 11...

Page 9: ...Operation 13 6 13 3 1 Output Port Function 13 6 13 3 2 Secondary Function 13 6 Chapter 14 14 Port 3 14 1 14 1 Overview 14 1 14 1 1 Features 14 1 14 1 2 Configuration 14 1 14 1 3 List of Pins 14 1 14...

Page 10: ...scription of Operation 17 8 17 3 1 RC Oscillator Circuits 17 8 17 3 2 Counter A Counter B Reference Modes 17 10 17 3 3 Example of Use of RC Oscillation Type A D Converter 17 13 17 3 4 Monitoring RC Os...

Page 11: ...ion 20 3 Chapter 21 21 Software Development 21 1 21 1 Overview 21 1 21 2 Development Version Setting Sequence 21 1 21 3 Development Version Resetting Sequence 21 2 21 4 Notice for the Software Program...

Page 12: ...Chapter 1 Overview...

Page 13: ...0 C to 85 C are available z CPU 8 bit RISC CPU CPU name nX U8 100 Instruction system 16 bit length instruction Instruction set Transfer arithmetic operations comparison logic operations multiplication...

Page 14: ...secondary functions z LCD driver Number of segments ML610471 ML610Q471 Up to 55 dots select among 11 segments x 5 commons 12 segments x 4 commons 13 segments x 3 commons and 14 segments x 2 commons M...

Page 15: ...Q471P xxxWA ML610472P xxxWA ML610Q472P xxxWA ML610473P xxxWA ML610Q473P xxxWA 48 pin plastic TQFP ML610471 xxxTPZ03A ML610Q471 xxxTPZ0AAL ML610472 xxxTPZ03A ML610Q472 xxxTPZ0AAL ML610473 xxxTPZ03A ML6...

Page 16: ...mons and 22 segments x 2 commons with the register Figure 1 1 Block Diagram of ML610471 ML610472 ML610473 Program Memory Mask 8Kbyte RAM 512 byte Interrupt Controller CPU nX U8 100 Timing Controller E...

Page 17: ...commons with the register Figure 1 2 Block Diagram of ML610Q471 ML610Q472 ML610Q473 Program Memory Flash 8Kbyte RAM 512 byte Interrupt Controller CPU nX U8 100 Timing Controller EA SP Flash Writer In...

Page 18: ...10471 ML610Q471 48pin TQFP Package P65 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 P66 P67 SEG13 SEG12 SEG11...

Page 19: ...44 45 46 47 48 26 25 24 23 10 14 13 16 15 NC 1 VPP 2 P03 59 P02 58 P01 57 P00 56 P43 55 P42 54 P21 53 P20 52 P60 51 P61 50 P62 49 P63 P64 NC 64 63 62 61 60 NC SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0...

Page 20: ...2 48pin Package SEG16 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SE...

Page 21: ...45 46 47 48 26 25 24 23 10 14 13 16 15 NC 1 VPP 2 P03 59 P02 58 P01 57 P00 56 P43 55 P42 54 P21 53 P20 52 P60 51 P61 50 P62 49 P63 SEG17 NC 64 63 62 61 60 NC SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 CO...

Page 22: ...pin Package SEG16 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 S...

Page 23: ...6 47 48 26 25 24 23 10 14 13 16 15 NC 1 VPP 2 P03 59 P02 58 P01 57 P00 56 P43 55 P42 54 P21 53 P20 52 SEG21 51 SEG20 50 SEG19 49 SEG18 SEG17 NC 64 63 62 61 60 NC SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG...

Page 24: ...chip VSS level Figure 1 9 Dimensions of ML610471 Chip 18 P01 P00 P43 P42 P21 P20 46 P60 45 P61 44 P62 43 P63 42 P64 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SEG1...

Page 25: ...VSS level Figure 1 10 Dimensions of ML610472 Chip 18 P01 P00 P43 P42 P21 P20 46 P60 45 P61 44 P62 43 P63 42 SEG17 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SEG13...

Page 26: ...level Figure 1 11 Dimensions of ML610473 Chip 18 P01 P00 P43 P42 P21 P20 46 SEG21 45 SEG20 44 SEG19 43 SEG18 42 SEG17 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SE...

Page 27: ...S level Figure 1 12 Dimensions of ML610Q471 Chip 18 P01 P00 P43 P42 P21 P20 46 P60 45 P61 44 P62 43 P63 42 P64 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SEG13 SEG...

Page 28: ...vel Figure 1 13 Dimensions of ML610Q472 Chip 18 P01 P00 P43 P42 P21 P20 46 P60 45 P61 44 P62 43 P63 42 SEG17 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SEG13 SEG12...

Page 29: ...Figure 1 14 Dimensions of ML610Q473 Chip 18 P01 P00 P43 P42 P21 P20 46 SEG21 45 SEG20 44 SEG19 43 SEG18 42 SEG17 41 40 39 38 SEG4 SEG3 COM4 SEG2 COM3 SEG1 COM2 SEG0 COM1 COM0 VL3 VL2 VL1 C2 C1 SEG13 S...

Page 30: ...SEG15 2 3 390 779 9 P45 340 779 P65 1 10 P46 420 779 36 SEG16 2 3 470 779 11 P47 500 779 P64 1 12 P35 580 779 37 SEG17 2 3 699 587 13 C1 699 468 P63 1 2 14 C2 699 388 38 SEG18 3 699 507 15 VL1 699 30...

Page 31: ...15 2 3 560 834 9 P45 510 834 P65 1 10 P46 590 834 36 SEG16 2 3 640 834 11 P47 670 834 P64 1 12 P35 750 834 37 SEG17 2 3 869 642 13 C1 869 523 P63 1 2 14 C2 869 443 38 SEG18 3 869 562 15 VL1 869 363 P6...

Page 32: ...XT1 O Low speed clock oscillation pin 44 59 46 46 P00 EXI0 CAP0 I Input port External interrupt Capture 0 input 45 60 47 47 P01 EXI1 CAP1 I Input port External interrupt Capture 1 input 46 61 48 48 P0...

Page 33: ...ent pin 29 38 29 29 SEG9 O LCD segment pin 30 39 30 30 SEG10 O LCD segment pin 31 40 31 31 SEG11 O LCD segment pin 32 41 32 32 SEG12 O LCD segment pin 33 42 33 33 SEG13 O LCD segment pin P67 4 Output...

Page 34: ...port when used as the secondary function Primary Positive General purpose input output port P35 I O General purpose input output port This cannot be used as the general input output port when used as...

Page 35: ...imary function of the P45 pin Primary LED drive LED0 1 O N channel open drain output pins to drive LED This pin is used as the primary function of the P20 pin and P21 pin Primary Positive negative RC...

Page 36: ...o ML610471 ML610Q471 ML610472 ML610Q472 LCD driver power supply VL1 VL2 VL3 Power supply pin for LCD bias internally generated or power supply connection pin Depending on LCD Bias setting and VDD volt...

Page 37: ...pen VL3 Open C1 C2 Open RESET_N Open TEST0 Pull down 1k to VSS P00 to P03 VDD or VSS P20 P21 Open P35 Open P42 to P47 Open P60 to P67 Open COM0 to COM4 Open SEG0 to SEG21 Open Note It is recommended t...

Page 38: ...Chapter 2 CPU and Memory Space...

Page 39: ...and can be used as table data The vector table which has 16 bit long data can be used as reset vectors hardware interrupt vectors and software interrupt vectors The program memory space consists of o...

Page 40: ...hows the configuration of the data memory space DSR Data address Segment 0 0000H ROM Window Area 1FFFH 2000H DFFFH Unused area E000H E1FFH RAM area 512 byte E400H EFFFH Unused area F000H FFFFH SFR Are...

Page 41: ...72 473 Q471 Q472 Q473 User s Manual Chapter 2 CPU and Memory Space 2 3 2 4 Instruction Length The length of an instruction is 16 bits 2 5 Data Type The data types supported include byte 8 bits and wor...

Page 42: ...72 473 Q471 Q472 Q473 User s Manual Chapter 2 CPU 2 4 2 6 Description of Registers 2 6 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F000H Data segment register DSR...

Page 43: ...0 DSR DSR3 DSR2 DSR1 DSR0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 DSR is a special function register SFR to retain a data segment Always use this register with the initial st...

Page 44: ...Chapter 3 Reset Function...

Page 45: ...RESET_N pin has an internal pull up resistor 250 ms 1 sec 4 sec or 16 sec can be selected as the watchdog timer WDT overflow period Built in reset status register RSTAT indicating the reset generatio...

Page 46: ...T are not initialized while the bit indicating the cause of the reset is set to 1 When checking the reset cause using this function perform write operation to RSTAT in advance and initialize the conte...

Page 47: ...tialization is not performed by software reset due to execution of the BRK instruction See Appendix A Registers for the initial values of the SFRs CPU is initialized All the registers in CPU are initi...

Page 48: ...Chapter 4 MCU Control Function...

Page 49: ...g and only the peripheral circuit is operating STOP mode where both low speed oscillation and high speed oscillation stop Stop code acceptor function which controls transition to STOP mode Block contr...

Page 50: ...ss Name Symbol Byte Symbol Word R W Size Initial value 0F008H Stop code acceptor STPACP W 8 0F009H Standby control register SBYCON W 8 00H 0F028H Block control register 0 BLKCON0 R W 8 00H 0F029H Bloc...

Page 51: ...to 1 in this state the mode is changed to the STOP mode When the STOP mode is set the STOP code acceptor is disabled When another instruction is executed between the instruction that writes 5nH to STP...

Page 52: ...ns to the program run mode HLT bit 0 The HALT bit is used for setting a HALT mode When the HALT bit is set to 1 the mode is changed to the HALT mode When the WDT interrupt request or enabled the inter...

Page 53: ...le operating Timer 2 DTM3 bit 3 The DTM3 bit is used to control Timer 3 operation DTM3 Description 0 Enable operating Timer 3 initial value 1 Disable operating Timer 3 Note When any flag is set to 1 d...

Page 54: ...e operation DCAPR Description 0 Enable operating Capture initial value 1 Disable operating Capture Note When any flag is set to 1 disable operation the function of the applicable block is reset all re...

Page 55: ...UART operation DUA0 Description 0 Enable operating UART initial value 1 Disable operating UART Note When any flag is set to 1 disable operation the function of the applicable block is reset all regist...

Page 56: ...er DLCD bit 6 The DLCD bit is used to control LCD driver operation DLCD Description 0 Enable operating LCD driver initial value 1 Disable operating LCD driver Note When any flag is set to 1 disable op...

Page 57: ...sses that are set in the addresses 0002H and 0003H For details of the BRK instruction and PSW see the nX U8 100 Core Instruction Manual and for the reset function see Chapter 3 Reset Function 4 3 2 HA...

Page 58: ...oscillation resumes If the high speed clock was oscillating before the STOP mode is entered the high speed oscillation restarts When the high speed clock was not oscillating before the STOP mode is en...

Page 59: ...supply to the peripheral circuits after the elapse of the low speed oscillation start time TXTL and low speed clock LSCLK oscillation stabilization time 8192 count For the high speed oscillation start...

Page 60: ...instruction that sets the STP HLT bit to 1 then goes to the interrupt routine Table 4 2 Return Operation from STOP HALT Mode Maskable Interrupt ELEVEL MIE IEn m IRQn m Return operation from STOP HALT...

Page 61: ...pply to this block is stopped When this flag is set to 1 the writing to all registers in the applicable block becomes invalid and thus the reading from such register becomes the initial value When usi...

Page 62: ...Chapter 5 Interrupts...

Page 63: ...f each interrupt see the following chapters Chapter 7 Time Base Counter Chapter 9 Timer Chapter 10 Watchdog Timer Chapter 11 UART Chapter 12 Port 0 Chapter 17 RC Oscillation Type A D Converter 5 1 1 F...

Page 64: ...IE4 R W 8 00H 0F015H Interrupt enable register 5 IE5 R W 8 00H 0F016H Interrupt enable register 6 IE6 R W 8 00H 0F017H Interrupt enable register 7 IE7 R W 8 00H 0F018H Interrupt request register 0 IRQ...

Page 65: ...enable flag MIE is set to 0 but the corresponding flag of IE1 is not reset Description of Bits EP00 bit 0 EP00 is the enable flag for the input port P00 pin interrupt P00INT EP00 Description 0 Disable...

Page 66: ...unction register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE4 is not reset...

Page 67: ...a special function register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE5 i...

Page 68: ...register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE6 is not reset Descrip...

Page 69: ...tion register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE7 is not reset Des...

Page 70: ...ted to the CPU regardless of the value of the Mask Interrupt Enable flag MIE Each IRQ0 request flag is set to 1 regardless of the MIE value when an interrupt is generated By setting the IRQ0 request f...

Page 71: ...nterrupt can be generated The corresponding flag of IRQ1 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QP00 bit 0 QP00 is the request flag for the input...

Page 72: ...ster IE4 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ4 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ4 is set to 0 by...

Page 73: ...t enable register IE5 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ5 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ5 is...

Page 74: ...E6 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ6 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ6 is set to 0 by hardwa...

Page 75: ...ter IE7 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ7 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ7 is set to 0 by h...

Page 76: ...the interrupt sources Table 5 1 Interrupt Sources Priority Interrupt source Symbol Vector table address 1 Watchdog timer interrupt WDTINT 0008H 2 P00 interrupt P00INT 0010H 3 P01 interrupt P01INT 0012...

Page 77: ...cessing of program shifts to the interrupt destination 1 Transfer PC to ELR2 2 Transfer CSR to ECSR2 3 Transfer PSW to EPSW2 4 Set the ELEVEL field to 2 5 Load the interrupt start address into PC 5 3...

Page 78: ...s in the stack Processing before the master interrupt enable MIE bit is set Specify RB Exx to invalidate the accepted interrupt Exx the accepted interrupt enable flag Processing at the end of interrup...

Page 79: ...rupt enable flag Processing at the end of interrupt routine execution Specify DI not to execute the same interrupt routine Specify SB Exx to validate the accepted interrupt Exx the accepted interrupt...

Page 80: ...PSW PC Return PC from the stack Return PSW from the stack End the interrupt routine B 2 When a subroutine is called in an interrupt routine IProcessing immediately after the start of interrupt routine...

Page 81: ...uction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section an interrupt is generated immediately following the execution of the instruction at the beg...

Page 82: ...Chapter 6 Clock Generation Circuit...

Page 83: ...sing the 32 768kHz double clock LSCLK x 2 64kHz for some peripherals High speed clock generation circuit 500kHz RC oscillation mode 500kHz RC oscillation 6 1 2 Configuration Figure 6 1 shows the confi...

Page 84: ...XT0 I Pin for connecting a crystal for low speed clock XT1 O Pin for connecting a crystal for low speed clock 6 2 Description of Registers 6 2 1 List of Registers Address Name Symbol Byte Symbol Word...

Page 85: ...or system clock and peripheral circuits including high speed time base counter OSCLK 1 2OSCLK 1 4OSCLK or 1 8OSCLK can be selected The maximum operating frequency guaranteed for the system clock SYSCL...

Page 86: ...1 nOSCLK n 1 2 4 8 selected by using the high speed clock frequency select bit SYSC1 0 of FCON0 When the oscillation of high speed clock is stopped ENOSC bit 0 the SYSCLK bit is fixed to 0 and the lo...

Page 87: ...TOP mode the XT0 and XT1 pins become Hiz high impedance When the ENMLT bit of FCON1 is set to 1 the low speed double clock LSCLK x 2 starts operation Figure 6 2 Circuit Configuration of 32 768 kHz Cry...

Page 88: ...e see Chapter 4 MCU Control Function Figure 6 3 shows the waveforms of the low speed clock generation circuit For the low speed oscillation start time TXTL see Appendix C Electrical Characteristics Fi...

Page 89: ...16 counts of the RC oscillation clock Figure 6 4 shows the high speed clock circuit configuration Figure 6 4 High Speed Clock Circuit Configuration Note After the system reset mode is cleared the OSC...

Page 90: ...plies clocks to peripheral circuits following the elapse of the high speed oscillation start period TRC and the oscillation stabilization time of the high speed clock OSCLK The oscillation stabilizati...

Page 91: ...confirming that the LSCLK is oscillating by checking that the time base counter interrupt request bit Q128H is 1 Figure 6 7 Flow of System Clock Switching Processing LSCLK to HSCLK Note If the system...

Page 92: ...21C1 bit P2CON1 register s bit 1 to 1 and the P21C0 bit P2CON0 register s bit 1 to 1 for specifying the state mode of the P21 pin to CMOS output Register name P2CON1 register Address 0F213H Bit 7 6 5...

Page 93: ...he P20 pin state mode to CMOS output Register name P2CON1 register Address 0F213H Bit 7 6 5 4 3 2 1 0 Bit name P21C1 P20C1 Setting value 1 Register name P2CON0 register Address 0F212H Bit 7 6 5 4 3 2...

Page 94: ...Chapter 7 Time Base Counter...

Page 95: ...Adjustment accuracy Approx 0 48ppm by using the low speed time base counter frequency adjustment registers LTBADJH and LTBADJL HTBC generates HTB1 to HTB32 signals by dividing the high speed clock HSC...

Page 96: ...counter frequency divide register Figure 7 2 Configuration of High Speed Time Base Counter Note The frequency of HSCLK changes according to specified data in SYSC1 and SYSC0 bits of Frequency control...

Page 97: ...e Symbol Word R W Size Initial value 0F00AH Low speed time base counter register LTBR R W 8 00H 0F00BH High speed time base counter frequency divide register HTBDR R W 8 00H 0F00CH Low speed time base...

Page 98: ...lue 0 0 0 0 0 0 0 0 LTBR is a special function register SFR to read the T128HZ to T1HZ outputs of the low speed time base counter The T128HZ T1HZ outputs are set to 0 when write operation is performed...

Page 99: ...D3 HTD0 bits 3 0 The HTD3 HTD0 bits are used to set the dividing ratio of the 4 bit 1 n counter The frequency divide ratios selectable include 1 1 to 1 16 Description HTD3 HTD2 HTD1 HTD0 Dividing rati...

Page 100: ...1 0 LTBADJH LADJS LADJ9 LADJ8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 LTBADJL and LTBADJH are special function registers SFRs to set the frequency adjustment values of the l...

Page 101: ...alues coincide to prevent reading of undefined data during counting Figure 7 3 shows an example of program to read LTBR LEA offset LTBR EA LTBR address MARK L R0 EA 1st read L R1 EA 2nd read CMP R0 R1...

Page 102: ...counter the divided clock 1 16 x HSCLK to 1 1 x HSCLK selected by the high speed time base counter divide register HTBDR is generated as HTBCLK HTBCLK is used as a timer and also as an operation clock...

Page 103: ...H 0 48 0 0 0 0 0 0 0 0 0 0 0 000H 0 1 1 1 1 1 1 1 1 1 1 1 7FFH 0 48 1 1 1 1 1 1 1 1 1 1 0 7FEH 0 95 1 0 0 0 0 0 0 0 0 0 1 401H 487 80 1 0 0 0 0 0 0 0 0 0 0 400H 488 28 The adjustment values LADJ10 to...

Page 104: ...16 bit timer 0 1 frequency measurement mode is generated from the output clock of the low speed time base counter See Chapter 9 Timer for more detail about the frequency measurement mode Figure 7 6 C...

Page 105: ...Chapter 8 Capture...

Page 106: ...rupt and Chapter 12 Port 0 8 1 1 Features Time base capture x 2 channels 4096Hz to 32Hz 8 1 2 Configuration Figure 8 1 shows the configuration of the capture circuit CAPCON Capture control register CA...

Page 107: ...sters Address Name Symbol Byte Symbol Word R W Size Initial value 0F090H Capture control register CAPCON R W 8 00H 0F091H Capture status register CAPSTAT R 8 00H 0F092H Capture data register 0 CAPR0 R...

Page 108: ...0 0 0 0 0 0 CAPCON is a special function register SFR to control the capture circuit Description of Bits ECAP0 bit 0 The ECAP0 bit is used to start or stop the operation of capture 0 ECAP0 Descriptio...

Page 109: ...t data is captured in capture data register 0 CAPR0 When the CAPF0 bit is set to 1 the next capture operation is stopped So perform the write operation to capture data register 0 CAPR0 to clear the CA...

Page 110: ...CP00 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CAPR0 is a register in which capture data is stored The T4KHZ to T32HZ signals of the low speed time base counter LTBC are captur...

Page 111: ...CP10 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CAPR1 is a register in which capture data is stored The T4KHZ to T32HZ signals of the low speed time base counter LTBC are captur...

Page 112: ...R R R R R Initial value X X X X X X X X CAPTB is a special function register SFR to read the T4KHZ to T32HZ outputs of the low speed time base counter LTBC The initial value varies depending on the s...

Page 113: ...re flag CAPF0 CAPF1 is 1 the following capture operation stops The value once captured by software into the capture data register 0 or 1 CAPR0 CAPR1 is read to the CPU Then in preparation for the next...

Page 114: ...Chapter 9 Timer...

Page 115: ...which can count HTBCLK and generates the timer interrupt TM3INT when the count ends Using the count data to know the frequency by software can determine more accurate baud rate 9 1 2 Configuration Fi...

Page 116: ...lock input pin 8bit timer mode used for timer2 16bit timer mode used for timer2 timer3 P45 T3CK I External clock input pin 8bit timer mode used for timer3 TM2C Data bus TM3NT LSCLK TM2CON0 TM2CON1 R H...

Page 117: ...er TM2D R W 8 16 0FFH 0F039H Timer 2 counter register TM2C TM2DC R W 8 00H 0F03AH Timer 2 control register 0 TM2CON0 R W 8 16 0A0H 0F03BH Timer 2 control register 1 TM2CON1 TM2CON R W 8 00H 0F03CH Tim...

Page 118: ...4 3 2 1 0 TM2D T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM2D is a special function register SFR to set the value to be compared with th...

Page 119: ...4 3 2 1 0 TM3D T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM3D is a special function register SFR to set the value to be compared with th...

Page 120: ...erformed to either the low order TM2C or high order TM3C both the low order and the high order are set to 0000H During timer operation the TM2C content may not be read depending on the conditions of t...

Page 121: ...rder and the high order are set to 0000H When reading TM3C in 16 bit timer mode be sure to read TM2C first since the count value of TM3C is stored in the TM3C latch when TM2C is read During timer oper...

Page 122: ...bit timer mode each of timer 0 and timer 1 operates independently as a 8 bit timer In 16 bit timer mode timer 2 and timer 3 are connected and they operate as a 16 bit timer In 16 bit timer mode timer...

Page 123: ...ol the Timer 3 Rewrite TM3CON0 while the timer 3 is stopped T3STAT of the TM3CON1 register is 0 Description of Bits T3CS1 T3CS0 bits 1 0 The T3CS1 and T3CS0 bits are used for selecting the operation c...

Page 124: ...stop start of timer 2 Setting the T2RUN bit can force cancel the counting in the 16 bit timer frequency measurement mode In that case TM3INT does not occur T2RUN Description 0 In timer mode Stops coun...

Page 125: ...or controlling stop start of timer 3 In 16 bit timer mode and 16 bit timer frequency measurement mode be sure to set this bit to 0 Regardless of the T3RUN value the Timer 3 counts up by the Timer 2 ov...

Page 126: ...n the TnRUN bits are set to 1 again TMn restart incremental counting from the previous values To initialize TMnC to 00H perform write operation in TMnC The timer interrupt period TTMI is expressed by...

Page 127: ...cy measurement mode 1 High speed clock HSCLK HTBCLK has to be in oscillating state by controlling with FCONn registers And also select 1 1 divide ratio of the high speed time base counter by setting H...

Page 128: ...generated Assuming a low accuracy high speed clock HTBCLK is exactly 600kHz then the count value N1 is N1 600000 437 32768 8001 Decimal 1F41 Hexadecimal 0001 1111 0100 0001 Binary Because 437 32768 se...

Page 129: ...ing 2 the data UART0 baud rate registers H and L are UA0BRTH UA0BRTL frequency ratio between HTBCLK clock and baud rate 1 N1 128 1 N2 1 See Section 14 3 2 Round data in calculation N1 1011101111110 bi...

Page 130: ...cy fop in Appendix C Electrical Characteristics 9 4 1 Operating Timer 2 8 Bit Timer Mode by External Clock P44 T2CK Set the P44MD1 bit P4MOD1 register s bit 4 to 0 and the P44MD0 bit P4MOD0 register s...

Page 131: ...D1 P45MD1 P44MD1 P43MD1 P42MD1 Setting value 0 Register name P4MOD0 register Address 0F224H Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 Setting value 0 Set the the P45DIR bi...

Page 132: ...5MD1 P44MD1 P43MD1 P42MD1 Setting value 0 Register name P4MOD0 register Address 0F224H Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 Setting value 0 Set the P44DIR bit P4DIR r...

Page 133: ...Chapter 10 Watchdog Timer...

Page 134: ...signal and shifts the mode to a system reset mode For interrupts see Chapter 5 Interrupt and for WDT interrupt see Chapter 3 Reset Function 10 1 1 Features Non maskable interrupt Free running cannot...

Page 135: ...ter 10 Watchdog Timer 10 2 10 2 Description of Registers 10 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F00EH Watchdog timer control register WDTCON R W 8 00H 0F...

Page 136: ...bit is used to write data to clear the WDT counter The WDT counter can be cleared by writing 5AH with the internal pointer WDP is 0 then writing 0A5H with the WDP 1 Note When the WDT interrupt WDTINT...

Page 137: ...W R W R W R W R W R W Initial value 0 0 0 0 0 0 1 0 WDTMOD is a special function register to set the overflow period of the WDT counter Description of Bits WDT1 0 bits 1 0 These bits are used to sele...

Page 138: ...cleared within the WDT counter overflow period TWOV a watchdog timer interrupt WDTINT occurs If the WDT counter is not cleared even by the software processing performed following the watchdog timer i...

Page 139: ...hdog timer interrupt request WDTINT is generated In this case the WDT counter and the internal pointer WDP are initialiaed for a half cycle of low speed clock about 15 26us If the WDT counter is not c...

Page 140: ...and the low speed clock LSCLK starts oscillating If the WDT counter gets overflow the WDT non maskable interrupt occurs and then a system reset occurs Therefore it is needed to clear the WDT counter e...

Page 141: ...Chapter 11 UART...

Page 142: ...d with parity error flag overrun error flag framing error flag and transmit buffer status flag Positive logic or negative logic selectable as communication logic LSB first or MSB first selectable as a...

Page 143: ...e P43 pin 1 P42 is not available in 48 pin plastic TQFP 11 2 Description of Registers 11 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F290H UART0 transmit receive...

Page 144: ...f the UART0 status register UA0STAT becomes 0 then write the next transmitted data to the UA0BUF Any value written to UA0BUF can be read In receive mode since data received at termination of reception...

Page 145: ...cial function register SFR to start stop communication of the UART Description of Bits U0EN bit 0 The U0EN bit is used to specify the UART communication operation start When U0EN is set to 1 UART comm...

Page 146: ...t 4 The U0RSEL bit is used to select the received data input pin for the UART0 In 48 pin plastic TQFP P42 pin is not available Please set the R0RSEL bit to 0 U0RSEL Description 0 Selects the P02 pin I...

Page 147: ...ts U0LG1 U0LG0 bits 1 0 The U0LG1 and U0LG0 bits are used to specify the data length in the communication of the UART U0LG1 U0LG0 Description 0 0 8 bit length initial value 0 1 7 bit length 1 0 6 bit...

Page 148: ...unication of the UART U0NEG Description 0 Positive logic initial value 1 Negative logic U0DIR bit 6 The U0DIR bit is used to select LSB first or MSB first in the communication of the UART U0DIR Descri...

Page 149: ...cess R W Access size 8 bit Initial value 0FH 7 6 5 4 3 2 1 0 UA0BRTH U0BR11 U0BR10 U0BR9 U0BR8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 1 1 1 1 UA0BRTL and UA0BRTH are special functio...

Page 150: ...error initial value 1 With framing error U0OER bit 1 The U0OER bit is used to indicate occurrence of an overrun error of the UART If the received data in the transmit receive buffer UA0BUF is receive...

Page 151: ...transmit mode this bit is set to 1 and when this transmitted data is transferred to the shift register this bit is set to 0 To transmit the data consecutively confirm the U0FUL flag becomes 0 then wr...

Page 152: ...All these options are set with the UART0 mode register UA0MOD1 Figure 11 2 and Figure 11 3 show the positive logic input output format and negative logic input output format respectively Figure 11 2 P...

Page 153: ...e bit UA0BRTH UA0BRTL Error 1200bps 32 768kHz 0 0 27 Approximately 824us 00H 1AH 1 1 32 768kHz 0 0 14 Approximately 427us 00H 0DH 2 5 2400bps 65 536kHz 0 1 27 Approximately 412us 00H 1AH 1 1 32 768kHz...

Page 154: ...level is output from the TXD0 output U0B6 U0B3 U0B7 U0B5 U0B2 U0B1 U0B4 U0B0 LSB reception LSB reception Data length 8 bits Data length 7 bits Data length 6 bits U0B7 is 0 at completion of Data lengt...

Page 155: ...utput d a UART0 interrupt is requested In the UART0 interrupt routine the next data to be transmitted is written to the transmit receive buffer UA0BUF When the next data to be transmitted is written t...

Page 156: ...h h System clock UA0BUF write instruction U0EN set instruction 1st data 2nd data BRT BRT Start 0 1 2 7 Parity Start 0 2 7 Parity Stop c d Transmit receive buffer write enable period Transmit receive...

Page 157: ...k The data and parity bit are shifted into the shift register and 5 to 8 bit received data is transferred to the transmit receive buffer UA0BUF concurrently with the fall of the internal transfer cloc...

Page 158: ...Stop Start 1 2 7 1st data 2nd data Parity error Overrun error f Detection of start bit g e d c Parity error overrun error framing error detected Request for UART0 interrupt Stop receiving because the...

Page 159: ...D0 is sampled almost at the center of the baud rate then loaded to the shift register The loading sampling timing of this shift register can be adjusted for one clock of the baud rate generator clock...

Page 160: ...rate generator clock uses a lower frequency such as LSCLK and LSCLK x 2 to realize a higher bit rate e g 4800bps 9600bps Figure 11 9 shows the baud rate errors and receive margin waveforms Figure 11 9...

Page 161: ...P43 pin to CMOS output Set P42DIR bit bit2 of P4DIR register to 1 for specifying the P42 as an input pin The set value is arbitrary for the P42C1 and P42C0 bits Select an arbitrary input mode dependin...

Page 162: ...ON1 register s bit 3 to 1 the P43C0 bit P4CON0 register s bit 3 to 1 and the P43DIR bit P4DIR register s bit 3 to 0 for specifying the state mode of the P43 pin to CMOS output Register name P4CON1 reg...

Page 163: ...etting value The P02D bit P0D register bit 2 data can either be 0 or 1 not need to be set Register name P0D register Address 0F204H Bit 7 6 5 4 3 2 1 0 Bit name P03D P02D P01D P00D Setting value Bit t...

Page 164: ...Chapter 12 Port 0...

Page 165: ...pin can be used as the RXD0 input pin of UART0 12 1 2 Configuration Figure 12 1 shows the configuration of Port 0 P0D Port 0 data register P0CON0 Port 0 control register 0 P0CON1 Port 0 control regis...

Page 166: ...Initial value 0F204H Port 0 data register P0D R 8 Depends on pin state 0F206H Port 0 control register 0 P0CON0 R W 8 16 00H 0F207H Port 0 control register 1 P0CON1 P0CON R W 8 00H 0F020H External int...

Page 167: ...0 x x x x P0D is a special function register SFR to only read the pin level of Port 0 Description of Bits P03D to P00D bits 3 to 0 The P03D to P00D bits are used to read the pin level of Port 0 P03D...

Page 168: ...0 0 0 0 P0CON0 and P0CON1 are special function registers SFRs to select the input mode of Port 0 Description of Bits P03C0 to P00C0 P03C1 to P00C1 bits 3 to 0 The P03C0 to P00C0 bits and the P03C1 to...

Page 169: ...l value 0 0 0 0 0 0 0 0 EXICON0 and EXICON1 are special function registers SFRs to select an interrupt edge of Port 0 Description of Bits P03E0 to P00E0 P03E1 to P00E1 bits 3 to 0 The P03E0 to P00E0 b...

Page 170: ...ed time base counter LTBC P03SM Description 0 Detects the input signal edge for a P03 interrupt without sampling initial value 1 Detects the input signal edge for a P03 interrupt with sampling P02SM D...

Page 171: ...e P02 pin as the RXD0 input to the UART0 For the capture function see Chapter 8 Capture For the UART function see Chapter 11 UART For the timer function see Chapter 9 Timer 12 3 2 Interrupt Request Wh...

Page 172: ...Q472 Q473 User s Manual Chapter 12 Port 0 12 8 d When Rising Edge Interrupt Mode with Sampling is Selected Figure 12 2 P00 to P03 Interrupts Generation Timing SYSCLK P0n pin P0nINT Interrupt request...

Page 173: ...Chapter 13 Port 2...

Page 174: ...t mode for each bit Allows output of low speed clock LSCLK high speed clock OUTCLK as a secondary function 13 1 2 Configuration Figure 13 1 shows the configuration of Port 2 P2D Port 2 data register P...

Page 175: ...Registers 13 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F210H Port 2 data register P2D R W 8 00H 0F212H Port 2 control register 0 P2CON0 R W 8 16 00H 0F213H Por...

Page 176: ...pecial function register SFR to set the output value of the Port 2 The value of this register is output to Port 2 The value written to P2D is readable Description of Bits P20D P21D bits 0 1 The P20D b...

Page 177: ...2 Description of Bits P20C0 P21C0 P20C1 P21C1 bits 0 1 The P20C0 P21C0 P20C1 P21C1 bits are used to select high impedance output mode P channel open drain output mode N channel open drain output mode...

Page 178: ...cription 0 General purpose output port function initial value 1 High speed clock OUTCLK output function P20MD bit 0 The P20MD bit is used to select the primary function or the secondary function of th...

Page 179: ...tting the Port 2 control registers 0 and 1 P2CON0 and P2CON1 At a system reset high impedance output mode is selected as the initial state Depending of the value set in the Port 2 data register P2D a...

Page 180: ...Chapter 14 Port 3...

Page 181: ...input with a pull down resistor or input with a pull up resistor for each bit in input mode The oscillation pin RCM for the RC ADC Channel 1 are available as the secondary function mode 14 1 2 Configu...

Page 182: ...egisters Address Name Symbol Byte Symbol Word R W Size Initial value 0F218H Port 3 data register P3D R W 8 00H 0F219H Port 3 direction register P3DIR R W 8 00H 0F21AH Port 3 control register 0 P3CON0...

Page 183: ...level of the Port 3 In output mode the value of this register is output to the Port 3 pin The value written to P3D is readable In input mode the input level of the Port 3 pin is read when P3D is read...

Page 184: ...alue 00H 7 6 5 4 3 2 1 0 P3DIR P35DIR R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 P3DIR is a special function register SFR to select the input output mode of Port 3 Description o...

Page 185: ...tput mode Input or output is selected by using the P3DIR register Description of Bits P35C1 P35C0 bit 5 P35C1 and P35C0 are the bit bits for selecting the high impedance output P channel open drain ou...

Page 186: ...mary function or the secondary function of Port 3 Description of Bits P35MD0 bit 5 The P35MD0 bit is used to select the primary or secondary function of the P35 pin P35MD0 Description 0 General purpos...

Page 187: ...nput mode input mode with a pull down resistor or input mode with a pull up resistor can be selected by setting the Port 3 control registers 0 and 1 P3CON0 and P3CON1 At a system reset high impedance...

Page 188: ...Chapter 15 Port 4...

Page 189: ...input mode The P44 pin can be used as the external clock input pin for the Timer 0 and Timer 2 The P45 pin can be used as the external clock input pin for the Timer 1 and Timer 3 The UART pins RXD0 TX...

Page 190: ...tput port Timer 2 external clock input RC oscillation waveform input pin for RC ADC1 P45 T3CK CS1 I O Input output port Timer 3 external clock input Reference capacitor connection pin for RC ADC1 P46...

Page 191: ...Byte Symbol Word R W Size Initial value 0F220H Port 4 data register P4D R W 8 00H 0F221H Port 4 direction register P4DIR R W 8 00H 0F222H Port 4 control register 0 P4CON0 R W 8 16 00H 0F223H Port 4 c...

Page 192: ...ibed later Description of Bits P47D to P42D bits 7 to 2 The P47D to P42D bits are used to set the output value of the Port 4 pin in output mode and to read the pin level of the Port 4 pin in input mod...

Page 193: ...f Bits P47DIR to P42DIR bits 7 to 2 P47DIR to P42DIR are the bits for selecting the input output mode of the Port 4 pins P47DIR Description 0 P47 pin Output initial value 1 P47 pin Input P46DIR Descri...

Page 194: ...1 to P42C1 and P47C0 to P42C0 are the bits for selecting the high impedance output P channel open drain output N channel open drain output or CMOS output in output mode and for selecting the high impe...

Page 195: ...nnel open drain output Input with a pull up resistor 1 1 CMOS output High impedance input Setting of P43 pin When output mode is selected P43DIR bit 0 When input mode is selected P43DIR bit 1 P43C1 P4...

Page 196: ...7 The P47MD1 and P47MD0 bits are used to select the primary or secondary function of the P47 pin P47MD1 P47MD0 Description 0 0 General purpose input output mode initial value 0 1 Resistor sensor conne...

Page 197: ...mary secondary or tertiary function of the P42 pin In 48 pin plastic TQFP P42pin is not available P42MD1 P42MD0 Description 0 0 General purpose input output mode initial value 0 1 UART0 data input pin...

Page 198: ...mpedance output mode is selected as the initial state In output mode L or H level is output to each pin of Port 4 depending on the value set by the Port 4 data register P4D In input mode the input lev...

Page 199: ...Chapter 16 Port 6...

Page 200: ...es Allows selection of N channel open drain output or CMOS output for each bit 16 1 2 Configuration Figure 16 1 shows the configuration of Port 6 P6D Port 6 data register P6CON0 Port 6 control registe...

Page 201: ...ion of Registers 16 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F230H Port 6 data register P6D R W 8 0FFH 1 00FH 2 0F232H Port 6 control register 0 P6CON0 R W 8...

Page 202: ...4D is 1 Description of Bits P67D to P60D bit 7 to 0 The P67D to P60D bits are used to set the output value of the Port 6 pins P67D Description 0 Output level of the P67 pin L 1 Output level of the P67...

Page 203: ...to 0 P67C0 to P60C0 are the bits that select either N channel open drain output or CMOS output P67C0 Description 0 N channel open drain output initial value 1 CMOS output P66C0 Description 0 N channe...

Page 204: ...the Port 6 pins N channel open drain output mode or CMOS output mode can be selected by setting the Port 6 control register 0 P6CON0 At the system reset N channel open drain output mode is selected a...

Page 205: ...Chapter 17 RC Oscillation Type A D Converter...

Page 206: ...uit 17 1 1 Features 1 channel system by time division 17 1 2 Configuration The RC ADC consists of the RC oscillator circuit to form the channel Counter A RADCA0 and RADCA1 and Counter B RADCB0 and RAD...

Page 207: ...P44 IN1 I Channel 1 oscillation input pin Used for the secondary function of the P44 pin P45 CS1 O Channel 1 reference capacitor connection pin Used for the secondary function of the P45 pin P46 RS1...

Page 208: ...ss Name Symbol Byte Symbol Word R W Size Initial value 0F300H RC ADC Counter A register 0 RADCA0 R W 8 00H 0F301H RC ADC Counter A register 1 RADCA1 R W 8 00H 0F304H RC ADC Counter B register 0 RADCB0...

Page 209: ...4 3 2 1 0 RADCA1 RAA15 RAA14 RAA13 RAA12 RAA11 RAA10 RAA9 RAA8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 RADCA0 and RADCA1 are special function registers SFRs for reading from...

Page 210: ...4 3 2 1 0 RADCB1 RAB15 RAB14 RAB13 RAB12 RAB11 RAB10 RAB9 RAB8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 RADCB0 and RADCB1 are special function registers SFRs for reading from...

Page 211: ...ohibited 0 1 0 1 RS1 CS1 oscillation mode 0 1 1 0 RT1 CS1 oscillation mode 0 1 1 1 IN1 pin external clock input mode 1 Prohibited RADI bit 4 The RADI bit is used to choose whether to generate the RC A...

Page 212: ...0 RADCON is a special function register SFR used to control A D conversion operation of the RC ADC Description of Bits RARUN bit 0 The RARUN bit is used to start or stop A D conversion of the RC ADC...

Page 213: ...uit RCOSC1 and 2 the RC monitor pin RCM that outputs RC oscillation waveforms respectively For the RC oscillator circuit configuration see 17 1 2 Configuration For the secondary functions of Port 3 se...

Page 214: ...e of the supply voltage VDD RI R or C Table 17 2 lists the typical kRCCLK values Table 17 2 Typical Values of the Proportional Constant kRCCLK of RC Oscillator Circuits VDD V CS1 pF CVR1 pF RS1 RT1 k...

Page 215: ...RADCA0 the value obtained by subtracting the count value nA0 from the maximum value 1 10000H The product of the count value nA0 and the BSCLK clock cycle indicates the gate time d Preset 0000H to Coun...

Page 216: ...cycle indicates the gate time d Preset 0000H to Counter A RADCA1 and RADCA0 e Set the OM3 OM0 bits of RADMOD to desired oscillation mode See Table 17 1 f Set the RADI bit of RADMOD to 1 to specify ge...

Page 217: ...K 0000H 0001H 0002H 0003H nA1 2 nA1 1 nA1 tBSCLK g h nA1xtBSCLK d 10000H nB1 1 2 0FFFEHH 0FFFFHH 0000H c nB1xtRCCLK Gate time i Interrupt request tRCCLK RARUN BSCLK RCON Counter A RC oscillator circui...

Page 218: ...ture T nT0 K RT1 K f T Expression A Therefore temperature T can be expressed as a digital value by performing the conversion processing that accords with the characteristics shown in Figure 17 6 for n...

Page 219: ...asically one A D conversion cycle must consist of two steps as shown in Figure 17 11 The reason for requiring two steps is that the reference resistor and the thermistor must first be oscillated separ...

Page 220: ...32 768 kHz Write 00H in FCON0 d Preset 10000H nA0 in Counter A e Preset 0000H in Counter B f Write 01H in RADMOD to select Counter A reference mode and the oscillation mode that uses reference resista...

Page 221: ...t to 1 and an RC ADC interrupt request is generated Section d Also the generation of interrupt request releases HALT mode section e and at the same time A D conversion operation stops Section f RARUN...

Page 222: ...ship between a sensor such as a thermistor and the oscillation frequency can be measured For instance the coefficient for conversion from the above described nA1 value to a temperature indication valu...

Page 223: ...3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 Setting value 1 1 1 1 Set the P47C1 to P44C1 bits P4CON1 register bits 7 to 4 to 0 the P47C0 to P44C0 bits P4CON0 register bits 7 to 4 to 0 and the...

Page 224: ...17 19 Register name P4D register Address 0F220H Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D Setting value Bit not related to the RC ADC function Don t care Note Status of output pins P45 P4...

Page 225: ...Chapter 18 LCD Drivers...

Page 226: ...mber of dots 55 75 95 The LCD display function consists of four blocks as shown in Figure 18 1 1 Display registers 2 Display control 3 Driver Figure 18 1 Configuration of LCD Display Function The disp...

Page 227: ...ge multiplying clock selectable 8 types 18 1 2 Configuration of the LCD Drivers Figure 18 4 shows the configuration of the LCD drivers and the bias generation circuit BIASCON Bias circuit control regi...

Page 228: ...3 1 and 18 3 2 show the configuration of the bias generation circuit Figure 18 3 1 Configuration of Bias Generation Circuit 1 3 Bias Bias generation circuit VDD VSS Bias circuit ON selected BSON To LC...

Page 229: ...Bias Bias generation circuit VDD VSS Bias circuit ON selected BSON To LCD driver VL1 to VL3 VDD 1 25 to 3 6V with LCD regulator VDD Voltage regulator circuit VDDL Cl VL3 VL2 Cc VL1 C2 C1 C12 Bias gen...

Page 230: ...in for LCD bias generation COM0 O LCD common pin COM1 O LCD common pin COM2 SEG0 O LCD common segment pin COM3 SEG1 O LCD common segment pin COM4 SEG2 O LCD common segment pin SEG3 O LCD segment pin S...

Page 231: ...f Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F0F0H Bias circuit control register BIASCON R W 8 38H 0F0F2H Display mode register 0 DSPMOD0 R W 8 00H 0F0F4H Display control r...

Page 232: ...bit 3 to 1 The BSN2 to BSN0 bits are used to select a clock for multiplying the bias voltage in the bias generation circuit LSCLK to 1 128LSCLK can be selected BSN2 BSN1 BSN0 Description 0 0 0 1 1 LS...

Page 233: ...ue 2c 14s 2c 18s 2c 22s 0 0 1 1 2 duty 2c 14s 2c 18s 2c 22s 0 1 0 1 3 duty 3c 13s 3c 17s 3c 21s 0 1 1 1 4 duty 4c 12s 4c 16s 4c 20s 1 1 5 duty 5c 11s 5c 15s 5c 19s FRM1 FRM0 bit 6 5 The FRM1 to FRM0 b...

Page 234: ...LCD display mode and all LCDs on mode can be selected In LCD stop mode Vss level is output to all the common drivers and segment drivers The charge and discharge current to and from the display panel...

Page 235: ...DSPRxx xx 00 to 15H are special function registers SFRs to store display data Each valid bit of DSPRxx becomes undefined at system reset The display registers that are not used for LCD display can be...

Page 236: ...R W DSPR06 0F106H SEG6 c4 c3 c2 c1 c0 R W DSPR07 0F107H SEG7 c4 c3 c2 c1 c0 R W DSPR08 0F108H SEG8 c4 c3 c2 c1 c0 R W DSPR09 0F109H SEG9 c4 c3 c2 c1 c0 R W DSPR0A 0F10AH SEG10 c4 c3 c2 c1 c0 R W DSPR0...

Page 237: ...e common and segment pins By using the bias circuit control register BIASCON select 1 2 bias or 1 3 bias and select the bias voltage multiplying clock Set a frame frequency and a duty by using the dis...

Page 238: ...C 2 DSPR0C 1 DSPR0C 0 DSPR0D 3 DSPR0D 2 DSPR0D 1 DSPR0D 0 For ML610471 Q471 DSPR0D 4 DSPR0C 4 DDSPR01 4 DSPR00 4 COM4 DSPR00 3 SEG0 COM0 COM1 COM2 COM3 DSPR00 2 DSPR00 1 DSPR00 0 DSPR01 3 DSPR01 2 DSP...

Page 239: ...18 6 shows the common output waveform at 1 5 duty 5 commons and 1 3 bias Figure 18 6 Common Output Waveform at 1 5 Duty 5 Commons and 1 3 Bias 0 1 2 3 0 1 COM0 COM1 COM2 COM3 VL3 VL2 VL1 VSS VL3 VL2...

Page 240: ...ows the common output waveform at 1 5 duty 5 commons and 1 2 bias Figure 18 7 Common Output Waveform at 1 5 Duty 5 Commons and 1 2 Bias 0 1 2 3 0 1 COM0 COM1 COM2 COM3 VL3 VL12 VSS VL3 VL12 VSS VL3 VL...

Page 241: ...and 1 3 Bias 0 1 2 3 0 1 2 4 SEGn SEGn VL3 VL2 VL1 VSS VL3 VL2 VL1 VSS Frame frequency About 64Hz 73Hz 85Hz 102Hz 0 0 0 0 0 0 0 SEGn VL3 VL2 VL1 VSS SEGn VL3 VL2 VL1 VSS SEGn VL3 VL2 VL1 VSS SEGn VL3...

Page 242: ...1 2 Bias 0 1 2 3 0 1 2 4 SEGn SEGn VL3 VL12 VSS VL3 VL12 VSS Frame frequency About 64Hz 73Hz 85Hz 102Hz 0 0 0 0 0 0 0 SEGn VL3 VL12 VSS SEGn VL3 VL12 VSS SEGn VL3 VL12 VSS SEGn VL3 VL12 VSS SEGn VL3...

Page 243: ...Chapter 19 Power Supply Circuit...

Page 244: ...ram memory RAM low speed oscillation etc 19 1 2 Configuration Figure 19 1 shows the configuration of the power supply circuit Figure 19 1 Configuration of Power Supply Circuit 19 1 3 List of Pins Pin...

Page 245: ...Chapter 20 uEASE Flash Writer System...

Page 246: ...nection to the uEASE Note Please do not apply LSIs being used for debugging to mass production When using the flash rewrite function after mounting of the board design the board so that the 6 pins VPP...

Page 247: ...command prompt by using CD command move to the folder which the complete HEX data is located in 3 On the U8 command prompt execute HTU command Example HTU8 ML610Q471 hex AL 0000H 1EFFH 0000H ML610Q471...

Page 248: ...se of 2 Kwords 4 Kbytes 1 word write Write of 1 word 2 bytes Table 20 3 shows the conditions and specifications of Flash memory rewrite Table 20 3 Specifications of Flash Memory Rewrite Parameter Spec...

Page 249: ...Chapter 21 Software Development...

Page 250: ...e by the steps shown below The steps explain an example of Development version ML610Q471 setting on ML610Q407 reference board 1 Connect ML610Q407 reference board and uEASE 1 2 Connect uEASE and PC wit...

Page 251: ...uEASE from PC ML610Q407 mode resetting is completed After re boot the reference board uEASE recognizes ML601Q407 reference board as ML610Q407 21 4 Notice for the Software Program Development 21 4 1 No...

Page 252: ...configuration data3 cseg at 03deeh dw 0a55ah Target configuration data4 cseg at 03df0h dw 8h DUP 0ffffh cseg 0 at 01f00h dw 0E80h DUP 0ffffh Unused address region and test region program for ML610Q47...

Page 253: ...on program into the your program Usable Unusable region for the program on the Flash memory address in each development version is shown below Address Development version ML610Q471 472 473 0000H 1EFFH...

Page 254: ...es Tone length 63 types Tempo 15 types Buzzer output mode 13 RC Oscillation Type A D Converter 16 bit counter Time division x 2 channels 16 bit counter Time division x 1 channels 14 LCD Drives segment...

Page 255: ...T0 I Low speed clock oscillation pin XT1 O Low speed clock oscillation pin P00 EXI0 CAP0 I Input port External interrupt Capture 0 input P01 EXI1 CAP1 I Input port External interrupt Capture 1 input P...

Page 256: ...rnal clock input Tertiary SCK0 I O SSIO0 synchronous clock input output 1 Secondary RS1 O RC type ADC1 reference resistor connection pin P46 I O Input output port Tertiary SOUT 0 O SSIO0 data output 1...

Page 257: ...t pin SEG7 O LCD segment pin SEG8 O LCD segment pin SEG9 O LCD segment pin SEG10 O LCD segment pin SEG11 O LCD segment pin SEG12 O LCD segment pin SEG13 O LCD segment pin SEG14 O LCD segment pin SEG15...

Page 258: ...Appendixes...

Page 259: ...W 8 00H 0F018H Interrupt request register 0 IRQ0 R W 8 00H 0F019H Interrupt request register 1 IRQ1 R W 8 00H 0F01CH Interrupt request register 4 IRQ4 R W 8 00H 0F01DH Interrupt request register 5 IR...

Page 260: ...F110H Display register 10 DSPR10 R W 8 Undefined 0F111H Display register 11 DSPR11 R W 8 Undefined 0F112H Display register 12 DSPR12 R W 8 Undefined 0F113H Display register 13 DSPR13 R W 8 Undefined 0...

Page 261: ...ART0 baud rate register H UA0BRTH UA0BRT R W 8 0FH 0F296H UART0 status register UA0STAT R W 8 00H 0F300H RC ADC Counter A register 0 RADCA0 R W 8 00H 0F301H RC ADC Counter A register 1 RADCA1 R W 8 00...

Page 262: ...s More than 5 m Package weight g 0 26typ Rev No Last Revised 1 Nov 10 2011 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow moun...

Page 263: ...han 5 m Package weight g 0 13typ Rev No Last Revised 3 Nov 9 2011 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and...

Page 264: ...ion PD Ta 25 C 0 9 W Storage temperature TSTG 55 to 150 C Recommended Operation Condition VSS 0V Parameter Symbol Condition Range Unit without P version 20 to 70 Operating temperature TOP P version 40...

Page 265: ...eristics 1 6 VDD 1 25 to 3 6V VSS 0V Ta 20 to 70 C Ta 40 to 85 C for P version unless otherwise specified Rating Parameter Symbol Condition Min Typ Max Unit Measur ement circuit Ta 25 C Typ 10 500 Typ...

Page 266: ...ise specified Rating Parameter Symbol Condition Min Typ Max Unit Measur ement circuit VDDL voltage VDDL fop 30k to 625kHz 1 1 1 2 1 3 V VDDL temperature deviation 1 VDDL VDD 3 0V 1 mV C VDDL voltage d...

Page 267: ...ed operating temperature Ta 20 to 70 C Ta 40 to 85 C for P version 6 LCD stop mode 1 3 bias Bias voltage multiplying clock 1 128 LSCLK 256Hz DC Characteristics for ML610Q471 Q472 Q473 4 6 VDD 3 0V VSS...

Page 268: ...ML3S 0 05mA VL1 1 2V VL2 0 2 VOLM3 IOLM3 0 05mA VL1 1 2V VL1 0 2 VOLM3S IOLM3S 0 05mA VL1 1 2V VL1 0 2 Output voltage 3 COM0 to 4 SEG0 to 13 1 SEG0 to 17 2 SEG0 to 21 3 VOL3 IOL3 0 05mA VL1 1 2V 0 2 V...

Page 269: ...SS 0V Ta 20 to 70 C Ta 40 to 85 C for P version unless otherwise specified Rating Parameter Symbol Condition Min Typ Max Unit Measur ement circuit VIH1 0 7 VDD VDD Input voltage 1 RESET_N TEST0 P00 to...

Page 270: ...L2 VL3 Cc VSS C2 C1 C12 CV 1 F CL 2 2uF Ca Cb Cc 0 1 F C12 0 47 F 32 768kHz crystal resonator DT 26 Load capacitance 6pF Made by KDS DAISHINKU CORP CGL CDL 6pF CV CDL 32 768kHz crystal resonator Input...

Page 271: ...VIL Output pin Note1 Input logic circuit to determine the specified measuring conditions Note2 Repeats for the specified output pin Note 2 Note1 Input pin A VDD VDDL VL1 VL2 VL3 VSS Output pin Note1...

Page 272: ...C Characteristics UART VDD 1 25 to 3 6V VSS 0V Ta 20 to 70 C Ta 40 to 85 C for P version unless otherwise specified Rating Parameter Symbol Condition Min Typ Max Unit Transmit baud rate tTBRT BRT 1 s...

Page 273: ...58 18 62 43 kHz Oscillation frequency VDD 3 0V fOSC3 Resistor for oscillation 100k 5 43 5 89 6 32 kHz Kf1 RT1 1k 7 972 9 028 9 782 Kf2 RT1 10k 0 981 1 1 019 RS to RT oscillation frequency ratio 1 VDD...

Page 274: ...0k 0 141 0 145 0 149 1 Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions fOSCX RT1 CS1 oscillation Kfx...

Page 275: ...10471 472 473 Q471 Q472 Q473 Application Circuit Diagram LCD ML610Q473 C2 C1 C12 VL3 VL2 VL1 VDD TEST0 VPP VDDL VSS CV CP CL 32 768kHz crystal resonator CGL CDL XT0 XT1 Cc Ca RESET_N TEST VPP VDDL VSS...

Page 276: ...ppendix C 2 in the user s manual Reset status flag No flag is provided that indicates the occurrence of reset by the RESET_N pin Refer to section 3 2 2 in the user s manual BRK instruction reset In sy...

Page 277: ...r How to read the timer counter registers Check notes for reading the timer counter registers while counting up Refer to Sections 9 2 4 to 9 2 5 in the user s manual Chapter 10 WDT Overflow period Cle...

Page 278: ...471 3COM x 13SEG ML610471 ML610Q471 4COM x 12SEG ML610471 ML610Q471 5COM x 11SEG ML610472 ML610Q472 2COM x 18SEG ML610472 ML610Q472 3COM x 17SEG ML610472 ML610Q472 4COM x 16SEG ML610472 ML610Q472 5COM...

Page 279: ...nected to VDD pin CL 0 47uF to 2 2uF connected to VDDL pin Chapter 20 uEASE Flash Writer System Supply a voltage from 3 0V to 3 6V to the VDD pin when programming erasing and writing the Flash ROM wit...

Page 280: ...Revision History...

Page 281: ...2uF FEUL610Q473 0 Jul 18 2012 1 3 B 1 B 2 1 3 B 1 B 2 The package dimension was changed C 1 C 1 The notes about CV CL were added 1 25 D 1 1 25 D 1 The pull down register 1k to VSS was added FEUL610Q4...

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