LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
9-7
9.2.5 Timer 3 Counter Register (TM3C)
Address: 0F03DH
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
TM3C T3C7 T3C6 T3C5 T3C4 T3C3 T3C2 T3C1 T3C0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TM3C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM3C is performed, TM3C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode and 16-bit timer frequency measurement mode, if write operation is performed to either the
low-order (TM2C) or high-order (TM3C), both the low order and the high order are set to “0000H”.
When reading TM3C in 16-bit timer mode, be sure to read TM2C first since the count value of TM3C is stored in the
TM3C latch when TM2C is read.
During timer operation, the TM3C content may not be read depending on the conditions of the timer clock and the
system clock.
Table 9-2 shows whether a TM3C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Table 9-2 TM3C Read Enable/Disable during Timer Operation
Timer clock
T3CK
System clock
SYSCLK
TM3C read enable/disable
LSCLK LSCLK Read enabled.
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined data
during incremental counting, read TM3C twice and check that the
results match.
HTBCLK LSCLK Read disabled.
HTBCLK HSCLK Read enabled.
LSCLK
External clock
HSCLK
Read disabled.