LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-8
5.2.7 Interrupt Request Register 0 (IRQ0)
Address: 0F018H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
IRQ0 — — — — — — — QWDT
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source.
The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that do not depend on MIE. In this case, an
interrupt is requested to the CPU regardless of the value of the Mask Interrupt Enable flag (MIE).
Each IRQ0 request flag is set to “1” regardless of the MIE value when an interrupt is generated. By setting the IRQ0
request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ0 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
•
QWDT (bit 0)
QWDT is the request flag for the watchdog timer interrupt (WDTINT).
QWDT Description
0 No request (initial value)
1 Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the interrupt shift
cycle starts after the next 1 instruction is executed.