LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 11 UART
11-11
11.3 Description of Operation
11.3.1 Transfer Data Format
In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits
can be selected as data bit. For the parity bit, “with parity bit”, “without parity bit”, “even parity”, or “odd parity” can be
selected. For the stop bit, “1 stop bit” or “2 stop bits” are available and for the transfer direction, “LSB first” or “MSB
first” are available for selection. For serial input/output logic, positive logic or negative logic can be selected.
All these options are set with the UART0 mode register (UA0MOD1).
Figure 11-2 and Figure 11-3 show the positive logic input/output format and negative logic input/output format,
respectively.
Figure 11-2 Positive Logic Input/Output Format
Figure 11-3 Negative Logic Input/Output Format
Start
bit
1
2
3
4 5
6
7 8
Parity
bit
Data bit
1 frame
•1 frame
Max. ... 12 bits
Min. ... 7 bits
•Data bit length ... 8 to 5 bits variable
•Parity bit ... With or without parity bit selectable
Odd or even parity selectable
•Stop bit ... 1 or 2 stop bits selectable
Stop
bit
Stop
bit
Start
bit
1 2 3 4 5 6 7 8
Parity
bit
Data bit
1 frame
Stop
bit
Stop
bit
•1 frame
Max. ... 12 bits
Min. ... 7 bits
•Data bit length ... 8 to 5 bits variable
•Parity bit ... With or without parity bit selectable
Odd or even parity selectable
•Stop bit ... 1 or 2 stop bits selectable