LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 1 Overview
1-4
1.2 Configuration of Functional Blocks
1.2.1 Block Diagram of ML610471/ML610472/ML610473
*
Secondary function or Tertiary function
(*1) Select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons with the register
(*2) Select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons with the register
(*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons with the register
Figure 1-1 Block Diagram of ML610471/ML610472/ML610473
Program
Memory
(Mask)
8Kbyte
RAM
512 byte
Interrupt
Controller
CPU (nX-U8/100)
Timing
Controller
EA
SP
Flash
Writer
Instruction
Decoder
BUS
Controller Instruction
Register
TBC
INT
4
INT
1
WDT
INT
2
8bit Timer
×
2
Capture
×
2
GPIO
INT
5
Data-bus
TEST0
RESET_N
OSC
XT0
XT1
LSCLK*
Power
V
DDL
LCD
Driver
LCD
BIAS
V
L1
, V
L2
, V
L3
C1, C2
RC-ADC
×
1
RCM*
CS1*
IN1*
RS1*
RT1*
RESET
&
TEST
ALU
EPSW1
−
3
PSW
ELR1
−
3
LR
ECSR1
−
3
DSR/CSR
PC
GREG
0
−
15
V
DD
V
SS
INT
1
Display
register
110bit
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG13 (ML610471) (*1)
SEG0 to SEG17 (ML610472) (*2)
SEG0 to SEG21 (ML610473) (*3)
P00 to P03
P20, P21
P35
P42 to P47
P60 to P67 (ML610471)
P60 to P63 (ML610472)
UART
INT
1
RXD0*
TXD0*