LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 18 LCD Drivers
18-9
18.2.4 Display Control Register (DSPCON)
Address: 0F0F4H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
DSPCON — — — — — — LMD1 LMD0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
DSPCON is a special function register (SFR) to control the LCD drivers.
[Description of Bits]
•
LMD1-LMD0 (bit 1, 0)
The LMD1 and LMD0 bits are used to select an LCD display mode.
LCD stop mode, all LCDs off mode, LCD display mode, and all LCDs on mode can be selected.
In LCD stop mode, V
ss
level is output to all the common drivers and segment drivers. The charge and discharge
current to and from the display panel can be stopped.
In all LCDs off mode, off waveform is output to all the segment drivers irrespective of the contents of the
display registers.
In LCD display mode, the contents of the display registers are output to each segment driver.
In all LCDs on mode, on waveform is output to all the segment drivers irrespective of the contents of the display
registers.
LMD1 LMD0
Description
0 0 LCD stop mode (initial value)
0 1 All LCDs off mode
1 0 LCD display mode
1 1 All LCDs on mode