LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 10 Watchdog Timer
10-3
10.2.2 Watchdog Timer Control Register (WDTCON)
Address: 0F00EH
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
WDTCON
d7 d6 d5 d4 d3 d2 d1 WDP/d0
R/W W W W W W W W R/W
Initial value 0 0 0 0 0 0 0 0
WDTCON is a special function register (SFR) to clear the WDT counter.
When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.
[Description of Bits]
•
WDP/d0 (bit 0)
The value of the internal pointer (WDP) is read from this bit. The WDP is reset to “0” at the system reset or WDT
counter overflow and is inverted every writing to WDTCON.
•
d7-d0 (bits 7-0)
This bit is used to write data to clear the WDT counter. The WDT counter can be cleared by writing "5AH" with
the internal pointer (WDP) is "0", then writing "0A5H" with the WDP "1".
Note:
When the WDT interrupt (WDTINT) occurs by the first WDT counter overflow, the counter and the internal pointer
(WDP) are initialiaed for a half cycle of low speed clock (about 15us). During the time period that they are initialized,
writing to WDTCON is disable and the logic of WDP does not change. Therefore, in the case of that you have
program codes handle to clear the WDT when the first overflow WDT interrupt occurs and also the codes run at
high-speed system clock, please check the WDP gets reversed after writing to WDTCON to see if the writing was
surely successful. For example of the program code, see Section 10.3.1, "Handling example when you do not want to
use the watch dog timer".