LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-13
5.2.12 Interrupt Request Register 7 (IRQ7)
Address: 0F01FH
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
IRQ7 — — — — Q2H — — Q16H
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ7 request flag is set to “1” regardless of the IE7 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE7) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ7 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ7 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
•
Q16H (bit 0)
Q16H is the request flag for the time base counter 8 Hz interrupt (T8HINT).
Q16H Description
0 No request (initial value)
1 Request
•
Q2H (bit 3)
Q2H is the request flag for the time base counter 2 Hz interrupt (T2HINT).
Q2H Description
0 No request (initial value)
1 Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ7) or to the interrupt
enable register (IE7), the interrupt shift cycle starts after the next 1 instruction is executed.