LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-4
6.2.3 Frequency Control Register 1 (FCON1)
Address: 0F003H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
FCON1
— — — — —
ENMLT ENOSC SYSCLK
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
•
SYSCLK (bit 0)
The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK
(1/nOSCLK: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0.
When the oscillation of high-speed clock is stopped (ENOSC bit = “0”), the SYSCLK bit is fixed to “0” and the
low-speed clock (LSCLK) is selected for system clock.
SYSCLK
Description
0 LSCLK (initial value)
1 HSCLK
•
ENOSC (bit 1)
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator circuit.
ENOSC
Description
0 Stops high-speed oscillation (initial value)
1 Enables high-speed oscillation
•
ENMLT (bit 2)
The ENMLT bit is used to select enable/disable of the operation of the low-speed double clock (LSCLK x 2).
ENMLT
Description
0 Disables low-speed double clock operation (initial value)
1 Enables low-speed double clock operation