LAPIS Semiconductor ML610472, User Manual

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 2 CPU and Memory Space
2-5
2.6.2 Data Segment Register (DSR)
Address: 0F000H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
DSR — — — — DSR3 DSR2 DSR1 DSR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
DSR is a special function register (SFR) to retain a data segment.
Always use this register with the initial state (0). For details of DSR, see “nX-U8/100 Core Instruction Manual”.
[Description of Bits]
•
DSR3-DSR0 (bits 3 to 0)
DSR3 DSR2 DSR1 DSR0 Description
0 0 0 0 Initial value
In other than above Prohibited