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Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.2.2
MPSoC Reset
The Zynq Ult MPSoC SBC
uses PMIC’s Reset output (
nRESET) for PS Power On Reset and connected to
PS_POR_B pin of MPSoC. Also it supports warm reset input from Reset Switch (SW2) and connected to PS_SRST_B pin
of MPSoC.
2.2.3
MPSoC Reference Clock
The Zynq Ult MPSoC SBC supports on board clock oscillators for reference clock to different blocks of Zynq
Ult MPSoC. These reference clock details are mentioned in the below table.
Table 3: Zynq Ult MPSoC SBC Reference Clock.
Sl.
No
On-SBC Oscillator
Frequency
SoC Ball Name/
Pin Number
Signal Type/
Termination
Description
1
33.33MHz
PS_REF_CLK /
R16
1.8V, LVCMOS
33.33Mhz single ended reference
clock for PS.
2
100MHz
¹
IO_L5P_HDGC_AD7P_43 /
AE12
1.8V², LVCMOS
100Mhz single ended reference
clock for PL. This is connected to PL
Bank43 HDGC Global clock pin.
3
300MHz
IO_L13N_T2L_N1_GC_QBC_66 /
D6
IO_L13P_T2L_N0_GC_QBC_66 /
D7
1.8V, LVDS
LVDS reference clock for PL DDR4
SDRAM. This is connected to PL
Bank66 Global clock pins.
¹ Important Note: I/O voltage of PL Bank43 is software configurable. Since this oscillator supports 1.8V to 3.3V VCC
only, this reference clock can be used only if the I/O voltage of PL Bank43 is set between 1.8V to 3.3V.
²
Mentioned voltage level is based on after uboot bootup I/O voltage set to PL Bank43.
