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Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.
ARCHITECTURE AND DESIGN
This section provides detailed information about the Zynq Ult MPSoC SBC features and Hardware architecture
with high level block diagram. Also, this section provides detailed information about Board to Board connectors pin
assignment and usage.
2.1
Zynq Ult MPSoC SBC Block Diagram
EEPROM
(For MAC ADDR)
WLAN+BT
DDR4
–
2GB
(Upgradable)
USB2.0
PHY
4 Port
USB Hub
iW-RainboW-G36S-Zynq Ult MPSoC SBC Block Diagram
1
. DP Dual line supports upto 4K resolution.
2
CG devices supports Dual ARM Cortex-A53 & Dual ARM Cortex-R5. EG devices supports Quad ARM Cortex-A53, Dual ARM Cortex-R5 & Mali-400MP2 GPU. EV devices supports Quad ARM
Cortex-A53, Dual ARM Cortex-R5 , Mali-400MP2 GPU & H.264/H.265 VCU.
³ SYSMONE4 supports 10bit 200KSPS ADC and supports upto 17 Analog Inputs (One dedicated Analog input and 16 auxiliary analog input from any PL BANK)
4
GTH Transceiver block is supported in ZU4 & ZU5 MPSoC with data rates up to 12.5Gb/s. GTH transceiver block is not supported in ZU2 & ZU3 MPSoC.
“ “ This symbol indicates Hardware assembly options available in the board and by default which option is support
ed. Contact iWave to support other assembly option.
Micro SD
(Optional)
DP
Connector ¹
GEM0
ULPI
DDR
Memory
Controller
SD0
DDR4 (64bit)
DDR4 (ECC)
(Optional)
eMMC
–
8GB
(Upgradable)
DDR4 ECC (8bit)
eMMC (8bit)
USB0
SD1
UART x 1
UART1
Ethernet
PHY1
Gigabit Ethernet1
RGMII
GEM3
Ethernet
PHY2
Gigabit Ethernet2
RGMII
CAN x 2
CAN0, CAN1
Lane0
P
S
G
TR
Tr
an
sce
iv
er
Lane1
Lane3
M.2 Key B
Connector
Lane2
DP (2nd Lane) x 1
SATA x 1
USB 3.0/2.0 x 2
DP (1st Lane) x 1
Dual RJ45
Magjack
Processing System (PS)
Quad/Dual ARM Cortex-A53,
Dual Cortex-R5,Mali-400MP2,VCU
Programmable Logic (PL)
I2C0
USB3.0/2.0 x 1
Zynq Ult (SFVC784)
ZU4/ZU5 - CG/EG/EV
²
ZU2/ZU3 - CG/EG
²
Debug UART
Header
Debug UART
UART0
JTAG Header
JTAG
PS JTAG
SPI0,I2C1
SPI x 1, I2C x 1
HD Bank
43,44
FPGA (13LVDS/26SE)
USB3.0 x 1
Dual Stack
USB 3.0 TypeA
Nano SIM
Connector
SIM
HP
Bank
64
FPGA IOs
Antenna
Connectors
RF (WLAN, BT )
SD (4bit) x 1
Bank 224
CH3
GTH Transceiver
4
High Speed Transceiver x 1
4
SDI Video Out
BNC Jack
(Optional)
SDI Video In
BNC Jack
(Optional)
SFP+ Conn
12V Power
Connector
Power
Regulators
Power to
Peripherals
12V
RTC Coin cell
Header
PMIC
HP Bank
65,66
DDR4
–
1GB
(Upgradable)
DDR4 (32bit)
HD Bank
46
B2B
Connector 3
B2B
Connector 1
FPGA (12LVDS/24SE) ³
B2B
Connector 2
FPGA (23LVDS/46SE)
HD Bank
45
FPGA (4LVDS/8SE)
HDMI Output
Connector
HDMI Input
Connector
Bank 224
CH[2:0]
High Speed Transceiver x 3
FPGA (7LVDS/14SE)
SYSMONE4
From B2B Connecor2
I2C x 1
FPGA (2LVDS/4SE)
From HD Bank45
Clock
Generator
To Transceiver
Bank
Figure 1: Zynq Ult MPSoC SBC Block Diagram
