REL0.2
Page 36 of 88
Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table 6: SFP+ Connector Pin Assignment
Pin
No
Pin
Name
MPSoC Pin
Name
MPSoC
Bank
MPSoC
Pin No
Signal Type/
Termination
Description
1
VEET1
NA
NA
NA
Power
Ground.
2
TFAULT
NA
NA
NA
I, LVTTL/
4.7K PU
Module Transmitter Fault.
3
TDIS
NA
NA
NA
O, LVTTL/
4.7K PD
Transmitter Disable.
4
SDA
PS_MIO11_50
0
500
AE17
IO,
3.3V
CMOS
I2C Data.
5
SCL
PS_MIO10_50
0
500
AD17
O, 3.3V CMOS I2C Clock.
6
MOD_ABS
NA
NA
NA
I, 3.3V
CMOS/
4.7K PU
Module Definition.
7
RS0
NA
NA
NA
O, 3.3V
CMOS/
4.7K PU
Rate select 0.
This Pin is connected to PMIC GPIO7
for software control if required.
8
RX_LOS
NA
NA
NA
I, 3.3V
CMOS/
4.7K PU
Receiver loss of signal indication.
This Pin is connected to PMIC GPIO10
for software control if required.
9
RS1
NA
NA
NA
O, 3.3V
CMOS/
4.7K PU
Rate select 1.
This Pin is connected to PMIC GPIO09
for software control if required.
10
VEER1
NA
NA
NA
Power
Ground.
11
VEER2
NA
NA
NA
Power
Ground.
12
RD-
MGTHRXN3_2
24
224
P1
I, DIFF
SFP+ Receiver Data Negative.
13
RD+
MGTHRXP3_2
24
224
P2
I, DIFF
SFP+ Receiver Data Positive.
14
VEER3
NA
NA
NA
Power
Ground.
15
VCCR
NA
NA
NA
O,
3.3V
Power
3.3V Receiver Supply Voltage.
16
VCCT
NA
NA
NA
O,
3.3V
Power
3.3V Transmitter Supply Voltage.
17
VEET2
NA
NA
NA
Power
Ground.
18
TD+
MGTHTXP3_2
24
224
N4
O, DIFF
SFP+ Transmit Data Positive.
19
TD-
MGTHTXN3_2
24
224
N3
O, DIFF
SFP+ Transmit Data Negative.
20
VEET3
NA
NA
NA
Power
Ground.