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Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.10.1.2
PL IOs
–
HD BANK45
The Zynq Ult MPSoC SBC supports 4 LVDS IOs/8 Single Ended (SE) IOs on Board to Board Connector2 from
MPSoC
’s
PL High-Density (HD) Bank45. Upon these 4 LVDS IOs/8 SE IOs, upto 4 PLSYSMON auxiliary analog inputs are
available.
The IO voltage of Bank45 is connected from LDO4 output of the PMIC and supports variable IO voltage setting. IO
voltage is configurable from 1.2V to 3.3V through software. While using as LVDS IOs or Single Ended IOs, make sure to
set the PMIC LDO4 to output appropriate IO voltage for PL Bank45. By default, IO voltage of PL Bank45 is set as 1.2V
and after U-boot bootup configured to 1.8V. For more details about supported IO standard, refer the Zynq Ult
MPSoC datasheet.
In the Zynq Ult MPSoC SBC, PL Bank45 signals are routed as LVDS IOs to Board to Board Connector2. Even
though PL Bank45 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board
Connector2 pins 47, 48, 51, 52, 53, 54, 55 and 56 are PLSYSMON auxiliary analog Input capable pins of PL Bank45.
Note: In ZCU2 & ZCU3 MPSoC devices, the PL Bank 43, 44, 45 & 46 is called as 44, 24, 25 & 26 respectively. Only the
Bank Numbering is different and all other functionalities remain same.
For more details on PL HD Bank45 pinouts on Board to Board Connector2, refer the below table.
B2B2
Pin No
Signal Name
MPSoC
Pin Name
MPSoC
Bank
MPSoC
Pin No
Signal Type/
Termination
Description
47
PL_H11_LVDS45_
L3P
IO_L3P_AD13P_45
45
H11
IO, 1.8V LVDS PL Bank45 IO3 differential
positive.
Same
pin
can
be
configured as PLSYSMON
differential analog input13
positive or Single ended
I/O.
48
PL_G10_LVDS45_
L3N
IO_L3N_AD13N_45
45
G10
IO, 1.8V LVDS PL Bank45 IO3 differential
negative.
Same
pin
can
be
configured as PLSYSMON
differential analog input13
negative or Single ended
I/O.
