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Zynq Ult MPSoC SBC Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

2.7.3

SFP+ Connector

The Zynq Ult MPSoC SBC supports SFP+ Connector for 10G Ethernet support. The

Zynq Ult MPSoC’s

PL GTH Bank224 Channel3 is connected to SFP+ connector. Also PS I2C0 is connected to this connector for control and

configuration. All other contorl signals of SFP+ connnector is connected from PMIC GPIOs. This SFP+ connector with

dust case (J13) is physically located at the top of the board as shown below.

Important Note: In Zynq Ult MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So

either SFP+ or SDI IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI

IN & Out.

Figure 13: SFP+ Connector

Summary of Contents for iW-G36S-2CG1-4E002G-E008G-BEA

Page 1: ...REL0 2 Page 1 of 88 Zynq Ultrascale MPSoC SBC Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G36S Zynq Ultrascale MPSoC SBC Hardware User Guide...

Page 2: ...This document contains proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by ot...

Page 3: ...n errata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Ce...

Page 4: ...ADC 21 2 4 PMIC with RTC 21 2 5 Memory 22 2 5 1 DDR4 SDRAM for PS 22 2 5 2 DDR4 SDRAM for PL 22 2 5 3 eMMC Flash 22 2 5 4 EEPROM 22 2 5 5 Micro SD Connector Optional 23 2 6 Fearures from PS Block 24 2...

Page 5: ...BANK64 55 2 11 1 2 PL IOs HD BANK45 58 2 11 1 3 PL IOs HD BANK46 60 2 11 2 Power 65 2 12 Board to Board Connector3 66 2 12 1 PL Interfaces 68 2 12 1 1 PL IOs HD BANK43 68 2 12 1 2 PL IOs HD BANK44 73...

Page 6: ...r 27 Figure 9 Dual Stack USB3 0 Type A Jack 28 Figure 10 M 2 Key B Connector 29 Figure 11 HDMI IN Connector 33 Figure 12 HDMI Out Connector 34 Figure 13 SFP Connector 35 Figure 14 JTAG Header 39 Figur...

Page 7: ...ector Pin Assignment 36 Table 7 Clock Synthesier Output Clocks 38 Table 8 JTAG Header Pinout 39 Table 9 Fan Header Pinout 40 Table 10 RTC Header Pinout 41 Table 11 Board to Board Connector1 Pinout 44...

Page 8: ...high speed ruggedized terminal strip connectors provide the interface to carry all the I O signals from Zynq Ultrascale MPSoC 1 3 List of Acronyms The following acronyms will be used throughout this...

Page 9: ...d Through hole PL Programmable Logic PS Processing System RGMII Reduced Gigabit Media Independent Interface RTC Real Time Clock SBC Single Board Computer SD Secure Digital SDIO Secure Digital Input Ou...

Page 10: ...ctor Signal LVDS Low Voltage Differential Signal GBE Gigabit Ethernet Media Dependent Interface differential pair signals USB Universal Serial Bus differential pair signals OD Open Drain Signal OC Ope...

Page 11: ...option Micro SD Optional DP Connector GEM0 ULPI DDR Memory Controller SD0 DDR4 64bit DDR4 ECC Optional eMMC 8GB Upgradable DDR4 ECC 8bit eMMC 8bit USB0 SD1 UART x 1 UART1 Ethernet PHY1 Gigabit Ethern...

Page 12: ...Logic with up to 256K Logic cells and Processing System with integrated Quad core ARM Cortex A53 MPCore Application processor up to 1 5GHz Dual core ARM Cortex R5 MPCore Real Time Processor up to 600...

Page 13: ...ional 4 3G 12G SDI Output through HD BNC Jack Optional 4 Additional Features Clock Synthesizer Generator JTAG Header FAN Header RTC Coin Cell Header Power On OFF Reset Switch Board to Board Connector1...

Page 14: ...V PL IOs HD Bank46 Upto 12 LVDS IOs 24 Single ended SE IOs o Upto 4 GC Global Clock Input pins LVDS SE o Upto 12 ADC Input pins Differential Single Ended o Variable IO voltage support from 1 2V to 3 3...

Page 15: ...So either Bluetooth or Board to Board connector1 UART can be supported By default UART1 is supported in Bluetooth in SBC Contact iWave to support UART1 on Board to Board Connector1 Important Note Sin...

Page 16: ...The Zynq Ultrascale MPSoC SBC is based on Xilinx Zynq Ultrascale MPSoC with SFVC784 package Zynq Ultrascale MPSoC family integrates Processing system PS and Xilinx programmable logic PL in a single d...

Page 17: ...The Zynq Ultrascale MPSoC s PS has 78 dedicated I O pins referred as MIO Multiplexed I O for the PS peripheral interfaces These 78 MIO pins are divided into three banks PS BANK500 501 502 and each ba...

Page 18: ...zed in banks of 24pins In Zynq Ultrascale MPSoC PL each bank supports four global clock GC or HDGC input pin pairs GC pins have direct access to the global clock buffers MMCMs and PLLs of the same Ban...

Page 19: ...ference Clock Sl No On SBC Oscillator Frequency SoC Ball Name Pin Number Signal Type Termination Description 1 33 33MHz PS_REF_CLK R16 1 8V LVCMOS 33 33Mhz single ended reference clock for PS 2 100MHz...

Page 20: ...ge The Zynq Ultrascale MPSoC SBC supports two LEDs for the MPSoC error status indication namely PS_ERROR_OUT and PS_ERROR_STATUS LED D1 is for PS_ERROR_OUT and it is asserted for accidental loss of po...

Page 21: ...mperature sensors one is physically located in the PS SYSMON near the RPU The second remote sensor is located in the FPD near the APU The ADC always uses an internally generated voltage reference 2 3...

Page 22: ...mum of 32GB based on the availability of higher density 16bit DDR4 device The Zynq Ultrascale MPSoC SBC supports 300MHz LVDS Oscillator on board for PL DDR4 reference clock and connected to Bank64 D6...

Page 23: ...o Micro SD Connector J24 through auto direction control memory card voltage level translator to support 1 8V and 3 3V supported cards It supports up to 4 Bit data transfer with card detect The memory...

Page 24: ...MPSoC is used for dual Ethernet support The GEM0 GEM3 MAC is integrated in the Zynq Ultrascale MPSoC PS and connected to the external individual Gigabit Ethernet PHY AR8031 on SBC Also both the Ether...

Page 25: ...er Management The Zynq Ultrascale MPSoC PS SD1 SDHC controller through MIO pins are used for Wi Fi interface which supports 1 bit or 4 bit transfer mode at the clock range of 0 50 MHz and works at 1 8...

Page 26: ...der J14 through 1 8V to 3 3V Level Translator This UART Header can be used for Debug purpose which is physically located at the top of the board as shown below Figure 7 Debug UART Header Table 4 Debug...

Page 27: ...2 Connector 2 lanes of DisplayPort TX only at 1 62Gb s 2 7Gb s or 5 4Gb s 1 lane of USB3 0 channels at 5 0Gb s 1 lane of SATA channels at 1 5Gb s 3 0Gb s or 6 0Gb s 2 6 1 Display Port Connector The Zy...

Page 28: ...tor To support backward compatibility USB 2 0 interface also supported through this HUB The USB0 controller of Zynq Ultrascale MPSoC PS is used for USB 2 0 interface through on board ULPI transceiver...

Page 29: ...and USB3 0 interface through M 2 Key B connector PS GTR3 Lane of Zynq Ultrascale MPSoC PS is used for SATA interface USB3 0 and USB2 0 Signals are connected from USB3 0 HUB MPSoC s SATA supports SATA...

Page 30: ...d from 17th pin of 4 Port USB HUB U33 8 W_DISABLE1 NA NA NA O 3 3V CMOS 10K PU M 2 Wireless Disable Signal This signal is configuring from PMIC GPIO2 U14 9 USB_D NA NA NA IO USB USB2 0 Port3 USB data...

Page 31: ...Transmit pair negative This pin is connected from 20th pin of 4 Port USB HUB U33 36 UIM PWR NA NA NA O SIM Power SIM Card Power 37 PETP1 USB3 1 TX SSIC TXP NA NA NA O DIFF USB3 0 Port3 Transmit pair...

Page 32: ...NA NA NA NA NC 62 COEX_TXD NA NA NA NA NC 63 ANTCTL2 NA NA NA NA NC 64 COEX_RXD NA NA NA NA NC 65 ANTCTL3 NA NA NA NA NC 66 SIM_DETECT NA NA NA NA NC 67 RESET NA NA NA NA NC 68 SUSCLK 32KHZ NA NA NA N...

Page 33: ...ese features from PL GTH are not supported in ZU3 ZU2 Zynq Ultrascale MPSoC based SBC Important Note In Zynq Ultrascale MPSoC SBC GTH Transceiver Channel3 is shared with SFP and SDI In Out So either S...

Page 34: ...gh HDMI TypeA connector J11 The Zynq Ultrascale MPSoC s PL GTH Bank224 Channel0 to Channel2 transmitter is directly connected to HDMI Retimer chip SN65DP159RGZR and then connected to HDMI Out Connecto...

Page 35: ...S I2C0 is connected to this connector for control and configuration All other contorl signals of SFP connnector is connected from PMIC GPIOs This SFP connector with dust case J13 is physically located...

Page 36: ...for software control if required 8 RX_LOS NA NA NA I 3 3V CMOS 4 7K PU Receiver loss of signal indication This Pin is connected to PMIC GPIO10 for software control if required 9 RS1 NA NA NA O 3 3V CM...

Page 37: ...Transceiver Channel3 is shared with SFP and SDI In Out So either SFP or SDI IN Out only can be supported By default SFP is supported in SBC Contact iWave to support SDI IN Out 2 7 5 3G 12G SDI Output...

Page 38: ...LK0P_224 148 5 MHz Zynq US MPSoC U12 Y6 18 OUT2b GTREFCLK0N_224 Zynq US MPSoC U12 Y5 22 OUT3 GTREFCLK1P_224 148 5 MHz Zynq US MPSoC U12 V6 21 OUT3b GTREFCLK1N_224 Zynq US MPSoC U12 V5 27 OUT4 PS_MGTRE...

Page 39: ...ption 1 NC 2 VCC_3V3 O 3 3V Power Supply Voltage 3 GND Power Ground 4 JTAG_TMS I 3 3V LVCMOS 49 9K PU JTAG Test Mode Select 5 GND Power Ground 6 JTAG_TCK I 3 3V LVCMOS 49 9K PU JTAG Test Clock 7 GND P...

Page 40: ...ed The Fan Header J12 is physically located on topside of the SBC as shown below Number of Pins 2 Connector Part 0530470210 from Molex Mating Connector 51021 0200 from Molex Compatible Fan Example AFB...

Page 41: ...ll through external cable This coin cell voltage is connected to Zynq Ultrascale MPSoC SBC for RTC back up voltage when VCC main power is off This Coin Cell Header J6 is physically located at the top...

Page 42: ...is power ON OFF switch is physically located at the top of the board as shown below Figure 17 Power ON OFF Switch 2 8 6 Reset Switch The Zynq Ultrascale MPSoC SBC supports Push button switch SW2 to re...

Page 43: ...rovide the maximum interfaces of Zynq Ultrascale MPSoC to SBC by adding these three Board to Board Connectors The Zynq Ultrascale MPSoC SBC Board to Board Connector1 pinout is provided in the below ta...

Page 44: ...LVDS64_L10N_QBC 19 20 SPI0_SCLK PS_MIO0_500 PL_AG6_LVDS64_L10P_QBC 21 22 I2C1_SCL PS_MIO24_500 GND 23 24 I2C1_SDA PS_MIO25_500 PL_AH7_LVDS64_L9N 25 26 GND PL_AH8_LVDS64_L9P 27 28 CAN1_RX PS_MIO41_501...

Page 45: ...PS_MI O5_500 PS_MIO5_ 500 500 AD16 IO 1 8V LVCMOS SPI Master output Slave input 18 SPI0_SS0 PS_MIO3 _500 PS_MIO3_ 500 500 AH15 O 1 8V LVCMOS SPI chip select0 20 SPI0_SCLK PS_MIO 0_500 PS_MIO0_ 500 50...

Page 46: ...DA PS_MIO 25_500 PS_MIO25 _500 500 AB21 IO 1 8V OD 4 7K PU I2C1 data 2 9 2 PL Interfaces 2 9 2 1 PL IOs HP BANK64 The Zynq Ultrascale MPSoC SBC supports 13 LVDS IOs 26 Single Ended SE IOs on Board to...

Page 47: ...O 1 8V LVDS PL Bank64 IO12 differential negative Same pin can be configured as HDGC Global Clock Input differential negative or Single ended I O 7 PL_AF6_LVDS64_ L11N_GC IO_L11N_T1U_N9_ GC_64 64 AF6 I...

Page 48: ...O 21 PL_AG6_LVDS64_ L10P_QBC IO_L10P_T1U_N6_ QBC_AD4P_64 64 AG6 IO 1 8V LVDS PL Bank64 IO10 differential positive Same pin can be configured as PLSYSMON differential analog input4 positive or Single e...

Page 49: ...39 PL_AE9_LVDS64_ L2P IO_L2P_T0L_N2_64 64 AE9 IO 1 8V LVDS PL Bank64 IO2 differential positive Same pin can be configured as Single ended I O 43 PL_AE7_LVDS64_ L4N_DBC IO_L4N_T0U_N7_D BC_AD7N_64 64 A...

Page 50: ...ositive or Single ended I O 57 PL_AC6_LVDS64_ L6N IO_L6N_T0U_N11_ AD6N_64 64 AC6 IO 1 8V LVDS PL Bank64 IO6 differential negative Same pin can be configured as PLSYSMON differential analog input6 nega...

Page 51: ...tive or Single ended I O 2 9 2 2 PL IOs HD BANK45 The Zynq Ultrascale MPSoC SBC supports 4 Single Ended SE IOs on Board to Board Connector1 from MPSoC s PL High Density HD Bank45 Upon these 4 SE IOs a...

Page 52: ...45 45 B11 IO 1 8V LVCMOS PL Bank45 IO10 Single ended I O 8 PL_A10_LVDS45_ L10N IO_L10N_AD10N_4 5 45 A10 IO 1 8V LVCMOS PL Bank45 IO10 Single ended I O 2 9 3 Power In Zynq Ultrascale MPSoC SBC 5V and 1...

Page 53: ...provide the maximum interfaces of Zynq Ultrascale MPSoC to SBC by adding these three Board to Board Connectors The Zynq Ultrascale MPSoC SBC Board to Board Connector2 pinout is provided in the below t...

Page 54: ...19 20 GND PL_L14_LVDS46_L12P 21 22 PL_L13_LVDS46_L12N PL_G15_LVDS46_L9P 23 24 PL_G14_LVDS46_L9N PL_B15_LVDS46_L1P 25 26 PL_A15_LVDS46_L1N PL_D15_LVDS46_L5P_GC 27 28 PL_D14_LVDS46_L5N_GC GND 29 30 GND...

Page 55: ...signals are routed as LVDS IOs to Board to Board Connector2 Even though PL Bank64 signals are routed as LVDS IOs these pins can be used as SE IOs if required The Board to Board Connector2 pins 15 and...

Page 56: ...15N_T2L_N5_ AD11N_64 64 AB3 IO 1 8V LVDS PL Bank64 IO15 differential negative Same pin can be configured as PLSYSMON differential analog input11 negative or Single ended I O 7 PL_AB2_LVDS64_ L17P IO_L...

Page 57: ...tive Same pin can be configured as PLSYSMON differential analog input3 positive or Single ended I O 14 PL_AD1_LVDS64_ L16N_QBC IO_L16N_T2U_N7_ QBC_AD3N_64 64 AD1 IO 1 8V LVDS PL Bank64 IO16 differenti...

Page 58: ...MPSoC SBC PL Bank45 signals are routed as LVDS IOs to Board to Board Connector2 Even though PL Bank45 signals are routed as LVDS IOs these pins can be used as SE IOs if required The Board to Board Co...

Page 59: ...ended I O 53 PL_J11_LVDS45_L 1P IO_L1P_AD15P_45 45 J11 IO 1 8V LVDS PL Bank45 IO1 differential positive Same pin can be configured as PLSYSMON differential analog input15 positive or Single ended I O...

Page 60: ...Board Connector2 Even though PL Bank46 signals are routed as LVDS IOs these pins can be used as SE IOs if required The Board to Board Connector2 pins 27 28 37 38 41 42 43 and 44 are HDGC Global Clock...

Page 61: ...gle ended I O 23 PL_G15_LVDS46_ L9P IO_L9P_AD3P_46 46 G15 IO 1 8V LVDS PL Bank46 IO9 differential positive Same pin can be configured as PLSYSMON differential analog input3 positive or Single ended I...

Page 62: ...fferential negative Same pin can be configured as HDGC Global Clock Input differential negative or PLSYSMON differential analog input7 negative or Single ended I O 31 PL_C14_LVDS46_ L4P IO_L4P_AD8P_46...

Page 63: ...ential analog input9 positive or Single ended I O 36 PL_A13_LVDS46_ L3N IO_L3N_AD9N_46 46 A13 IO 1 8V LVDS PL Bank46 IO3 differential negative Same pin can be configured as PLSYSMON differential analo...

Page 64: ...46 46 E15 IO 1 8V LVDS PL Bank46 IO8 differential negative Same pin can be configured as HDGC Global Clock Input differential negative or PLSYSMON differential analog input4 negative or Single ended I...

Page 65: ...IO10 differential negative Same pin can be configured as PLSYSMON differential analog input2 negative or Single ended I O 2 10 2Power In Zynq Ultrascale MPSoC SBC 5V and 12V powers are fed to Board t...

Page 66: ...provide the maximum interfaces of Zynq Ultrascale MPSoC to SBC by adding these three Board to Board Connectors The Zynq Ultrascale MPSoC SBC Board to Board Connector3 pinout is provided in the below t...

Page 67: ...19 20 GND PL_W12_LVDS44_L11P 21 22 PL_W11_LVDS44_L11N PL_Y12_LVDS44_L12P 23 24 PL_AA12_LVDS44_L12N PL_AG14_LVDS44_L2P 25 26 PL_AH14_LVDS44_L2N GND 27 28 GND PL_AG13_LVDS44_L3P 29 30 PL_AH13_LVDS44_L3N...

Page 68: ...IOs to Board to Board Connector3 Even though PL Bank43 signals are routed as LVDS IOs these pins can be used as SE IOs if required The Board to Board Connector3 pins 41 42 43 44 53 and 54 are HDGC Glo...

Page 69: ...nded I O 35 PL_AA11_LVDS43 _L9P IO_L9P_AD3P_43 43 AA11 IO 1 8V LVDS PL Bank43 IO9 differential positive Same pin can be configured as PLSYSMON differential analog input3 positive or Single ended I O 3...

Page 70: ...43 AC11 IO 1 8V LVDS PL Bank43 IO8 differential negative Same pin can be configured as HDGC Global Clock Input differential negative or PLSYSMON differential analog input4 negative or Single ended I O...

Page 71: ...ed I O 49 PL_AF11_LVDS43 _L2P IO_L2P_AD10P_43 43 AF11 IO 1 8V LVDS PL Bank43 IO2 differential positive Same pin can be configured as PLSYSMON differential analog input10 positive or Single ended I O 5...

Page 72: ...ended I O 54 PL_AD12_LVDS43 _L6N_HDGC IO_L6N_HDGC_AD6 N_43 43 AD12 IO 1 8V LVDS PL Bank43 IO6 differential negative Same pin can be configured as HDGC Global Clock Input differential negative or PLSY...

Page 73: ...IOs to Board to Board Connector3 Even though PL Bank44 signals are routed as LVDS IOs these pins can be used as SE IOs if required The Board to Board Connector3 pins 5 6 7 8 11 12 17 and 18 are HDGC G...

Page 74: ...O 5 PL_AD15_LVDS44 _L5P_HDGC IO_L5P_HDGC_44 44 AD15 IO 1 8V LVDS PL Bank44 IO5 differential positive Same pin can be configured as HDGC Global Clock Input differential positive or Single ended I O 6 P...

Page 75: ...le ended I O 13 PL_Y14_LVDS44_ L10P IO_L10P_AD10P_44 44 Y14 IO 1 8V LVDS PL Bank44 IO10 differential positive Same pin can be configured as PLSYSMON differential analog input10 positive or Single ende...

Page 76: ...gle ended I O 21 PL_W12_LVDS44 _L11P IO_L11P_AD9P_44 44 W12 IO 1 8V LVDS PL Bank44 IO11 differential positive Same pin can be configured as PLSYSMON differential analog input9 positive or Single ended...

Page 77: ...44 IO3 differential positive Same pin can be configured as PLSYSMON differential analog input13 positive or Single ended I O 30 PL_AH13_LVDS44 _L3N IO_L3N_AD13N_44 44 AH13 IO 1 8V LVDS PL Bank44 IO3 d...

Page 78: ...GEM0 NA PS_MIO26_501 GPIO26 GEM0_TX_CLK CAN0_RX I2C0_SCL PJTAG_TCK SPI0_SCLK UART0_RX NA PS_MIO27_501 GPIO27 GEM0_TXD0 CAN0_TX I2C0_SDA PJTAG_TDI SPI0_SS2 UART0_TX NA PS_MIO28_501 GPIO28 GEM0_TXD1 CA...

Page 79: ...N1_TX I2C1_SCL SPI1_SCLK UART1_TX NA PS_MIO45_501 GPIO45 GEM1_RXD0 eMMC _DATA4 SD1_CD CAN1_RX I2C1_SDA SPI1_SS2 UART1_RX NA PS_MIO43_501 GPIO43 GEM1_TX_CTL eMMC_DATA2 SD1_PWR CAN0_TX I2C0_SDA SPI0_MIO...

Page 80: ...PSoC SBC is designed to work with 12V external power and uses on board voltage regulators for internal power management 12V power input from an external power supply is connected to the Zynq Ultrascal...

Page 81: ...r Output Specification Sl No Power Rail Min V Typical V Max V Max Output Current To Board to Board Connector1 1 VCC_5V 4 85V 5V 5 15V 500mA 2 VCC_1V8 1 75 1 8 1 85 500mA To Board to Board Connector2 1...

Page 82: ...d find necessary thermal solution in the system before using this board in the end application 3 3 2 RoHS2 Compliance iWave s Zynq Ultrascale MPSoC SBC is designed by using RoHS2 compliant components...

Page 83: ...s 3 4 1 Zynq Ultrascale MPSoC SBC Mechanical Dimensions Zynq Ultrascale MPSoC SBC PCB size is 72mm x 100 mm x 1 6mm SBC mechanical dimension is shown below Measured dimensions are all in MM Figure 23...

Page 84: ...t component is HDMI IN Out Connectors J11 J9 16 40mm followed by USB Type A connector J17 16 20mm and bottom side maximum height component is Board to Board connectors J21 J22 J26 7 37mm followed by I...

Page 85: ...B EMMC HDMI In Out SDI and Wi Fi Boot code Extended iW G36S 5EV1 4E002G E008G BEC ZU5EV 1 MPSOC XCZU5EV 1SFVC784E 2GB PS DDR4 1GB PL DDR4 8GB EMMC HDMI In Out SFP Boot code Extended iW G36S 5EV1 4E002...

Page 86: ...E008G BIC ZU4EV 1 MPSOC XCZU4EV 1SFVC784I 2GB PS DDR4 1GB PL DDR4 8GB EMMC HDMI In Out SFP Boot code Industrial iW G36S 4EV1 4E002G E008G BID ZU4EV 1 MPSOC XCZU4EV 1SFVC784I 2GB PS DDR4 1GB PL DDR4 8...

Page 87: ...Ultrascale MPSoC SBC Hardware User Guide iWave Systems Technologies Pvt Ltd Product Part Number Description Temperature iW G36S 2CG1 4E002G E008G BIB ZU2CG 1 MPSOC XCZU2CG 1SFVC784I 2GB PS DDR4 8GB E...

Page 88: ...REL0 2 Page 88 of 88 Zynq Ultrascale MPSoC SBC Hardware User Guide iWave Systems Technologies Pvt Ltd...

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