Intel® Server System M50FCP1UR System Integration and Service Guide
102
Post
Code
(Hex)
Upper Nibble
Lower Nibble
Description
8h
4h
2h
1h
8h
4h
2h
1h
A9
1
0
1
0
1
0
0
1
Program final IO SAD setting
AA
1
0
1
0
1
0
1
0
Protocol layer and other uncore settings
AB
1
0
1
0
1
0
1
1
Transition links to full speed operation
AE
1
0
1
0
1
1
1
0
Coherency settings
AF
1
0
1
0
1
1
1
1
KTI initialization done
Pre-EFI Initialization (PEI) Phase
10
0
0
0
1
0
0
0
0
PEI Core
11
0
0
0
1
0
0
0
1
CPU PEIM
15
0
0
0
1
0
1
0
1
Platform Type Init
19
0
0
0
1
1
0
0
1
Platform PEIM Init
Integrated I/O Progress Codes
E0
1
1
1
0
0
0
0
0
Integrated I/O Early Init Entry
E1
1
1
1
0
0
0
0
1
Integrated I/O Pre-link Training
E2
1
1
1
0
0
1
0
Integrated I/O EQ Programming
E3
1
1
1
0
0
0
1
1
Integrated I/O Link Training
E4
1
1
1
0
0
1
0
0
Internal Use
E5
1
1
1
0
0
1
0
1
Integrated I/O Early Init Exit
E6
1
1
1
0
0
1
1
0
Integrated I/O Late Init Entry
E7
1
1
1
0
0
1
1
1
Integrated I/O PCIe Ports Init
E8
1
1
1
0
1
0
0
0
Integrated I/O IOAPIC init
E9
1
1
1
0
1
0
0
1
Integrated I/O VTD Init
EA
1
1
1
0
1
0
1
0
Integrated I/O IOAT Init
EB
1
1
1
0
1
0
1
1
Integrated I/O DXF Init
EC
1
1
1
0
1
1
0
0
Integrated I/O NTB Init
ED
1
1
1
0
1
1
0
1
Integrated I/O Security Init
EE
1
1
1
0
1
1
1
0
Integrated I/O Late Init Exit
EF
1
1
1
0
1
1
1
1
Integrated I/O ready to boot
MRC Progress Codes – At this point the MRC Progress Code sequence is executed.
31
0
0
1
1
0
0
0
1
Memory Installed
32
0
0
1
1
0
0
1
0
CPU PEIM (CPU Init)
33
0
0
1
1
0
0
1
1
CPU PEIM (Cache Init)
34
0
0
1
1
0
1
0
0
CPU BSP Select
35
0
0
1
1
0
1
0
1
CPU AP Init
36
0
0
1
1
0
1
1
0
CPU SMM Init
4F
0
1
0
0
1
1
1
1
DXE IPL started
Memory Feature Progress Codes
C1
1
1
0
0
0
0
0
1
Memory POR check
C2
1
1
0
0
0
0
1
0
Internal Use
C3
1
1
0
0
0
0
1
1
Internal Use
C4
1
1
0
0
0
1
0
0
Internal Use
C5
1
1
0
0
0
1
0
1
Memory Early Init
C6
1
1
0
0
0
1
1
0
Display DIMM info in debug mode
C7
1
1
0
0
0
1
1
1
JEDEC Nvdimm training
C9
1
1
0
0
1
0
0
1
Setup SVL and Scrambling
CA
1
1
0
0
1
0
1
0
Internal Use
Summary of Contents for M50FCP1UR
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Page 121: ...Intel Server System M50FCP1UR System Integration and Service Guide 121 6 7 8 9 10...
Page 130: ...Intel Server System M50FCP1UR System Integration and Service Guide 130 1 2 3 4 5 ESD 6 1 2 3...
Page 131: ...Intel Server System M50FCP1UR System Integration and Service Guide 131 1 2 3 4 5...
