Intel M50FCP1UR, Manual

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Intel® Server System M50FCP1UR System Integration and Service Guide
101
Table 10. MRC Fatal Error Codes
Post Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
E8 1 1 1 0 1 0 0 0
No usable memory error
01h = No memory was detected from SPD read, or invalid config that
causes no operable memory.
02h = Memory DIMMs on all channels of all sockets are inactivated due
to hardware memtest error.
03h = No memory installed. All channels are inactivated.
E9 1 1 1 0 1 0 0 1
Memory is locked by Intel® TXT and is inaccessible
EA 1 1 1 0 1 0 1 0
DDR5 channel training error
01h = Error on read DQ/DQS (Data/Data Strobe) init
02h = Error on Receive Enable
03h = Error on Write Leveling
04h = Error on write DQ/DQS (Data/Data Strobe
EB 1 1 1 0 1 0 1 1
Memory test failure
01h = Software memtest failure.
02h = Hardware memtest failed.
ED 1 1 1 0 1 1 0 1
DIMM configuration population error
01h = Different DIMM types (RDIMM, LRDIMM) are detected installed in
the system.
02h = Violation of DIMM population rules.
03h = The 3rd DIMM slot cannot be populated when QR DIMMs are
installed.
04h = UDIMMs are not supported.
05h = Unsupported DIMM Voltage.
EF 1 1 1 0 1 1 1 1
Indicates a CLTT table structure error
D.2 BIOS POST Progress Codes
The following table provides a list of all POST progress codes.
Table 11. POST Progress Codes
Post
Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
Security (SEC) Phase
01 0 0 0 0 0 0 0 1 First POST code after CPU reset
02 0 0 0 0 0 0 1 0 Microcode load begin
03 0 0 0 0 0 0 1 1 CRAM initialization begins
04 0 0 0 0 0 1 0 0 PEI Cache When Inactivated
05 0 0 0 0 0 1 0 1 SEC Core At Power On Begin.
06 0 0 0 0 0 1 1 0 Early CPU initialization during SEC Phase.
UPI RC (Fully leverage without platform change)
A1 1 0 1 0 0 0 0 1 Collect info: SBSP, boot mode, reset type, etc.
A3 1 0 1 0 0 0 1 1 Setup minimum path between SBSP and other sockets
A6 1 0 1 0 0 1 1 0 Sync up with PBSPs
A7 1 0 1 0 0 1 1 1 Topology discovery and route calculation
A8 1 0 1 0 1 0 0 0 Program final route