Infineon Technologies XC161, User Manual

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XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-55 V2.2, 2004-01
GPT_X1, V2.0
14.3 Interfaces of the GPT Module
Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2
are connected to their environment in two basic ways (see
Figure 14-32 ):
• Internal connections interface the timers with on-chip resources such as clock
generation unit, interrupt controller, or other timers.
• External connections interface the timers with external resources via port pins.
Figure 14-32 GPT Module Interfaces
Port pins to be used for timer input signals must be switched to input, the respective
direction control bits must be cleared (DPx.y = 0).
Port pins to be used for timer output signals must be switched to output, the respective
direction control bits must be set (DPx.y = 1). The alternate timer output signal must be
selected for these pins via the respective alternate select registers (see
Chapter 7 ).
Interrupt nodes to be used for timer interrupt requests must be enabled and programmed
to a specific interrupt level.
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