Infineon Technologies XC161, User Manual

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XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-52 V2.2, 2004-01
GPT_X1, V2.0
External Count Clock Input
The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see
Figure 14-20 ). To ensure that a signal is recognized correctly, its current level (high or
low) must be held active for at least one complete sampling period, before changing. A
signal transition is recognized if two subsequent samples of the input signal represent
different levels. Therefore, a minimum of two basic clock periods are required for the
sampling of an external input signal. Thus, the maximum frequency of an input signal
must not be higher than half the basic clock.
Table 14-17 summarizes the resulting requirements for external GPT2 input signals.
These limitations are valid for all external input signals to GPT2, including the external
count signals in counter mode and the gate input signals in gated timer mode.
Table 14-17 GPT2 External Input Signal Limits
System Clock = 10 MHz Input
Frequ.
Factor
GPT2
Divider
BPS1 Input
Phase
Duration System Clock = 40 MHz
Max. Input
Frequency Min. Level
Hold Time Max. Input
Frequency Min. Level
Hold Time
2.5 MHz 200 ns f
GPT
/4 01
B
2
×
t
GPT
10.0 MHz 50 ns
1.25 MHz 400 ns
f
GPT
/8 00
B
4
×
t
GPT
5.0 MHz 100 ns
625.0 kHz 800 ns f
GPT
/16 11
B
8
×
t
GPT
2.5 MHz 200 ns
312.5 kHz 1.6
µ
s
f
GPT
/32 10
B
16
×
t
GPT
1.25 MHz 400 ns