XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
User’s Manual
22-20
V2.2, 2004-01
SDLM_X, V2.0
22.2.7.3
Read Operations
Read of the Receive FIFO in Normal Mode
Bit RxINCE in register BUFFCON has to be set in order to provide FIFO functionality.
Register RxCPU is incremented after each read operation from RxD00. The receive
buffer is read out by multiple read actions from RxD00. All other registers of the receive
buffer can always be directly accessed via their addresses without changing RxCPU.
Figure 22-14 Receive Operation in FIFO Mode
Start
RBC=1 ?
read RxD00
end
y
The CPU releases the receive
buffer by setting bit DONE.
This action resets RBC. If the
receive buffer on bus side
contains valid data (RBB=1
and RBC=0), the buffers are
swapped.
Bit RBC=1 indicates that
the receive buffer on bus
side contains valid data
and has not yet been
released by the CPU.
The CPU reads from RxD00,
which is the base address of
the FIFO. After each read
action, RxCPU is incremented
by HW.
If RxCPU (number of bytes
already read out) is lower than
RxCNT (total number of bytes in
the receive buffer), the CPU has
to continue reading RxD00.
n
RxCPU
<RxCNT ?
DONE:=1
y
n
