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Infineon Technologies XC161, User Manual

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Serial Data Link Module SDLM

User’s Manual

22-1

V2.2, 2004-01

SDLM_X, V2.0

22

Serial Data Link Module SDLM 

22.1

Overview

The Serial Data Link Module (SDLM) provides serial communication to a J1850 based
multiplexed bus via an external J1850 bus transceiver chip. The module is conform to
the SAE Class B J1850 specification and compatible to class 2 protocol.

General SDLM Features

•

Compliant to SAE Class B J1850 specification

•

GM class 2 protocol fully supported

•

Variable Pulse Width (VPW) format with 10.4 kBaud

•

High speed receive/transmit 4x mode with 41.6 kBaud

•

Digital noise filter

•

Power save mode and automatic walk-up upon bus activity

•

Single-byte headers or consolidated headers supported

•

CRC generation & check supported

•

Receive and transmit block mode supported

•

Transmission of two passive bits after arbitration loss on a byte boundary can be
enabled

Data Link Operation Features

•

11 bytes transmit buffer

•

Double-buffered 11 bytes receive buffer

•

Support of In-frame response (IFR) types 1, 2, 3 

•

Automatic IFR Transmission for IFR types 1, 2 for three byte consolidated headers

•

Advanced interrupt handling for RX, TX and error conditions

•

All interrupt sources can be separately enabled/disabled

•

8-byte transmit FIFO and 16-byte receive FIFO in block mode

Summary of Contents for XC161

Page 1: ...User s Manual V2 2 Jan 2004 Microcontrollers N e v e r s t o p t h i n k i n g XC161 Volume 2 of 2 Peripheral Units 16 Bit Single Chip Microcontroller with C166SV2 Core...

Page 2: ...r nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your...

Page 3: ...User s Manual V2 2 Jan 2004 Microcontrollers N e v e r s t o p t h i n k i n g XC161 Volume 2 of 2 Peripheral Units 16 Bit Single Chip Microcontroller with C166SV2 Core...

Page 4: ...he contents have not been changed otherwise except for the Pre release note on page 1 2 or obvious typographical errors 14 1ff Timer block description introduced 14 7 Phrasing improved 14 26 Figure co...

Page 5: ...Processing 2 6 1 2 1 4 Consistent and Optimized Instruction Formats 2 7 1 2 1 5 Programmable Multiple Priority Interrupt System 2 8 1 2 1 6 Interfaces to System Resources 2 9 1 2 2 On Chip System Res...

Page 6: ...rs 4 26 1 4 5 Use of General Purpose Registers 4 29 1 4 5 1 GPR Addressing Modes 4 31 1 4 5 2 Context Switching 4 33 1 4 6 Code Addressing 4 37 1 4 7 Data Addressing 4 39 1 4 7 1 Short Addressing Mode...

Page 7: ...em Control Functions 6 1 1 6 1 System Reset 6 2 1 6 1 1 Reset Sources and Phases 6 3 1 6 1 2 Status After Reset 6 6 1 6 1 3 Application Specific Initialization Routine 6 11 1 6 1 4 System Startup Conf...

Page 8: ...7 1 9 2 2 1 A Phase CS Change Phase 9 7 1 9 2 2 2 B Phase Address Setup ALE Phase 9 7 1 9 2 2 3 C Phase Delay Phase 9 7 1 9 2 2 4 D Phase Write Data Setup MUX Tristate Phase 9 7 1 9 2 2 5 E Phase RD W...

Page 9: ...tstrap Loader Mode 10 4 1 10 4 Choosing the Baudrate for the BSL 10 5 1 11 Debug System 11 1 1 11 1 Introduction 11 1 1 11 2 Debug Interface 11 2 1 11 3 OCDS Module 11 3 1 11 3 1 Debug Events 11 5 1 1...

Page 10: ...Analog Digital Converter 16 1 2 16 1 Mode Selection 16 3 2 16 1 1 Compatibility Mode 16 3 2 16 1 2 Enhanced Mode 16 5 2 16 2 ADC Operation 16 8 2 16 2 1 Fixed Channel Conversion Modes 16 11 2 16 2 2...

Page 11: ...nous Transmission 18 20 2 18 3 2 Synchronous Reception 18 20 2 18 3 3 Synchronous Timing 18 20 2 18 4 Baudrate Generation 18 22 2 18 4 1 Baudrate in Asynchronous Mode 18 22 2 18 4 2 Baudrate in Synchr...

Page 12: ...n 21 1 2 21 1 1 Overview 21 1 2 21 1 2 TwinCAN Control Shell 21 4 2 21 1 2 1 Initialization Processing 21 4 2 21 1 2 2 Interrupt Request Compressor 21 5 2 21 1 2 3 Global Control and Status Logic 21 6...

Page 13: ...3 XC161 Module Implementation Details 21 82 2 21 3 1 Interfaces of the TwinCAN Module 21 82 2 21 3 2 TwinCAN Module Related External Registers 21 83 2 21 3 2 1 System Registers 21 84 2 21 3 2 2 Port...

Page 14: ...Status Registers 22 29 2 22 4 1 Transmission Related Registers 22 39 2 22 4 2 Reception Related Registers 22 43 2 22 5 SDLM Module Register Table 22 50 2 22 6 XC161 Module Implementation Details 22 51...

Page 15: ...is fGPT 4 The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer These registers are listed in Section 14 1 6 fGPT 4 maximum resolution 3 independe...

Page 16: ...ated by the Output Toggle Latch T3OTL whose state may be output on the associated pin T3OUT alternate pin function The auxiliary timers T2 and T4 may additionally be concatenated with the core timer T...

Page 17: ...functions are located in the respective port modules Note The timing requirements for external input signals can be found in Section 14 1 5 Section 14 3 summarizes the module interface signals includ...

Page 18: ...w rw rw Field Bits Typ Description T3RDIR 15 rh Timer T3 Rotation Direction Flag 0 Timer T3 counts up 1 Timer T3 counts down T3CHDIR 14 rwh Timer T3 Count Direction Change Flag This bit is set each ti...

Page 19: ...5 3 rw Timer T3 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved Do not use this comb...

Page 20: ...e or by the external input pin TxEUD Timer Tx External Up Down Control Input These options are selected by bits TxUD and TxUDE in the respective control register TxCON When the up down control is prov...

Page 21: ...ed simultaneously In this case both signals to the auxiliary timers carry the same level and no edge will be detected Bit T3OE overflow underflow output enable in register T3CON enables the state of T...

Page 22: ...field T3M in register T3CON to 000B In timer mode T3 is clocked with the module s input clock fGPT divided by two programmable prescalers controlled by bitfields BPS1 and T3I in register T3CON Please...

Page 23: ...ociated pin T3IN must be configured as input that is the corresponding direction control bit must contain 0 Figure 14 5 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 010B the timer is enab...

Page 24: ...red as input the respective direction control bit DPx y must be 0 The maximum input frequency allowed in counter mode depends on the selected prescaler value To ensure that a transition of the count i...

Page 25: ...e sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal So T3 is modified automatically according to the speed and the direction...

Page 26: ...h pins T3IN and T3EUD must be configured as input i e the respective direction control bits must be 0 Bit T3UDE must be 1 to enable automatic external direction control The maximum count frequency all...

Page 27: ...binations Figure 14 9 and Figure 14 10 give examples of T3 s operation visualizing count signal generation and direction control They also show how input jitter is compensated which might occur if the...

Page 28: ...ly provides information on the sensor s current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods This is facilitated by an addition...

Page 29: ...ectively These registers can also be written to by the CPU for example to set the initial start value The individual configurations for timers T2 and T4 are determined by their bitaddressable control...

Page 30: ...e Mode is enabled 1 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled TxRC 9 rw Timer Tx Remote Control 0 Timer Tx is controlled by its own run bit TxR 1...

Page 31: ...it is set and the gate is active high or low as programmed Note If remote control is selected T3R will start stop timer T3 and the selected auxiliary timer s synchronously Count Direction Control The...

Page 32: ...dentical with the core timer s operation with very few exceptions Additionally some combined operating modes can be selected Timers T2 and T4 in Timer Mode Timer mode for an auxiliary timer Tx is sele...

Page 33: ...0 TxCON 3 selects the active level of the gate input Note A transition of the gate signal at line TxIN does not cause an interrupt request Figure 14 12 Block Diagram of an Auxiliary Timer in Gated Ti...

Page 34: ...iagram of an Auxiliary Timer in Counter Mode Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL v...

Page 35: ...imer Tx is selected by setting bitfield TxM in the respective register TxCON to 110B or 111B In incremental interface mode the two inputs associated with an auxiliary timer Tx TxIN TxEUD are used to i...

Page 36: ...nsition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL...

Page 37: ...gure 14 16 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the respective interrupt request flag T2IR or T4IR is...

Page 38: ...ible Pulse Width Modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3...

Page 39: ...both auxiliary timers should be avoided In such a case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4...

Page 40: ...re mode and must be cleared TxI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independently of its run flag T2R or T4R Figure 14 18 GPT1 Auxiliary Timer in Ca...

Page 41: ...field TxI in the respective timer s control register TxCON The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lower clock frequencies as can be seen from the follow...

Page 42: ...14 8 GPT1 Timer Parameters System Clock 10 MHz Overall Divider Factor System Clock 40 MHz Frequency Resolution Period Frequency Resolution Period 2 5 MHz 400 ns 26 21 ms 4 10 0 MHz 100 ns 6 55 ms 1 2...

Page 43: ...or external GPT1 input signals These limitations are valid for all external input signals to GPT1 including the external count signals in counter mode and incremental interface mode the gate input sig...

Page 44: ...respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers Note Please refer to the general Interrupt Control Regist...

Page 45: ...with the core timer T6 through T6OTL The Capture Reload register CAPREL can be used to capture the contents of timer T5 or to reload timer T6 A special mode facilitates the use of register CAPREL for...

Page 46: ...art of the GPT2 block The input and output lines of GPT2 are connected to pins of Ports P3 and P5 The control registers for the port functions are located in the respective port modules Note The timin...

Page 47: ...rw rwh rw rw rw rw rw Field Bits Typ Description T6SR 15 rw Timer 6 Reload Mode Enable 0 Reload from register CAPREL Disabled 1 Reload from register CAPREL Enabled T6CLR 14 rw Timer T6 Clear Enable Bi...

Page 48: ...timers core timer and auxiliary timer can be controlled by software The count direction can be altered by setting or clearing bit TxUD The count direction can be changed regardless of whether or not...

Page 49: ...ly In this case both signals to the auxiliary timers carry the same level and no edge will be detected Bit T6OE overflow underflow output enable in register T6CON enables the state of T6OTL to be moni...

Page 50: ...ing bitfield T6M in register T6CON to 000B In this mode T6 is clocked with the module s input clock fGPT divided by two programmable prescalers controlled by bitfields BPS2 and T6I in register T6CON P...

Page 51: ...the associated pin T6IN must be configured as input the corresponding direction control bit must contain 0 Figure 14 23 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M 010B the timer is enab...

Page 52: ...figured as input the respective direction control bit DPx y must be 0 The maximum input frequency allowed in counter mode depends on the selected prescaler value To ensure that a transition of the cou...

Page 53: ...control register T5CON Some bits in this register also control the function of the CAPREL register Note that functions which are present in all timers of block GPT2 are controlled in the same bit pos...

Page 54: ...rw Timer T3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines T3IN and or T3EUD T5RC 9 rw Timer T5 Remote Control 0 Timer T5 is controlled by its ow...

Page 55: ...ly 14 2 4 GPT2 Auxiliary Timer T5 Operating Modes The operation of the auxiliary timer in the basic operating modes is almost identical with the core timer s operation with very few exceptions Additio...

Page 56: ...the auxiliary timer can be controlled locally or remotely Timer T5 in Counter Mode Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 001B In counter mode th...

Page 57: ...he count input signal applied to T5IN is recognized correctly its level must be held high or low for a minimum number of module clock cycles before it changes This information can be found in Section...

Page 58: ...of T6OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit...

Page 59: ...control register T5CON set bitfield CI in register T5CON to a non zero value to select a trigger signal In capture mode the contents of the auxiliary timer T5 are latched into register CAPREL in resp...

Page 60: ...leared after the current timer T5 value has been latched into register CAPREL Note Bit T5SC only controls whether or not a capture is performed If T5SC is cleared the external input pin s can still be...

Page 61: ...inimum number of module clock cycles detailed in Section 14 2 6 GPT2 Capture Reload Register CAPREL in Reload Mode Reload mode for register CAPREL is selected by setting bit T6SR in control register T...

Page 62: ...This combined mode can be used to detect consecutive external events which may occur aperiodically but where a finer resolution that means more ticks within the time between two external events is re...

Page 63: ...to pin CAPIN Note The underflow signal of Timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibility to set compare events based on a...

Page 64: ...ck for each GPT2 timer is derived from the GPT2 basic clock by a programmable prescaler controlled by bitfield TxI in the respective timer s control register TxCON The count frequency fTx for a timer...

Page 65: ...8 256 512 1024 TxI 111B 256 512 1024 2048 1 Please note the non linear encoding of bitfield BPS2 Table 14 16 GPT2 Timer Parameters System Clock 10 MHz Overall Divider Factor System Clock 40 MHz Freque...

Page 66: ...f an external input signal Thus the maximum frequency of an input signal must not be higher than half the basic clock Table 14 17 summarizes the resulting requirements for external GPT2 input signals...

Page 67: ...E_Tx Timer x Count Register SFR FE4xH 2yH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Txvalue rwh Table 14 18 GPT1 Timer Register Locations Timer Register Physical Address 8 Bit Address T5...

Page 68: ...nterrupt vector T5INT T6INT or CRINT or trigger a PEC service if the respective interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register f...

Page 69: ...ut signals must be switched to input the respective direction control bits must be cleared DPx y 0 Port pins to be used for timer output signals must be switched to output the respective direction con...

Page 70: ...of a chain of 3 divider blocks a selectable 8 1 divider on off the reloadable 16 bit timer T14 the 32 bit RTC timer block accessible via RTC_RTCH and RTC_RTCL made of the reloadable 10 bit timer CNT0...

Page 71: ...s used to control the RTC s logic blocks and its bus interface To synchronize properly to the count clock the system clock must run at least four times faster than the count clock this means fSYS 4 fC...

Page 72: ...de are only meaningful if the system clock is not switched off of course Switching Clocking Modes The clocking mode of the RTC synchronous or asynchronous is selected via bit RTCCM in register SYSCON0...

Page 73: ...eviation causes an error of 1 cycle can be easily computed So the only action is to correct the count by 1 after each series of N cycles The correction may be made cyclically for instance within an in...

Page 74: ...zation software must ensure the proper RTC operating mode The RTC control register RTC_CON selects the basic operation of the RTC module RTC_CON Control Register ESFR F110H 88H Reset Value 8003H 15 14...

Page 75: ...Clock User s Manual 15 6 V2 2 2004 01 RTC_X8 V2 1 PRE 1 rw RTC Input Source Prescaler Enable 0 Prescaler disabled T14 clocked with fRTC 1 Prescaler enabled T14 clocked with fRTC 8 RUN 0 rw RTC Run Bi...

Page 76: ...overflows must be taken into account to avoid reading writing corrupted values Care must be taken when reading the timer s as this requires up to three read accesses to the different registers with an...

Page 77: ...lue Notes RTC_T14 F0D2H 69H 0000H 16 bit timer can be used as prescaler for the RTC block RTC_T14REL F0D0H 68H 0000H Timer T14 reload register RTC_RTCH RTC Timer High Register ESFR F0D6H 6BH Reset Val...

Page 78: ...stem reset but via software RTC_RELH RTC Reload High Register ESFR F0CEH 67H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REL3 REL2 rw rw RTC_RELL RTC Reload Low Register ESFR F0CCH 66H Res...

Page 79: ...optionally and indicates the current time and date This is possible because the RTC module is not affected by a system reset1 The resolution for this clock information is determined by the input clock...

Page 80: ...oad values and by enabling the appropriate interrupt request In this mode the other operating modes can be combined For example a reload value of T14REL F9C0H 216 1600 generates a T14 interrupt reques...

Page 81: ...ed together on this line see Figure 15 5 The interrupt handler can determine the source of an interrupt request via the specific request flags and must clear them after appropriate processing not clea...

Page 82: ...CNT 3IE CNT 2IR CNT 2IE CNT 1IR CNT 1IE CNT 0IR CNT 0IE T14 IR T14 IE rwh rw rwh rw rwh rw rwh rw rwh rw Field Bits Type Description CNTxIR x 3 0 9 7 5 3 rwh Section CNTx Interrupt Request Flag 0 No r...

Page 83: ...Read Mode start a conversion automatically when the previous result was read Channel Injection Mode start a conversion when a hardware trigger occurs can insert the conversion of a specific channel i...

Page 84: ...to the selected analog input and is charged or discharged to the voltage of the analog signal During the actual conversion phase the network is disconnected from the analog input and is repeatedly cha...

Page 85: ...ADC_CTR2 and ADC_CTR2IN are used Their bitfields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter 16 1 1 Compatibility Mode In compatibility...

Page 86: ...l which is to be converted ADC_CON1 ADC Control Register 1 SFR FFA6H D3H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICST SAM PLE CAL RES ADCTC ADSTC rw rh rh rw rw rw Field Bits Type Desc...

Page 87: ...ion Control 0 10 bit resolution default after reset 1 8 bit resolution ADCTC 11 6 rw ADC Conversion Time Control Defines the ADC basic conversion clock fBC fADC ADCTC 1 ADSTC 5 0 rw ADC Sample Time Co...

Page 88: ...Wait for Read Control ADBSY 8 rh Busy Flag 0 ADC is idle 1 A conversion is active ADST 7 rwh ADC Start Stop Control 0 Stop a running conversion 1 Start conversion s ADM 6 5 rw Mode Selection Control...

Page 89: ...7 6 5 4 3 2 1 0 RES ADCTC ADSTC rw rw rw ADC_CTR2IN Injection Control Register 2 ESFR F09EH 4FH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES ADCTC ADSTC r rw rw rw Field Bits Type Descr...

Page 90: ...ADST The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH The sampled level will then be held internally...

Page 91: ...en in the control registers Conversion Mode Selection ADM Bitfield ADM selects the conversion mode of the A D converter as listed in Table 16 1 While a conversion is in progress the mode selection fie...

Page 92: ...er ADC_DAT2 is loaded by the CPU to select the analog channel which is to be injected ADC_DAT ADC Result Register SFR FEA0H 50H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES rwh r...

Page 93: ...set and the channel specified in bitfield ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set In Single Conversion Mode the converter will automatical...

Page 94: ...version Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of th...

Page 95: ...tored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value th...

Page 96: ...is specified in bitfield CHNR of register ADC_DAT2 Note Bitfield CHNR in ADC_DAT2 is not modified by the A D converter but only the ADRES bitfield Since the channel number for an injected conversion i...

Page 97: ...al Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injection mode is enabled or not It is recommended to always...

Page 98: ...gled from 0 to 1 i e the bit must have been zero before being set Table 16 2 summarizes the ADC operation in the possible situations Table 16 2 Conversion Arbitration Conversion in Progress New Reques...

Page 99: ...e reference voltages as well as the supply voltages must be stable during the power up calibration During the calibration sequence a series of calibration cycles is executed where the step width for a...

Page 100: ...he general speed of the controller This allows adjusting the A D converter of the XC161 to the properties of the system Fast Conversion can be achieved by programming the respective times to their abs...

Page 101: ...de bit MD 1 the bitfields in register ADC_CTR2 are used for standard conversions Injected conversions use the bitfields in register ADC_CTR2IN Bitfield ADCTC conversion time control selects the basic...

Page 102: ...ndard conversion timing The timings refer to module clock cycles where tADC 1 fADC Assumptions fADC 40 MHz i e tADC 25 ns ADCTC 01B ADSTC 00B Basic clock fBC fADC 2 20 MHz i e tBC 50 ns Sample time tS...

Page 103: ...C will be set either if a conversion result overwrites a previous value in register ADC_DAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADC_DAT2 en...

Page 104: ...f the ADC are connected to the interrupt control block External Connections The analog input signals for the ADC are connected with Port 5 of the XC161 input only Two dedicated pins VAREF and VAGND pr...

Page 105: ...L CAPCOM1 Timer Reload Register T0IC T1IC CAPCOM1 Timer x Intr Ctrl Reg CC1 2_SEE CAPCOM Single Event En Reg CC1 2_SEM CAPCOM Single Event Mode Reg CC1 2_DRM CAPCOM Double Reg Mode Reg CC1 2_OUT CAPCO...

Page 106: ...ter may be allocated to either of the two timers Each capture compare register has one signal associated with it which serves as an input signal for the capture operation or as an output signal for th...

Page 107: ...teen 16 bit Capture Compare Registers Timer T1 T8 Reload Reg T1REL T8REL T0 T7 Input Control Mode Control Capture or Compare T1 T8 Input Control MCB05418 Reload Reg T0REL T7REL T0IRQ T7IRQ CCxIRQ CCxI...

Page 108: ...ith 32 compare registers The functions of the CAPCOM timers are controlled via the bit addressable control registers T01CON and T78CON The high byte of T01CON controls T1 the low byte of T01CON contro...

Page 109: ...00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T8R T8M T8I T7R T7M T7I rw rw rw rw rw rw Field Bits Type Description TxR 14 6 rw Timer Counter Tx Run Control 0 Timer Counter Tx is disabled 1 Timer Counter...

Page 110: ...ister TxREL The reload value determines the period PTx between two consecutive overflows of Tx as follows Staggered Mode 17 3 Non Staggered Mode 17 4 After a timer has been started by setting its run...

Page 111: ...ns 26 21 ms 010B 32 1 25 MHz 800 ns 52 43 ms 011B 64 625 kHz 1 6 s 104 86 ms 100B 128 312 5 kHz 3 2 s 209 72 ms 101B 256 156 25 kHz 6 4 s 419 43 ms 110B 512 78 125 kHz 12 8 s 838 86 ms 111B 1024 39 0...

Page 112: ...r a positive a negative or both a positive and a negative transition of the external signal at pin T0IN T7IN to trigger an increment of timer T0 T7 Please note that certain criteria must be met for th...

Page 113: ...IC is identical with the other interrupt control registers Note Please refer to the general Interrupt Control Register description for an explanation of the control fields CC1_T0IC CAPCOM T0 Intr Ctrl...

Page 114: ...its for mode selection and timer allocation for four capture comp registers Capture Compare Registers for the CAPCOM1 Unit CC15 CC0 CC1_M0 CAPCOM Mode Ctrl Reg 0 SFR FF52H A9H Reset Value 0000H 15 14...

Page 115: ...MOD22 ACC 21 MOD21 ACC 20 MOD20 rw rw rw rw rw rw rw rw CC2_M6 CAPCOM Mode Ctrl Reg 6 SFR FF26H 93H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC 27 MOD27 ACC 26 MOD26 ACC 25 MOD25 ACC 2...

Page 116: ...gger a channel injection on the XC161 s A D converter if enabled Table 17 2 Selection of Capture Modes and Compare Modes Mode MODy Selected Operating Mode Disabled 0 0 0 Disable Capture and Compare Mo...

Page 117: ...lected external signal transition occurs the selected timer s contents is latched into the capture compare register and the respective interrupt request line CCyIRQ is activated This can cause an inte...

Page 118: ...contents of a compare register In addition the comparator is only enabled in the clock cycle directly after the timer was incremented by hardware This is done to prevent repeated matches if the timer...

Page 119: ...e used as general purpose IO Note If compare mode 0 is programmed for one of the bank2 registers the double register compare mode may be enabled for this register see Chapter 17 5 5 17 5 2 Compare Mod...

Page 120: ...nversion of the output signal If the contents of register CCy are not changed this operation will take place each time the timer reaches the programmed compare value In Case 2 software reloads the com...

Page 121: ...ntil the timer reaches FFFAH in the following timer period to cause the desired compare match Reloading register CCy now with a value higher than the current timer contents will cause the next match w...

Page 122: ...When a match is detected in compare mode 3 for the first time within a count period of the allocated timer the interrupt request line CCyIRQ is activated and the associated output signal is set to 1 I...

Page 123: ...ctivates the associated interrupt request line TxIRQ If the contents of register CCy are not changed the port output will be set again during the following timer period and reset again when the timer...

Page 124: ...e match blocking are illustrated In Case 4 a new compare value is written to a compare register before the first match within the timer period One can see that of course the originally programmed comp...

Page 125: ...atment is required for this case see Case 3 Cases 2 4 and 5 show different options for the generation of a 0 duty cycle signal Case 2 shows an asynchronous reprogramming of the compare value equal to...

Page 126: ...f a CAPCOM unit are regarded as two banks of 8 registers each The lower eight registers form bank1 while the upper eight registers form bank2 For double register mode a bank1 register and a bank2 regi...

Page 127: ...r will be referred to as CCz while the corresponding bank1 register will be referred to as CCy CC1_DRM Double Reg Cmp Mode Reg SFR FF5AH ADH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR7...

Page 128: ...n CCyIO will be toggled only once but two separate compare interrupt requests will be generated Each of the two registers of a pair can be individually allocated to one of the two timers in the CAPCOM...

Page 129: ...ase the port latch must be selected for the respective pin The direct port latch option is disabled in non staggered mode or it can be disabled by setting bit PL in register CCx_IOC Register CCx_OUT i...

Page 130: ...nal and the current states of the Port and OUT latches For the output toggle function e g in compare mode 1 the state of the output latch is read inverted and then written back The associated output p...

Page 131: ...eliminates the need for software to react after the first compare match The complete operation can be set up before the event and no action is required after the event The hardware takes care of gene...

Page 132: ...t is cleared any compare operation is disabled To setup a new event this bit must first be set again CC1_SEE Single Event Enable Reg SFR FE2EH 17H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 133: ...alue are not switched at the same time but with a fixed time delay This operation helps to reduce noise and peak power consumption caused by simultaneous switching outputs In non staggered Mode a CAPC...

Page 134: ...e number of the register indicates the delay of the output signal in clock cycles the output of register CC7 is switched 7 cycles later than the one of register CC0 In the example the compare value fo...

Page 135: ...ation MCT05428 CC0 FFFE Timer contents FFFD Timer increments to FFFE Timer increments to FFFF Timer is reloaded with FFFC Timer overflow 1 CAPCOM Cycle 8 fCC Clock Cycles 1 CAPCOM Cycle 8 fCC Clock Cy...

Page 136: ...ck cycle Timer increment and the comparison of its new contents with the contents of the compare register takes place within one clock cycle The appropriate output signals are switched in the followin...

Page 137: ...peration MCT05429 CC0 FFFE Timer contents FFFD Timer increments to FFFE Timer increments to FFFF Timer is reloaded with FFFC Timer overflow 1 CAPCOM Cycle 1 fCC Clock Cycle 1 CAPCOM Cycle 1 fCC Clock...

Page 138: ...equests with the additional feature of recording the time at which the triggering event occurred Each of the capture compare registers has its own bitaddressable interrupt control register and its own...

Page 139: ...FR CC2_CC19IC F166H B3H ESFR CC1_CC4IC FF80H C0H SFR CC2_CC20IC F168H B4H ESFR CC1_CC5IC FF82H C1H SFR CC2_CC21IC F16AH B5H ESFR CC1_CC6IC FF84H C2H SFR CC2_CC22IC F16CH B6H ESFR CC1_CC7IC FF86H C3H S...

Page 140: ...nal input signal Thus the maximum frequency of an input signal must not be higher than half the module clock frequency in non staggered mode and a 1 16th of the module clock frequency in staggered mod...

Page 141: ...d as individual external interrupt inputs External Connections The capture compare signals of both CAPCOM units are connected with input output ports of the XC161 Depending on the selected direction t...

Page 142: ...2 CC2IO P6 3 CC3IO P6 4 CC4IO P6 5 CC5IO P6 6 CC6IO P6 7 CC7IO P3 0 T0IN P2 8 CC8IO P2 9 CC9IO P2 10 CC10IO P2 11 CC11IO P2 12 CC12IO P2 13 CC13IO P2 14 CC14IO P2 15 T7IN CC15IO CC15IRQ CC14IRQ CC13I...

Page 143: ...4 CC20IO P9 5 CC21IO P2 15 T7IN CC15IO P7 4 CC28IO P7 5 CC29IO P7 6 CC30IO CC31IRQ CC30IRQ CC29IRQ CC28IRQ CC27IRQ CC26IRQ CC25IRQ CC24IRQ CC23IRQ CC22IRQ CC21IRQ CC20IRQ CC19IRQ CC18IRQ CC17IRQ CC16...

Page 144: ...nsmission up to 115 2 kbit s maximum Half duplex 8 bit synchronous operating mode Baudrate from 5 Mbit s to 202 bit s 40 MHz module clock fASC Double buffered transmitter receiver Interrupt generation...

Page 145: ...ial Interface ASC User s Manual 18 2 V2 2 2004 01 ASC_X V2 0 Figure 18 1 ASC Interface Diagram ASC Module Kernel Module Bus Interface MCA05432 Port Control Product Interface Clock Control Address Deco...

Page 146: ...is generated by the microcontroller In Asynchronous Mode either 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is pro...

Page 147: ...y the selected operating mode Bits in the upper half of RBUF that are not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second cha...

Page 148: ...ng in Asynchronous Mode Figure 18 3 Asynchronous Mode of Serial Channel ASC Serial Port Control MCA05434 13 bit Reload Register 13 bit Baudrate Timer 16 fBRT fBR fDIV CON FDE MUX CON BRS Fractional Di...

Page 149: ...the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit PEN always OFF in 8 bit data mode The parity error flag PE will be set along...

Page 150: ...s 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in a multi processor system When the master processor wants to tran...

Page 151: ...r a 0 bit in the UART frame a high pulse is generated For a 1 bit in the UART frame no pulse is generated The high pulse starts in the middle of a bit cell and has a fixed width of 3 16 of the bit tim...

Page 152: ...stop bit is shifted out of the transmit shift register Note The transmitter output pin TxD must be configured for alternate data output 18 2 3 Transmit FIFO Operation The transmit FIFO TXFIFO provides...

Page 153: ...r of the ASC 3 bytes remain in the TXFIFO Therefore the value of TXFITL is reached and a transmit buffer interrupt will be generated at the beginning and a transmit interrupt at the end of the byte 3...

Page 154: ...FIFO is overwritten and the transmit FIFO filling level TXFFL is set to maximum The TXFIFO can be flushed or cleared by setting bit TXFFLU in register ASCx_TXFCON After this TXFIFO flush operation the...

Page 155: ...to 0 transition at the receive data input line Note The receiver input pin RxD must be configured for input Asynchronous reception is stopped by clearing bit REN A currently received frame is complet...

Page 156: ...FIFO still contains one byte RIR becomes again active after two more bytes byte 5 and 6 have been received RXFIFO filled again with 3 bytes Finally the FIFO is cleared after three read operation If th...

Page 157: ...ed or cleared by setting bit RXFFLU in register RXFCON After this RXFIFO flush operation the RXFIFO is empty and the receive FIFO filling level RXFFL is set to 0000B The RXFIFO is flushed automaticall...

Page 158: ...s always generated when the first byte is written into an empty RXFIFO RXFFL changes from 0000B to 0001B If the RXFIFO is filled with at least one byte the occurrence of further receive interrupts dep...

Page 159: ...itten into the transmit FIFO is overwritten and an overrun error interrupt EIR will be generated with bit OE set Note The Transmit FIFO Interrupt Trigger Level bitfield TXFITL is a don t care in Trans...

Page 160: ...l bits in the registers CON and ABCON as shown in Figure 18 11 The Synchronous Mode operation is not affected by these data path selection capabilities The input signal from RxD passes an inverter whi...

Page 161: ...in Asynchronous Modes Note In Echo Mode the transmit output signal is blocked by the Echo Mode output multiplexer Figure 18 11 shows that it is not possible to use an IrDA coded receiver input signal...

Page 162: ...e transmitted or received synchronous to a shift clock generated by the internal baudrate generator The shift clock is active only as long as data bits are transmitted or received Figure 18 12 Synchro...

Page 163: ...s to the clock that is output at TxD After the eighth bit has been shifted in the contents of the receive shift register are transferred to the receive data buffer RBUF the receive interrupt request l...

Page 164: ...eforms MCT05444 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 Shift Clock TxD Transmit Data RxD Receive Data RxD Continuous Transmit Timing 1 Byte 2 Byte 1 Byte 2 Byte Valid...

Page 165: ...eturns the contents of the timer BR_VALUE bits 15 13 return zero while writing to BG always updates the reload register bits 15 13 are insignificant An autoreload of the timer with the contents of the...

Page 166: ...C when using the fixed input clock divider ratios FDE 0 and the required reload value for a given baudrate can be determined by the following formulas BG represents the contents of the reload bitfield...

Page 167: ...ts the contents of the reload bitfield BR_VALUE taken as an unsigned 13 bit integer Note FDV represents the contents of the fractional divider register FD_VALUE taken as an unsigned 9 bit integer Tabl...

Page 168: ...ider FDE BRS BG FDV Formula 1 1 8191 1 511 0 Table 18 6 Typical Asynchronous Baudrates Using the Fractional Input Clock Divider fASC Desired Baudrate BG FDV Resulting Baudrate Deviation 40 MHz 115 2 k...

Page 169: ...chronous operation of serial channel ASC can be determined by the formulas as shown in Table 18 7 Note BG represents the contents of the reload bitfield BR_VALUE taken as an unsigned 13 bit integers T...

Page 170: ...ode of the RxD data input signal bits in register ASCx_CON and the value of register ASCx_BG in the baudrate timer are set to the appropriate values and the ASC can start immediately with the receptio...

Page 171: ...how the serial frames which are detected at least Note Some other two byte combinations will be defined too Figure 18 17 Two Byte Serial Frames with ASCII at MCT05448 1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0...

Page 172: ...rate s to be detected Programming of the baudrate timer prescaler setup of the clock rate of fDIV MCT05449 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 A 41H 7 Bit Even Parity T 54H 1 0 0 0 0 0 1 1 1 0 0 1 0 1...

Page 173: ...daption of fDIV to the required value Standard Baudrates For standard baudrate detection the baudrates as shown in Table 18 8 can be e g detected Therefore the output frequency fDIV of the baudrate ge...

Page 174: ...lid Br0 fDIV 48D Br1 fDIV 96D up to Br8 fDIV 9216D A requirement for detecting standard baudrates up to 230 400 kbit s is the fDIV minimum value of 11 0592 MHz With the value FD_VALUE the fractional d...

Page 175: ...the value of the fractional divider register FDV must be set in this example according to the formula with fDIV 9 6 MHz 18 3 Using this selection fDIV 9 6 MHz the detectable baudrates start at 200 kbi...

Page 176: ...In control register ASCx_CON the mode control bits M and the parity select bit ODD are overwritten Register ASCx_BG is loaded with the 13 bit reload value for the baudrate timer Note The autobaud det...

Page 177: ...e framing error detection enable bit FEN is set and any of the expected stop bits is not high the framing error flag FE is set indicating that the error interrupt request is due to a framing error Asy...

Page 178: ...has been transmitted RIR is activated when the received frame is moved to RBUF Note While the receive task is handled by a single interrupt handler the transmitter is serviced by two interrupt handle...

Page 179: ...ervice request control registers ASC0_ABIC ASC1_ABIC control the autobaud interrupts ASC0_TIC ASC1_TIC control the transmit interrupts ASC0_RIC ASC1_RIC control the receive interrupts ASC0_EIC ASC1_EI...

Page 180: ...TMEN is cleared TXFIFL defines when the interrupt is generated depending on the FIFO fill state Transmit Interrupt TIR The interrupt is generated after the last eight data bit of a transmission frame...

Page 181: ...O and therefore lost Read to empty FIFO EIR A read operation from the CPU to an empty receive FIFO generates this interrupt Transparent Read Operation RIR In Transparent Mode a receive interrupt is al...

Page 182: ...ol Register F1B8H DCH ESFR F1BCH DEH ASCx_ABSTAT Autobaud Status Register F0B8H 5CH ESFR F0BCH 5EH ASCx_BG Baudrate Timer Reload Register FEB4H 5AH SFR FEBCH 5EH ASCx_FDV Fractional Divider Register F...

Page 183: ...rw Baudrate Generator Run Control Bit 0 Baudrate generator disabled ASC inactive 1 Baudrate generator enabled Note BR_VALUE should only be written if R 0 LB 14 rw Loopback Mode Enabled 0 Loopback Mod...

Page 184: ...rity Error Flag Set by hardware on a parity error PEN 1 Must be cleared by software OEN 7 rw Overrun Check Enable 0 Ignore overrun errors 1 Check overrun errors FEN 6 rw Framing Check Enable Asynchron...

Page 185: ...nchronous operation 011 7 bit data and parity for asynchronous operation 100 9 bit data for asynchronous operation 101 8 bit data and wake up bit for asynchronous operation 110 Reserved Do not use thi...

Page 186: ...is also used for reference clock generation of the autobaud detection unit ASCx_FDV Fractional Divider Register SFR Table 18 13 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FD_VALUE rw Fie...

Page 187: ...mode ASCx_PMW IrDA Pulse Mode Width Reg SFR Table 18 13 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRP W PW_VALUE rw rw Field Bits Type Description IRPW 8 rw IrDA Pulse Width Selection 0...

Page 188: ...and Synchronous Mode ASCx_TBUF Transmit Buffer Register SFR Table 18 13 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TD_VALUE rw Field Bits Type Description TD_VALUE 8 0 rw Transmit Data R...

Page 189: ...R Table 18 13 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RD_VALUE rw Field Bits Type Description RD_VALUE 8 0 rw Receive Data Register Value RBUF contains the received data bits and depen...

Page 190: ...nverter Enable 0 Receive inverter disabled 1 Receive inverter enabled TXINV 10 rw Transmit Inverter Enable 0 Transmit inverter disabled 1 Transmit inverter enabled ABEM 9 8 rw Autobaud Echo Mode Enabl...

Page 191: ...affected during autobaud detection 1 CON REN is cleared receiver disabled when ABEN and AUREN are set together CON REN is set receiver enabled after a successful Autobaud Detection with the stop bit...

Page 192: ...character a A t or T has been detected 1 The autobaud detection unit waits for the first a or A Bit is cleared when either FCSDET or FCCDET is set a or A detected Bit can be also cleared by software D...

Page 193: ...irst Character with Capital Letter Detected 0 No capital A character detected 1 Capital A character detected Bit is cleared by hardware when ABEN is set or if FCSDET or SCSDET or SCCDET is set Bit can...

Page 194: ...ted after the reception of a byte when the filling level of the receive FIFO is equal to or greater than RXFITL 0000 Reserved Do not use this combination 0001 Interrupt trigger level is set to one 001...

Page 195: ...e the RXFIFO should be flushed before data is received RXFFLU 1 rw Receive FIFO Flush 0 No operation 1 Receive FIFO is flushed Note Setting RXFFLU clears bitfield RXFFL in register FSTAT RXFFLU is alw...

Page 196: ...rated after the transfer of a byte when the filling level of the transmit FIFO is equal to or lower than TXFITL 0000 Reserved Do not use this combination 0001 Interrupt trigger level is set to one 001...

Page 197: ...FLU 1 rw Transmit FIFO Flush 0 No operation 1 Transmit FIFO is flushed Note Setting TXFFLU clears bitfield TXFFL in register ASCx_FSTAT TXFFLU is always read as 0 TXFEN 0 rw Transmit FIFO Enable 0 Tra...

Page 198: ...IFO Filling Level 0000 Transmit FIFO is filled with zero bytes 0001 Transmit FIFO is filled with one byte 0111 Transmit FIFO is filled with seven bytes 1000 Transmit FIFO is filled with eight bytes No...

Page 199: ...lines of each module are connected to the Interrupt Control Block Clock control and emulation control of the SSC Module is handled by the System Control Unit SCU Figure 18 21 ASC0 Module Interfaces Fi...

Page 200: ...the direction of the RxD pin is not automatically set by the ASC modules it must be switched by software via the corresponding bit in register DP3 depending on the selected mode receive or transmit da...

Page 201: ...s and Functions Master and Slave Mode operation Full duplex or half duplex operation Flexible data format Programmable number of data bits 2 to 16 bits Programmable shift direction LSB or MSB shift fi...

Page 202: ...his peripheral including the port pins which may be used for alternate input output functions and including their direction control bits Figure 19 1 SFRs Associated with the SSC Unit MCA05454 P1H DP1H...

Page 203: ...ng SSC disabled by SSCx_CON EN 0 it provides access to a set of control bits During operation SSC enabled by SSCx_CON EN 1 it provides access to a set of status flags In the following the layout of re...

Page 204: ...rw Master Select 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK AREN 12 rw Automatic Reset Enable 0 No additional action upon a baudrat...

Page 205: ...g edge HB 4 rw Heading Control 0 Transmit Receive LSB First 1 Transmit Receive MSB First BM 3 0 rw Data Width Selection 0000 Reserved Do not use this combination 0001 Transfer Data Width is 2 bits Tra...

Page 206: ...eration Receiver Buffer Register The SSC Receive Buffer Register SSCx_RB see Table 19 2 contains the receive data value Unselected bits of SSCx_RB will be not valid and should be ignored The received...

Page 207: ...o 16 bits A transfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading edge or the trailing edge of the shift clock si...

Page 208: ...us their SCLK pin must be switched to input mode The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register inputs The...

Page 209: ...ster is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST...

Page 210: ...a with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the re...

Page 211: ...arbitrary stations Similar to Full Duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non transmitting de...

Page 212: ...er transfer It is just a matter of software how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus for instance N...

Page 213: ...as below calculate either the resulting baudrate for a given reload value or the required reload value for a given baudrate 19 1 BR represents the contents of the reload register taken as unsigned 16...

Page 214: ...ing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requ...

Page 215: ...ed when a transfer was initiated by the master SCLK gets active but the transmit buffer SSCx_TB of the slave was not updated since the last transfer This condition sets the error flag TE and when enab...

Page 216: ...Bit 16 Bit 8 Bit SSCx_CON Control Register FFB2H D9H SFR FF5EH AFH SSCx_BR Baudrate Timer Reload Register F0B4H 5AH ESFR F05EH 2FH SSCx_TB Transmit Buffer Register F0B0H 58H ESFR F05AH 2DH SSCx_RB Re...

Page 217: ...19 3 SSC0 SSC1 IO Selection and Setup Module Mode Port Lines Alternate Select Register Direction and Port Output Register IO SSC0 Master P3 8 MRST0 ALTSEL0P3 P8 1 DP3 P8 0 Input P3 9 MTSR0 ALTSEL0P3 P...

Page 218: ...ee interrupt request lines of each module are connected to the Interrupt Control Block Clock control and emulation control of the SSC Module is handled by the System Control Unit SCU Figure 19 8 SSC0...

Page 219: ...ions and provides the clock signal Slave mode where an external master controls the bus transactions and provides the clock signal Multimaster mode where several masters can be connected to the bus i...

Page 220: ...ule and provides a number of status signals and flags reflecting the conditions of the module to the software To operate in an IIC Bus system it is not only necessary for a station to be able to drive...

Page 221: ...evices For this purpose the respective pin drivers must be switched to open drain mode Figure 20 2 IIC Bus Configuration Example In an IIC Bus system a station may be able to play different roles Mast...

Page 222: ...3 SFRs Associated with the IIC Bus Module P9 DP9 ODP9 DIC PEIC CON CFG RTBL RTBH System Registers Interrupt Registers Control Status Reg Data Registers ADR ST ALTSEL0P9 ALTSEL1P9 SYSCON3 OPSEN MCA054...

Page 223: ...P 9 rwh Master Stop Control 0 No action 1 Setting bit STP generates a stop condition after the next transmission Bit BUM is cleared Note STP is automatically cleared by a stop condition IGE 8 rw Ignor...

Page 224: ...usy BB 1 generates an arbitration lost situation In this case BUM is cleared and bit AL is set BUM cannot be set in slave mode MOD 3 2 rw Basic Operating Mode 00 IIC module is disabled and initialized...

Page 225: ...tes 100 4 bytes 1xx Reserved IRQE 7 rwh End of Data Transmission Interrupt Req Flag 0 No interrupt request pending 1 An End Of Data Transmission interrupt request is pending See Section 20 4 for detai...

Page 226: ...s in Master mode 1 The IIC Bus Module has been addressed as a slave own slave address or general address 00H was received AL 1 rwh Arbitration Lost Flag Bit AL is set when the IIC Bus Module has tried...

Page 227: ...rw Baudrate Generator Mode Control 0 Mode 0 Reciprocal Divider 1 Mode 1 Fractional Divider PREDIV 14 13 rw Pre Divider for Baudrate Generation 00 Pre divider is disabled 01 Pre divider factor is 8 10...

Page 228: ...P 15 8 rw Baudrate Prescaler Value Determines the baudrate for the IIC Bus module together with bit ADR BRPMOD and bitfield ADR PREDIV SCLENx x 2 0 6 5 4 rw Enable Bit for SCLx Clock Line These bits d...

Page 229: ...eive Transmit Buffer High XSFR E60AH Reset Value 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTB3 RTB2 rwh rwh IIC_RTBL Receive Transmit Buffer Low XSFR E608H Reset Value 0000H 15 14 13 12 1...

Page 230: ...BUM in register CON This generates a start condition on the bus the busy bit BB is set and the transmission of the buffer contents begins To start a new transfer or to change the transfer direction t...

Page 231: ...witches to slave mode to receive the address information At the end of the address phase hardware automatically compares the received address with the own station address stored in register ADR If the...

Page 232: ...Buffer The IIC Bus Module has a transmit receive buffer which can be set to a depth of one to four bytes Access to this buffer is performed via the two registers RTBL and RTBH each of these represent...

Page 233: ...mode 0 which is compatible with previous implementations of the IIC Bus module High baudrates may be configured precisely in mode 1 Figure 20 4 IIC Bus Module Baudrate Generator Reciprocal Divider Mo...

Page 234: ...module s registers should only be performed after appropriate interrupt requests are generated by the module indicating a pause in or the termination of ongoing transfers During initialization mode M...

Page 235: ...revent further transactions on the bus The clock line is released again when all three flags are set to 0 Then further transactions can take place on the IIC bus This operation can also be used to con...

Page 236: ...as lost arbitration Additionally the arbitration lost flag AL is set In Multi Master and in Slave Mode this request is activated when either the general call address or the device s own address has be...

Page 237: ...drain mode no upper transistor The high level on these lines are held via external pull up devices approx 10 k for operation at 100 kbit s 2 k for operation at 400 kbit s All pins of the XC161 that ar...

Page 238: ...Bus Module deactivates output lines by setting the line to high level which results in a passive level at the open drain output Table 20 3 IIC IO Selection and Setup Port Lines Alternate Select Regis...

Page 239: ...e connected to the Interrupt Control Block Please note that two of the thee possible interrupt sources in the IIC Bus Module or ORed together onto the request line IIC_DIRQ see Section 20 4 Clock cont...

Page 240: ...Bus operation Figure 20 8 IIC Bus Characteristics SCL SDA Data Stable SCL SDA Start Stop SCL SDA Transmitter SDA Receiver 1st 2nd 8th 9th A6 A5 A4 A0 R W Start ACK Bit Normal Data Transfer Start and...

Page 241: ...32 message objects can be individually assigned to one of the two CAN nodes Gateway functionality allows automatic data exchange between two separate CAN bus systems which reduces CPU load and improv...

Page 242: ...and B to 8 interrupt nodes A message buffer unit containing the message buffers the FIFO buffer management the gateway control logic and a message based interrupt request generation unit The message...

Page 243: ...ter According the contents in both timers the CAN controller is set into an error active error passive or bus off state The interrupt request generation unit signals globally the successful end of a m...

Page 244: ...ct registers hold their current values except the error counters Resetting bit INIT to 0 without being in the bus off state starts the synchronization sequence connection to the CAN bus which has to m...

Page 245: ...ncrease flexibility in interrupt processing Each of the 8 CAN interrupt nodes can trigger an independent interrupt routine with its own interrupt vector and its own priority Figure 21 3 Interrupt Node...

Page 246: ...e objects Flag RXIPNDn is set by hardware if the corresponding message object has correctly received a data or remote frame and the correlated interrupt request generation has been enabled by RXIEn 10...

Page 247: ...mote frames are answered by the corresponding data frame nor data frames can be transmitted by setting TXRQ if CAN analyzer mode is enabled Receive interrupts are generated if enabled for all correctl...

Page 248: ...e associated CAN bus CAN frame counting is performed by a 16 bit counter which is controlled by register AFCR BFCR Bitfield CFCMD defines the operation mode and the trigger event incrementing the fram...

Page 249: ...ropagation delay quantities rounded up to a multiple of tq The phase buffer segments 1 and 2 Tb1 Tb2 before and after the signal sample point are used to compensate a mismatch between transmitter and...

Page 250: ...dominant bus level If the hard synchronization is enabled at the start of frame the bit time is restarted at the synchronization segment Otherwise the resynchronization jump width TSJW defines the max...

Page 251: ...d data frame handling interrupt generation and status processing 21 1 3 4 Error Handling Logic The error handling logic is responsible for the fault confinement of the CAN device Its two counters the...

Page 252: ...bitfield TRINP in control register AGINP BGINP An error is reported by a last error code interrupt request if activated by LECIE 1 in the ACR BCR register The corresponding interrupt node pointer is d...

Page 253: ...in the associated message control register MSGCTRn are set to 10 The associated interrupt node pointers are defined by bitfields RXINP and TXINP in message configuration register MSGCFGn 21 1 3 7 Inte...

Page 254: ...sources If a mask bit is reset the corresponding interrupt source is not taken into account for the generation of the INTID value Figure 21 8 INTID Mask for Message Interrupt Request Sources MCA05477...

Page 255: ...ated message control register bit MSGVAL When a message object is initialized by the CPU bitfield MSGVAL in message control register MSGCTRn should be reset inhibiting a read or write access of the CA...

Page 256: ...me reception a matching identifier length declaration XTD 1 marks extended 29 bit identifiers XTD 0 indicates standard 11 bit identifiers The result of the compare operation is bit by bit ANDED with t...

Page 257: ...rates If a data frame with matchingidentifier is received If a remote frame with matching identifier is received Receive Object receives data frames transmits remote frames control bit DIR 0 a remote...

Page 258: ...ansmit message object if some MSGAMRn mask register bits have been set to 0 As long as bitfield MSGVAL in register MSGCTRn is set to 10 the reception of a remote frame with matching identifier automat...

Page 259: ...the selected message object s data registers is copied to the bitstream processor Bitfields RMTPND and TXRQ are automatically reset when the message object has been successfully transmitted The captu...

Page 260: ...Direction 1 Transmit by the CAN Controller Node Hardware MCA05481 Matching Remote Frame Received NEWDAT 01 Copy Message to Bitstream Processor Send Message Transmission Successful no yes TXRQ 10 CPUU...

Page 261: ...f the previously stored message and signals a data loss by setting bitfield MSGLST In any case bitfield NEWDAT is automatically set to 10 reporting an update of the data register by the CAN controller...

Page 262: ...AN Controller Node Hardware MCA05482 Matching Data Frame Received Load Identifier and Control Bits into Bitstream Processor Send Remote Frame Transmission Successful no yes TXRQ 10 CPUUPD 01 no Bus Id...

Page 263: ...by a data frame based on the contents of the corresponding message object This behavior may lead to multiple generation and transmission of identical data frames according to the number of accepted r...

Page 264: ...ts as individual buffer storage building a circular buffer used as message FIFO Figure 21 13 FIFO Buffer Control Structure The number of base and slave message objects combined to a buffer has to be a...

Page 265: ...ects have to be set up with the message number of the base object The CANPTR of the base object addresses the next FIFO element to be accessed for information transfer and its value can be calculated...

Page 266: ...ed with receive objects the first accepted message is stored in the base message object number n the second message is written to buffer element n 1 and so on The number of the element used to store t...

Page 267: ...e case that the MSGVAL bitfields are set to 10 for the FIFO base object and 01 for the currently addressed FIFO slave object the data will not be delivered to the slave object whereas the bitfield CAN...

Page 268: ...change between both CAN nodes can be handled by coupling two message objects normal gateway mode or by sharing one common message object shared gateway mode In the following paragraphs the gateway sid...

Page 269: ...ociated to the source CAN bus via bit NODE Register MSGFGCR s should be initialized according the following enumeration Bitfield MMC s has to be set to 100 indicating a normal mode gateway for incomin...

Page 270: ...message object In this case data frames received on the source side can be automatically emitted on the destination side if enabled by the respective control bits CPUUPD d and GDFS s Remote frames re...

Page 271: ...the destination node are not transferred to the source side but can be directly answered by the destination message object For this purpose control bitfields TXRQ d and RMTPND d are set to 10 which im...

Page 272: ...bus if CPUUPD d is reset When bit SRREN d is set to 1 a remote frame received on the destination side is transferred via the gateway and transmitted again by the CAN source node controller A transmit...

Page 273: ...O element is set after reception of a data frame copied from the source side The base message object is indicated by ba the slave message objects by sl The number of base and slave message objects com...

Page 274: ...software routine operating on the FIFO buffered gateway configuration for data frame transfers The elements of the FIFO buffer on the destination side should be configured as transmit message objects...

Page 275: ...ating the transmission of a remote frame on the source side Figure 21 20 Remote Frame Transfer in Normal Gateway Mode with a 2 stage FIFO on the Destination Side FIFO CANPTR sl MMC sl 011 Node d MCA05...

Page 276: ...NODE is cleared CAN node A is used as source transferring data frames to destination node B If NODE is set to 1 CAN node B operates as data source A bidirectional gateway is achieved by using a secon...

Page 277: ...4 2 a data source connected with CAN node A transmits a data frame upon a matching remote frame which has been triggered by a matching remote frame received by CAN node B The respective data frame has...

Page 278: ...ate bubble Then the shared gateway message object emits the corresponding remote frame without any CPU interaction state transition 6 to the lower left state bubble The gateway message object remains...

Page 279: ...changed Identifier received unchanged unchanged received if RMM 1 DLC received unchanged unchanged received if RMM 1 TXRQ set reset reset set RMTPND reset reset reset set NEWDAT set reset reset reset...

Page 280: ...d frame counter overflow interrupt request with one of the eight common interrupt nodes The contents of the INTID mask register AIMR0 4 and BIMR0 4 decides which interrupt sources may be reported by t...

Page 281: ...cated by the CPU via setting NEWDAT to 10 Afterwards bit CPUUPD must be reset to 01 if an automatic message handling is requested In this case the data transmission is started when flag TXRQ in regist...

Page 282: ...date Message yes no no TXRQ 10 CPUUPD 01 MSGVAL 01 INTPND 01 RMTPND 01 TXRQ 01 NEWDAT 01 DIR 1 transmit object Identifier application specific XTD application specific TXIE application specific RXIE a...

Page 283: ...me Transmission no no TXRQ 10 MSGVAL 01 INTPND 01 RMTPND 01 TXRQ 01 NEWDAT 01 DIR 0 receive object MSGLST 01 TXIE application specific RXIE application specific Identifier application specific XTD app...

Page 284: ...e transceiver The transmit signals are combined together and are connected to the internal receive signals as shown in Figure 21 25 The receive input pins are not taken into account in loop back mode...

Page 285: ...y bit STT in register MSGFGCRn If the single transmission try functionality is enabled the transmit request flag TXRQ is reset immediately after the transmission of a frame related to this message obj...

Page 286: ...ed see last column of Table 21 6 if no frames without data data frames with DLC 0 or remote frames are transferred over the CAN bus This is possible because internal operations can be executed while t...

Page 287: ...Reg Receive Interrupt Pending Register ACR ASR AIR ABTR AGINP AFCR AIMR0 AIMR4 AECNT MSGDRn0 MSGARn MSGCTRn MSGFGCRn RXIPND AIR ABTR AGINP AFCR AIMR0 AIMR4 AECNT BCR BSR CAN Node B Registers BIR BBTR...

Page 288: ...Counter Reg INTID Mask 4 Reg 1CH INTID Mask 0 Reg 18H Frame Counter Reg 14H Global INP Reg 10H Bit Timing Reg 0CH Interrupt Pending Reg 08H Status Reg 04H Control Reg 00H 20H Error Counter Reg INTID...

Page 289: ...he CAN bus After a synchronization procedure1 the node takes part in CAN communication 1 After setting bit INIT the CAN node stops all CAN bus activities and all registers can be initialized without a...

Page 290: ...should be written with 0 1 After resetting bit INIT by software without being in the bus off state e g after power on a sequence of 11 consecutive recessive bits 11 1 on the bus has to be monitored be...

Page 291: ...t Error Code Bitfield LEC indicates if the latest CAN message transfer has been correct No Error or it indicates the type of error which has been detected The error conditions are detailed in Table 21...

Page 292: ...re this is not allowed Form Error A fixed format part of a received frame has the wrong format Ack Error The transmitted message was not acknowledged by another node Bit1 Error During a message transm...

Page 293: ...egister Reset Value 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 INTID r rwh Field Bits Type Description INTID 7 0 rwh Interrupt Identifier 00H No interrupt is pending 01H LEC EI TXOK or RXOK in...

Page 294: ...0H BECNTL Node B Error Counter Register Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 LE INC LE TD EWRNLVL r rh rh rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEC REC rwh rwh Field Bits T...

Page 295: ...sage REC has been incremented 1 The last error occurred while the corresponding CAN node was transmitting a message TEC has been incremented An error during message reception is indicated without rega...

Page 296: ...10 9 8 7 6 5 4 3 2 1 0 0 LBM r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIV 8X TSEG2 TSEG1 SJW BRP rw rw rw rw rw Field Bits Type Description BRP 5 0 Low rw Baudrate Prescaler One bit time quantum cor...

Page 297: ...nt a user defined delay and compensate a mismatch between transmitter and receiver clock phase Valid values for TSEG2 are 1 7 DIV8X 15 Low rw Division of Module Clock fCAN by 8 0 The baudrate prescale...

Page 298: ...Node B Frame Counter Register High Reset Value 0000H BFCRL Node B Frame Counter Register Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CFC OV CFC IE 0 CFCMD r rwh rw r rw 15 14 13 12 1...

Page 299: ...transmitted by the node 01XXB The CFC is incremented each time a frame was transmitted correctly by the node 1XXXB Time Stamp 1000B The CFC is incremented with the beginning of a new bit time The valu...

Page 300: ...it CFCMD 0 enables or disables the counting of foreign frames A foreign frame is a correct frame on the bus which has not been transmitted received by the node itself Bit CFCMD 1 enables or disables t...

Page 301: ...by EIE 1 000B CAN interrupt node 0 is selected 111B CAN interrupt node 7 is selected LECINP 6 4 rw Last Error Code Interrupt Node Pointer Number of interrupt node reporting the last error interrupt re...

Page 302: ...D value AIMRH0 Node A INTID Mask Register 0 High Reset Value 0000H AIMRL0 Node A INTID Mask Register 0 Low Reset Value 0000H BIMRH0 Node B INTID Mask Register 0 High Reset Value 0000H BIMRL0 Node B IN...

Page 303: ...2 0 rw Last Error Interrupt INTID Mask Control 0 The last error interrupt source is ignored for the generation of the INTID value 1 The last error interrupt source is taken into account for the genera...

Page 304: ...ge Data Register 0 contains the data bytes 0 to 3 of message object n MSGDRHn0 n 31 0 Message Object n Data Register 0 High Reset Value 0000H MSGDRLn0 n 31 0 Message Object n Data Register 0 Low Reset...

Page 305: ...SGDRLn4 n 31 0 Message Object n Data Register 4 Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA7 DATA6 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA5 DATA4 rwh rwh Field Bits Typ...

Page 306: ...n 31 0 Message Object n Arbitration Register Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID 28 16 r rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID 15 0 rwh Field Bits Type Description...

Page 307: ...set Value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 AM 28 16 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AM 15 0 rw Field Bits Type Description AM 15 0 AM 28 16 15 0 Low 12 0 High rw Message Accept...

Page 308: ...ription INTPND 1 0 Low rwh Message Object Interrupt Pending INTPND is generated by an OR operation between the RXIPNDn and TXIPNDn flags if enabled by TXIE or RXIE INTPND must be reset by software Res...

Page 309: ...Indicates that the corresponding message object can not be transmitted now The software sets this bit in order to inhibit the transmission of a message that is currently updated by the CPU or to contr...

Page 310: ...r after receiving a data frame with matching identifier It has to be reset by software When the CAN controller writes new data into the message object unused message bytes will be overwritten with non...

Page 311: ...SGVAL to 10 This avoids unintentional modification while the message object is still active by explicitly defining a timing instant for the update Bits XTD NODE or DIR can be written while MSGVAL is 0...

Page 312: ...e B XTD 2 Low rw Message Object Extended Identifier 0 This message object uses a standard 11 bit identifier 1 This message object uses an extended 29 bit identifier DIR 3 Low rwh Message Object Direct...

Page 313: ...is selected TXINP 6 4 High rw Transmit Interrupt Node Pointer Bitfield TXINP determines which interrupt node is triggered by a message object transmit event if bitfield TXIE in register MSGCTRn is set...

Page 314: ...ty while odd numbered message objects are restricted to slave functionality In gateway mode FSIZE determines the length of the FIFO on the destination side 00000B message object n is part of a 1 stage...

Page 315: ...ssage object n itself to generate a data frame or in the message object pointed to by CANPTRn in order to generate a remote frame on the source bus 0 A remote on the source bus will not be generated a...

Page 316: ...copied to the transmitting message object Bitfield IDC is restricted to message objects configured in normal gateway mode DLCC 11 Low rw Data Length Code Copy DLCC controls the handling of the data l...

Page 317: ...ame DIR 1 or a remote frame DIR 0 from the currently addressed message object The CANPTR is left unchanged after any reception Bitfield FD is not correlated with bit DIR SDT 14 Low rw Single Data Tran...

Page 318: ...e object is configured for normal gateway mode MMC 100 CANPTR contains the number of the message object used as gateway destination object Message object is configured as gateway destination object wi...

Page 319: ...ng MSGVAL to 10 Changes of bitfield CANPTR for receive objects are immediately taken into account MMC 10 8 High rw Message Object Mode Control Bitfield MMC controls the functionality of message object...

Page 320: ...errupt Pending Register Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXIPNDn n 31 16 rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXIPNDn n 15 0 rh Field Bits Type Description RXIPNDn n 15...

Page 321: ...ster Low Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXIPNDn n 31 16 rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXIPNDn n 15 0 rh Field Bits Type Description TXIPNDn n 15 0 TXIPND n 31 16 n...

Page 322: ...by bitfield RISA for node A and bitfield RISB for node B in the PISEL register The output transmit pins are defined by the corresponding ALTSEL registers of Port 4 Port 7 or Port 9 The TwinCAN has ei...

Page 323: ...gisters Figure 21 29 shows the module related external registers which are required for programming the TwinCAN module Figure 21 29 TwinCAN Implementation Specific Registers MCA05499 ALTSEL0P4 DP4 Por...

Page 324: ...0 rw Receive Input Selection for Node A Bitfield RISA defines the input pin for the TwinCAN receive line RXDCA for node A 000 The input pin for RXDCA is P4 5 001 The input pin for RXDCA is P4 7 010 T...

Page 325: ...6 0 r rw rw r Field Bit Type Description ALTSEL0 P4 y 6 7 rw P4 Alternate Select Register 0 bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is...

Page 326: ...r Field Bit Type Description ALTSEL0 P7 y 7 5 rw P7 Alternate Select Register 0 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected a...

Page 327: ...ect Register 0 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is selected as alternate function ALTSEL1P9 P9 Alternate Select Register 1 Rese...

Page 328: ...ed bits are not related to TwinCAN operation DP9 P9 Direction Ctrl Register Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 P0 r rw rw rw rw rw rw Field Bit Type Description D...

Page 329: ...Control Register IO TwinCAN Node A P4 5 RxDCA CAN_PISEL 2 0 000 DP4 P5 0 Input P4 6 TxDCA ALTSEL0P4 P6 1 DP4 P6 1 Output P4 7 RxDCA CAN_PISEL 2 0 001 DP4 P7 0 Input P7 6 RxDCA CAN_PISEL 2 0 010 DP7 P...

Page 330: ...pt Registers The interrupts of the TwinCAN module are controlled by the following interrupt control registers CAN_0IC CAN_1IC CAN_2I CAN_3I CAN_4I CAN_5IC CAN_6IC CAN_7IC All interrupt control registe...

Page 331: ...em Registers CAN_PISEL TwinCAN Port Input Select Register 20 0004H 0000H CAN_0IC TwinCAN Interrupt Control Register for the CAN interrupt node 0 F196H 0000H CAN_1IC TwinCAN Interrupt Control Register...

Page 332: ...Baud High speed receive transmit 4x mode with 41 6 kBaud Digital noise filter Power save mode and automatic walk up upon bus activity Single byte headers or consolidated headers supported CRC generati...

Page 333: ...tablishes the requirements for a serial bus protocol used in automotive and industrial applications Basically it describes the network s characteristics in three layers the physical layer the data lin...

Page 334: ...idle SOF DATA_0 Data_N CRC EOD NB IFR_1 IFR_N EOF IFS idle Figure 22 2 Standard Frame Types Table 22 1 summarizes the used abbreviations SOF Header Type 0 No IFR Data Field Type 1 Single Byte From A...

Page 335: ...te Cyclic redundancy check byte generated at the transmission and checked during reception EOD End of Data Indicates the end of a transmission by the originator of a frame directly after EOD an IFR ca...

Page 336: ...Data Bit 1 or Passive Active Data Bit 0 or Start of Frame Tv2 Tv1 Tv1 Tv2 SOF Tv3 Passive Active End of Frame EOF Tv4 Passive Active Tv3 End of Data EOD Passive Active Normalization Bit Tv3 Passive A...

Page 337: ...M module is built up by two basic blocks the Protocol Controller and the Data Link Controller The Protocol Controller basically contains the Bit Stream Processor and the two Shift Registers for the tr...

Page 338: ...onfiguration single or consolidated Normalization bit polarity selection Receive buffer overwrite control Clock divider for J1850 bus rate to adapt to the peripheral clock frequency Compensation of tr...

Page 339: ...an interrupt After Break occurrence CPU needs to reset RX TX status flags The transceiver delay should not exceed 4 s 22 2 2 2 Break Operation Break allows bus communication to be terminated All node...

Page 340: ...r detected Data receive transmit interrupt conditions combined to interrupt SDLM_I1 Message transmitted Message received Header received Figure 22 6 Interrupt Structure of SDLM SHORTH 1 Bus Shorted Hi...

Page 341: ...he user programmable overwrite enable bit OVWR If the CPU buffer is empty and the J1850 buffer is full both buffers are swapped By this action the full buffer can be accessed by the CPU and the empty...

Page 342: ...peration Register BUFFCON provides flags controlling the transmit buffer TxINCE enables analog to RxINCE FIFO Mode for the transmit buffer TXRQ initiates a frame transmission to the J1850 bus In case...

Page 343: ...t out not depending on CRCEN If the transmit buffer is used CRC will be sent out if bit CRCEN is set Bit HEADER indicates complete reception of header byte s in the receive buffer on bus side Transmis...

Page 344: ...ion a receive interrupt can be generated if RxCNT0 RxCPU0 after reception of a byte The counting sequence for the transmit buffer is 6 7 0 1 2 representing a circular buffer of 8 bytes length The coun...

Page 345: ...request flags MSGREC reception and MSGTRA transmission are automatically reset by hardware upon a read action from RxD00 or a write action to TxD0 respectively RBB RBC is set upon a pointer match aft...

Page 346: ...ed by the LSB the other byte is 0 The pointer is incremented by one after each read access to RxD00 The transmit buffer only takes over one byte per write access to TxD0 according to the LSB of the po...

Page 347: ...combined either with SDLM_I0 or can be independent GLOBCON 19H CLKDIV 84H BUFFCON 00 load data in TxBuffer END Configure J1850 Loading data into TxBuffer Data transmission MSGTRA 1 Bit 0 TRANSSTAT TxR...

Page 348: ...art TIP 1 TxRQ 0 more bytes write byte to TxD0 TxCPU 0 ARLRST 1 TxRST 1 TxRQ 1 end y n y n y n The transmit buffer should not be modified while the module is transmitting The transmission request if t...

Page 349: ...re is still one pending for the current transmit buffer is cleared Data bytes max 11 have to be written to the dedicated addresses inside the transmit buffer In normal mode TxCPU is not incremented Th...

Page 350: ...W has to check what kind of error has been detected to run an appropriate servive routine Bit MSGTRA 1 indicates that a complete byte has been sent on the bus that the transmission of the last byte is...

Page 351: ...heir addresses without changing RxCPU Figure 22 14 Receive Operation in FIFO Mode Start RBC 1 read RxD00 end y The CPU releases the receive buffer by setting bit DONE This action resets RBC If the rec...

Page 352: ...1 bytecount 0 BUSRST 1 end y The SW has to check what kind of error has been detected to run an appropriate servive routine Bit MSGREC 1 indicates that a new byte has been received which can be read...

Page 353: ...byte headers or one byte consolidated headers the flowchart shows a possibility to send IFR If an IFR is requested automatically or by hardware the IFR byte s are sent after the EOD symbol In case of...

Page 354: ...obel Kernel Control Registers Data Buffer Control Registers PISEL GLOBCON TXCNT IC0 CLKDIV TXCPU IC1 TXDELAY RXCNT IFR RXCPU BUFFSTAT RXCNTB TRANSSTAT SOFPTR BUSSTAT ERRSTAT BUFFCON FLAGRST INTCON Tra...

Page 355: ...d and data transmission via the serial bus is possible Resetting GMEN by software from 1 to 0 resets the module except the timings EN4X1 1 rw High Speed Transfer Enable 4x 0 The data transfer rate is...

Page 356: ...n case of an arbitration loss handling of IFR types 1 3 The collision detection mechanism is generally enabled during IFR 1 An automatic retry of IFR transmission in case of arbitration loss is enable...

Page 357: ...ferent system frequencies the divider can be programmed from 1 to 64 000000B System clock module clock 1 000001B System clock module clock 2 000010B System clock module clock 3 000011B System clock mo...

Page 358: ...V TD r rw rw Field Bits Type Description TD 5 0 rw Transceiver Delay Bits This bitfield defines the transceiver delay which is taken into account by the J1850 bitstream processor The value of TD deter...

Page 359: ...smission or triggered by SW IFR In Frame Response Value Register Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IFRVAL r rw Field Bits Type Description IFRVAL 7 0 rw In Frame Response Value...

Page 360: ...s and has not yet lost arbitration TIP is reset by hardware when the arbitration is lost or EOD or ENDF are detected RIP 1 rh Reception in Progress 0 The SDLM module does not currently receive a frame...

Page 361: ...uffer status and its contents are not changed new data is not received RBB is reset by hardware when the buffer is swapped to CPU side In block mode only one buffer so RBB RBC RBB is set upon a pointe...

Page 362: ...e MSGTRA is set upon a pointer match after transmission of a byte or ENDF detection It is reset when the CPU writes to the transmit buffer or by bit TXRST MSGREC 1 rh Message Received Normal Mode MSGR...

Page 363: ...been won or the transmission has been aborted H 5 rh H Bit in Consolidated Headers This bit monitors the status of bit 4 of the first byte in a frame on bus side K 6 rh K Bit in 3 Byte Consolidated H...

Page 364: ...1 0 0 IDLE END F EOD SOF r rh rh rh rh Field Bits Type Description SOF 0 rh Start Of Frame Detected Indicates the detection of SOF bit is reset by BUSRST EOD 1 rh End Of Data Detected Indicates the d...

Page 365: ...escription FORMAT 0 rh Format Error Bit is set if a frame length error byte length error symbol timing error or bit timing error occurred SHORTL 1 rh Bus Shorted Low This bit is set if the device trie...

Page 366: ...on Resetting TxIFR by software stops the transmission of the IFR TXRQ 1 rwh Transmit Request Setting bit TXRQ declares the transmit buffer to be valid and starts its transmission TXRQ is automatically...

Page 367: ...t buffer contains IFR data byte s IFR types 1 2 3 supported CRC depending on CRCEN 1 IFRVAL contains data byte for types 1 2 IFR Automatic IFR for types 1 2 for 3 byte consolidated headers supported N...

Page 368: ...by HW after clearing bit ARL and delivers 0 when read 1 wh Reset Buffer Status Flag resets ARL TXRST3 3 This bit is automatically reset by HW after clearing bit MSGTRA and delivers 0 when read 2 wh R...

Page 369: ...d Interrupt The header interrupt is disabled An interrupt is generated if bit HEADER is set ENDFIE 3 rw Enable End of Frame Detection The end of frame interrupt is disabled An interrupt is generated i...

Page 370: ...r Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TxCNT r rh Field Bits Type Description TxCNT 3 0 rh Bus Transmit Byte Counter Bitfield TxCNT contains the number of bytes transmitted by the...

Page 371: ...mit Byte Counter Bitfield TxCPU contains the number of bytes which have been written to the transmit buffer by the CPU In FIFO mode TxINCE 1 or BMEN 1 TXCPU is incremented by 1 after each CPU write ac...

Page 372: ...5 4 3 2 1 0 TXDATA1 TXDATA0 rw rw Field Bits Type Description TXDATA0 7 0 rw Transmit Buffer Data Byte 0 TXDATA1 15 8 rw Transmit Buffer Data Byte 1 TXD2 Transmit Data Register 2 Reset Value 0000H 15...

Page 373: ...DATA7 15 8 rw Transmit Buffer Data Byte 7 TXD8 Transmit Data Register 8 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDATA9 TXDATA8 rw rw Field Bits Type Description TXDATA8 7 0 rw Transmi...

Page 374: ...er RXCNT Bus Receive Byte Counter Register on CPU side Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RxCNT r rh Field Bits Type Description RxCNT 3 0 rh Receive Byte Counter Bitfield RxCNT...

Page 375: ...7 6 5 4 3 2 1 0 0 RxCPU r rwh Field Bits Type Description RxCPU 3 0 rwh CPU Receive Byte Counter Bitfield RxCPU contains the number of bytes read out by the CPU In FIFO mode RxINCE 1 or BMEN 1 RXCPU...

Page 376: ...nt the receive buffer 1 on bus side In block mode the 16 byte receive buffer is built by bitfields RXDATA00 07 and bitfields RXDATA10 17 RXD00 Receive Data Register 00 on CPU side Reset Value 0000H 15...

Page 377: ...5 15 8 rh Receive Buffer 0 Data Byte 5 RXD06 Receive Data Register 06 on CPU side Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA07 RXDATA06 rh rh Field Bits Type Description RXDATA06 7...

Page 378: ...Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RXDATA010 rh rh Field Bits Type Description RXDATA010 7 0 rh Receive Buffer 0 Data Byte 8 0 15 8 Reserved returns 0 if read RXCNTB Bus Receive Byte...

Page 379: ...s Type Description SOFCNT 3 0 rh Start of Frame Counter for Block Mode The value of bitfield RxCNT is automatically copied to this bitfield if an end of frame symbol is detected This feature can be us...

Page 380: ...3 15 8 rh Receive Buffer 1 Data Byte 3 RXD14 Receive Data Register 14 on bus side Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA15 RXDATA14 rh rh Field Bits Type Description RXDATA14 7...

Page 381: ...ses and reset values RXD18 Receive Data Register 18 on bus side Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA19 RXDATA18 rh rh Field Bits Type Description RXDATA18 7 0 rh Receive Buff...

Page 382: ...e is connected to Port pins according to Figure 22 18 Figure 22 18 SDLM Module IO Interface The input receive pins can be selected by bitfield RIS in the SDLM_PISEL register The output transmit pins a...

Page 383: ...st lines The interrupt request line SDLM_I1 can share a interrupt node with SDLM_I0 or alternatively with the TwinCAN interrupt request line 7 The selection is controlled via bitfield I1SEL in the SDL...

Page 384: ...LM Module Related External Registers Figure 22 20 shows the module related external registers which are required for programming the SDLM module Figure 22 20 SDLM Implementation Specific Registers Por...

Page 385: ...00 The input pin for RxDJ is P4 6 01 The input pin for RxDJ is P4 4 10 The input pin for RxDJ is P9 3 11 The input pin for RxDJ is P7 7 I1SEL 2 rw Interrupt SDLM_I1 Selection Bit I1SEL defines the int...

Page 386: ...n of this pin must be set to input via the Port Direction Control register DP4 or DP7 or DP9 ALTSEL0P4 P4 Alternate Select Register 0 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 P7 P6 0...

Page 387: ...cription DP4 y 7 6 4 rw Port Direction Register DP4 Bit y 0 Port line P4 y is an input high impedance 1 Port line P4 y is an output ALTSEL0P7 P7 Alternate Select Register 0 Reset Value 0000H 15 14 13...

Page 388: ...y 7 6 rw Port Direction Register DP7 Bit y 0 Port line P7 y is an input high impedance 1 Port line P7 y is an output ALTSEL0P9 P9 Alternate Select Register 0 Reset Value 0000H 15 14 13 12 11 10 9 8 7...

Page 389: ...rw rw rw Field Bit Type Description ALTSEL1 P9 y 2 rw P9 Alternate Select Register 1 Bit y 0 associated peripheral output is not selected as alternate function 1 associated peripheral output is select...

Page 390: ...election and Setup Port Lines Alternate Select Registers Port Input Select Register Direction Control Register IO P4 4 RxDJ SDLM_PISEL 1 0 01 DP4 P4 0 Input P4 6 RxDJ SDLM_PISEL 1 0 00 DP4 P6 0 Input...

Page 391: ...rs The interrupt of the SDLM module is controlled by interrupt control register SDLM_IC Note Please refer to the general Interrupt Control Register description for an explanation of the control fields...

Page 392: ...gister 0000H ASC0_RBUF FEB2H 59H SFR ASC0 Receive Buffer Register 0000H ASC0_ ABCON F1B8H DCH ESFR ASC0 Autobaud Control Register 0000H ASC0_ ABSTAT F0B8H 5CH ESFR ASC0 Autobaud Status Register 0000H...

Page 393: ...FB2H D9H SFR SSC0 Control Register 0000H SSC0_BR F0B4H 5AH ESFR SSC0 Baudrate Timer Reload Register 0000H SSC0_TB F0B0H 58H ESFR SSC0 Transmit Buffer Reg 0000H SSC0_RB F0B2H 59H ESFR SSC0 Receive Buff...

Page 394: ...low word 8003H RTC_T14 F0D2H 69H ESFR Timer 14 Register UUUUH RTC_T14REL F0D0H 68H ESFR Timer 14 Reload Register UUUUH RTC_RTCL F0D4H 6AH ESFR RTC Timer Low Register UUUUH RTC_RTCH F0D6H 6BH ESFR RTC...

Page 395: ...0H SFR CAPCOM 1 Register 0 0000H CC1_CC1 FE82H 41H SFR CAPCOM 1 Register 1 0000H CC1_CC2 FE84H 42H SFR CAPCOM 1 Register 2 0000H CC1_CC3 FE86H 43H SFR CAPCOM 1 Register 3 0000H CC1_CC4 FE88H 44H SFR C...

Page 396: ...T7 F050H 28H ESFR CAPCOM 2 Timer 7 Register 0000H CC2_T8 F052H 29H ESFR CAPCOM 2 Timer 8 Register 0000H CC2_T7REL F054H 2AH ESFR CAPCOM 2 Timer 7 Reload Register 0000H CC2_T8REL F056H 2BH ESFR CAPCOM...

Page 397: ...D Converter Control Register 0000H ADC_CTR0 FFBEH DFH SFR A D Converter Control Register 0 1000H ADC_CTR2 F09CH 4EH ESFR A D Converter Control Register 2 0000H ADC_CTR2IN F09EH 4FH ESFR A D Converter...

Page 398: ...Error Status 0000H SDLM_ BUFFCON E924H IO Buffer Control Register 0000H SDLM_ FLAGRST E928H IO Flag Reset Register 0000H SDLM_ INTCON E92CH IO Interrupt Control Register 0000H SDLM_ TXCNT E93CH IO Bu...

Page 399: ...XD04 E944H IO Receive Data Register 04 0000H SDLM_ RXD06 E946H IO Receive Data Register 06 0000H SDLM_ RXD08 E948H IO Receive Data Register 08 0000H SDLM_ RXD010 E94AH IO Receive Data Register 010 000...

Page 400: ...rupt Control Register 0000H ASC0_RIC FF6EH B7H SFR ASC0 Receive Interrupt Control Register 0000H ASC0_EIC FF70H B8H SFR ASC0 Error Interrupt Control Register 0000H ASC0_TBIC F19CH CEH ESFR ASC0 Transm...

Page 401: ...C F1A0H D0H ESFR RTC Interrupt Control Register 0000H CC1_T0IC FF9CH CEH SFR CAPCOM Timer 0 Interrupt Control Register 0000H CC1_T1IC FF9EH CFH SFR CAPCOM Timer 1 Interrupt Control Register 0000H CC2_...

Page 402: ...l Register 0000H CC1_CC12IC FF90H C8H SFR CAPCOM Register 12 Interrupt Control Register 0000H CC1_CC13IC FF92H C9H SFR CAPCOM Register 13 Interrupt Control Register 0000H CC1_CC14IC FF94H CAH SFR CAPC...

Page 403: ...ontrol Register 0000H CC2_CC28IC F178H BCH ESFR CAPCOM Register 28 Interrupt Control Register 0000H CC2_CC29IC F184H C2H ESFR CAPCOM Register 29 Interrupt Control Register 0000H CC2_CC30IC F18CH C6H E...

Page 404: ...ESFR Port Input Threshold Control Register 0000H POCON0L F080H 40H ESFR P0L Output Control Register 0000H POCON0H F082H 41H ESFR P0H Output Control Register 0000H POCON1L F084H 42H ESFR P1L Output Co...

Page 405: ...ster 0000H DP3 FFC6H E3H SFR P3 Direction Control Register 0000H ODP3 F1C6H E3H ESFR P3 Open Drain Control Register 0000H ALTSEL0P3 F126H 93H ESFR P3 Alternate Select Register 0 0000H ALTSEL1P3 F128H...

Page 406: ...nate Select Register 1 0000H P9 FF16H 8BH SFR Port 9 Data Register 0000H DP9 FF18H 8CH SFR P9 Direction Control Register 0000H ODP9 FF1AH 8DH SFR P9 Open Drain Control Register 0000H ALTSEL0P9 F138H 9...

Page 407: ...AN_AFCRH 20 0216H Node A Frame Counter Register High 0000H CAN_AIMRL0 20 0218H Node A INTID Mask Register 0 Low 0000H CAN_AIMRH0 20 021AH Node A INTID Mask Register 0 High 0000H CAN_AIMR4 20 021CH Nod...

Page 408: ...Control Register 0 0000H CAN_1IC 00 F142H 1 TwinCAN Interrupt Control Register 1 0000H CAN_2IC 00 F144H 1 TwinCAN Interrupt Control Register 2 0000H CAN_3IC 00 F146H 1 TwinCAN Interrupt Control Regis...

Page 409: ...ect 16 20 0500H Message Object 17 20 0520H Message Object 18 20 0540H Message Object 19 20 0560H Message Object 20 20 0580H Message Object 21 20 05A0H Message Object 22 20 05C0H Message Object 23 20 0...

Page 410: ...GARLn 08H Message Object n Arbitration Register Low 0000H CAN_ MSGARHn 0AH Message Object n Arbitration Register High 0000H CAN_ MSGAMRLn 0CH Message Object n Acceptance Mask Register Low 0000H CAN_ M...

Page 411: ...Segment 6 19 1 Addressing Modes CoREG Addressing Mode 4 51 1 DSP Addressing Modes 4 47 1 Indirect Addressing Modes 4 45 1 Long Addressing Modes 4 41 1 Short Addressing Modes 4 39 1 Alternate Port Fun...

Page 412: ...SEE CC2_SEE 17 28 2 CC1_SEM CC2_SEM 17 27 2 CC1_T01CON 17 5 2 CC1_T0IC 17 9 2 CC1_T1IC 17 9 2 CC2_M4 7 17 11 2 CC2_T78CON 17 5 2 CC2_T7IC 17 9 2 CC2_T8IC 17 9 2 CCxIC 17 34 2 Chip Select Configuration...

Page 413: ...d Flash 3 21 1 Error correction 3 25 1 Error Detection ASC 18 34 2 SSC 19 14 2 EXICON 5 37 1 EXISEL0 5 38 1 EXISEL1 5 38 1 External Bus 2 13 1 Fast interrupts 5 37 1 Interrupt pulses 5 40 1 Interrupt...

Page 414: ...1 Pipeline 4 11 1 protected 12 6 1 Interface ASC 18 1 2 CAN 2 25 1 External Bus 9 1 1 IIC 2 26 1 20 1 2 J1850 2 24 1 SDLM 22 1 2 SSC 19 1 2 Interrupt Arbitration 5 4 1 during sleep mode 5 39 1 Enable...

Page 415: ...7 29 1 P4 7 41 1 P5 7 51 1 7 52 1 P8 7 54 1 7 65 1 7 72 1 7 82 1 PEC 2 10 1 5 18 1 Latency 5 41 1 Transfer Count 5 19 1 PEC pointers 3 7 1 PECCx 5 19 1 PECISNC 5 27 1 PECSEGx 5 23 1 Peripheral Event C...

Page 416: ...atures Flash 3 27 1 Segment Address 6 19 1 boundaries 3 15 1 Segmentation 4 37 1 Self calibration 16 17 2 Serial Interface 2 22 1 2 23 1 ASC 18 1 2 Asynchronous 18 5 2 CAN 2 25 1 IIC 2 26 1 20 1 2 J18...

Page 417: ...normal mode 21 29 2 shared mode 21 36 2 with FIFO 21 33 2 initialization 21 40 2 interrupts indication INTID 21 13 2 21 53 2 node pointer request compressor 21 5 2 loop back mode 21 44 2 message handl...

Page 418: ...21 51 2 BBTRH 21 56 2 BBTRL 21 56 2 BCR 21 49 2 BECNTH 21 54 2 BECNTL 21 54 2 BFCRH 21 58 2 BFCRL 21 58 2 BGINP 21 61 2 BIMR0H 21 62 2 BIMR0L 21 62 2 BIMR4 21 63 2 BIR 21 53 2 BSR 21 51 2 MSGAMRHn 21...

Page 419: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG...

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