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XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Table of Contents
Page
User’s Manual
I-2
V2.2, 2004-01
Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1]
Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 [1]
IMB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1]
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1]
Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1]
Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1]
Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1]
Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]
Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1]
Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1]
Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1]
Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1]
CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1]
Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1]
GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1]
Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1]
Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]
Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1]
Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1]
DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1]
The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1]
Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1]
16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . 4-61 [1]
Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1]
Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1]
DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1]
Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . 4-66 [1]
The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . 4-67 [1]
Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]
The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]
The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]
The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . 4-69 [1]
The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1]
The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1]