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MB95630H Series

448

FUJITSU SEMICONDUCTOR LIMITED

MN702-00009-1v0-E

CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers

[bit4] ICRE: Compare clear interrupt enable bit
This bit enables or disables the compare clear interrupt.
When this bit is set to "1", and the compare clear interrupt request flag bit (ICLR) is also set to "1", a
compare clear interrupt is generated.

[bit3] TMEN: Timer enable bit
This bit enables or disables the counting operation of the 16-bit timer.

Note: When the counting operation of the 16-bit timer is disabled, the output compare operation is also

disabled.

[bit2:0] CLK[2:0]: Clock frequency select bits
These bits select the count clock of the 16-bit timer.

Note: Since the count clock is changed immediately after these bits are updated, it is recommend to modify

these bits while the 16-bit timer is in stop state.

bit4

Details

Writing "0"

Disables the compare clear interrupt.

Writing "1"

Enables the compare clear interrupt.

bit3

Details

Writing "0"

Disables the counting operation of the 16-bit timer.

Writing "1"

Enables the counting operation of the 16-bit timer.

bit2:0

Details

(MCLK: machine clock)

Count clock

MCLK = 16 MHz MCLK = 8 MHz

MCLK = 4 MHz

MCLK = 1 MHz

Writing "000"

1 MCLK

62.5 ns

125 ns

0.25 µs

1 µs

Writing "001"

MCLK/2

125 ns

0.25 µs

0.5 µs

2 µs

Writing "010"

MCLK/4

0.25 µs

0.5 µs

1 µs

4 µs

Writing "011"

MCLK/8

0.5 µs

1 µs

2 µs

8 µs

Writing "100"

MCLK/16

1 µs

2 µs

4 µs

16 µs

Writing "101"

MCLK/32

2 µs

4 µs

8 µs

32 µs

Writing "110"

MCLK/64

4 µs

8 µs

16 µs

64 µs

Writing "111"

MCLK/128

8 µs

16 µs

32 µs

128 µs

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Summary of Contents for MB95630H Series

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL 8 BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL MN702 00009 1v0 E ...

Page 2: ......

Page 3: ...ITSU SEMICONDUCTOR LIMITED 8 BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL For the information for microcontroller supports see the following website http edevice fujitsu com micom en support ...

Page 4: ......

Page 5: ...ipheral functions but not to provide specifications of a device For detailed specifications of a device refer to its data sheet For details on individual instructions refer to F2 MC 8FX Programming Manual Note F2MC is the abbreviation of FUJITSU Flexible Microcontroller Trademark The company names and brand names in this document are the trademarks or registered trademarks of their respective owne...

Page 6: ...ad access and write access of each bit R Read only W Write only R W Readable Writable Undefined Initial value Initial value of a bit after a reset 0 The initial value is 0 1 The initial value is 1 X The initial value is undefined Multiple bits are indicated in this manual in the following way Example 1 bit7 0 represents bit7 to bit0 Example 2 SCM 2 0 represents SCM2 to SCM0 The values such as thos...

Page 7: ...ontained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a s...

Page 8: ...iv ...

Page 9: ...3 4 Standby Control Register STBC 32 3 3 5 System Clock Control Register 2 SYCC2 34 3 3 6 Standby Control Register 2 STBC2 36 3 4 Clock Modes 37 3 5 Operations in Low Power Consumption Mode Standby Mode 41 3 5 1 Notes on Using Standby Mode 42 3 5 2 Sleep Mode 48 3 5 3 Stop Mode 49 3 5 4 Time base Timer Mode 51 3 5 5 Watch Mode 53 3 6 Clock Oscillator Circuit 54 3 7 Overview of Prescaler 55 3 8 Con...

Page 10: ... 8 4 1 Watchdog Timer Control Register WDTC 107 8 5 Notes on Using Watchdog Timer 109 CHAPTER 9 WATCH PRESCALER 111 9 1 Overview 112 9 2 Configuration 113 9 3 Interrupt 115 9 4 Operations and Setting Procedure Example 116 9 5 Register 119 9 5 1 Watch Prescaler Control Register WPCR 120 9 6 Notes on Using Watch Prescaler 122 CHAPTER 10 WILD REGISTER FUNCTION 123 10 1 Overview 124 10 2 Configuration...

Page 11: ...1 15 Notes on Using 8 16 bit Composite Timer 173 CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT 175 12 1 Overview 176 12 2 Configuration 177 12 3 Channels 178 12 4 Pin 179 12 5 Interrupt 180 12 6 Operations and Setting Procedure Example 181 12 7 Register 183 12 7 1 External Interrupt Control Register EIC 184 12 8 Notes on Using External Interrupt Circuit 186 CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT 187 1...

Page 12: ... 255 14 7 7 LIN UART Baud Rate Generator Registers 1 0 BGR1 BGR0 257 14 8 Notes on Using LIN UART 258 CHAPTER 15 8 10 BIT A D CONVERTER 263 15 1 Overview 264 15 2 Configuration 265 15 3 Pin 267 15 4 Interrupt 268 15 5 Operations and Setting Procedure Example 269 15 6 Registers 272 15 6 1 8 10 bit A D Converter Control Register 1 ADC1 273 15 6 2 8 10 bit A D Converter Control Register 2 ADC2 275 15...

Page 13: ...ocedure Example 340 19 7 Registers 344 19 7 1 16 bit PPG Downcounter Register Upper Lower PDCRHn PDCRLn 345 19 7 2 16 bit PPG Cycle Setting Buffer Register Upper Lower PCSRHn PCSRLn 346 19 7 3 16 bit PPG Duty Setting Buffer Register Upper Lower PDUTHn PDUTLn 347 19 7 4 16 bit PPG Status Control Register Upper PCNTHn 348 19 7 5 16 bit PPG Status Control Register Lower PCNTLn 350 19 8 Notes on Using...

Page 14: ...r Upper OPCUR 427 21 6 2 16 bit MPG Output Control Register Lower OPCLR 429 21 6 3 16 bit MPG Output Data Register Upper Lower OPDUR OPDLR 431 21 6 3 1 16 bit MPG Output Data Register Upper OPDUR 432 21 6 3 2 16 bit MPG Output Data Register Lower OPDLR 434 21 6 4 16 bit MPG Output Data Buffer Register Upper Lower OPDBRHx OPDBRLx 435 21 6 4 1 16 bit MPG Output Data Buffer Register Upper OPDBRHx 436...

Page 15: ...Bus Interface 503 24 6 2 Function to Wake up the MCU from Standby Mode 511 24 7 Registers 513 24 7 1 I2C Bus Control Register 0 IBCR0n 514 24 7 2 I2 C Bus Control Register 1 IBCR1n 517 24 7 3 I2 C Bus Status Register IBSRn 521 24 7 4 I2C Data Register IDDRn 524 24 7 5 I2 C Address Register IAARn 525 24 7 6 I2 C Clock Control Register ICCRn 526 24 8 Notes on Using I2C Bus Interface 528 CHAPTER 25 D...

Page 16: ...RTH 581 26 3 2 Main CR Clock Trimming Register Lower CRTL 582 26 3 3 Main CR Clock Temperature Dependent Adjustment Register CRTDA 583 26 3 4 Watchdog Timer Selection ID Register Upper Lower WDTH WDTL 584 26 4 Notes on Main CR Clock Trimming 585 26 5 Notes on Using NVR Interface 587 CHAPTER 27 COMPARATOR 589 27 1 Overview 590 27 2 Configuration 591 27 3 Pins 593 27 4 Interrupt 594 27 5 Operations ...

Page 17: ...trol Register STBC Register Functions Corrected the following heading in the bit function table of the TMD bit In main clock mode or main CR clock mode In main clock mode main CR clock mode or main CR PLL clock mode 53 3 5 5 Watch Mode Operations in Watch Mode Release from Watch Mode Added the following statement at the end of the section However if a program is being executed on the RAM no Flash ...

Page 18: ...0 Register Functions Corrected the bit number in the title of details of the F 3 0 bits bit3 bit3 0 299 CHAPTER 17 CLOCK SUPERVISOR COUNTER 17 4 1 Clock Monitoring Data Reg ister CMDR Register Functions Corrected the name of the CMDR 7 0 bits Analog input pin select bits Clock monitoring data bits 323 CHAPTER 18 8 16 BIT PPG 18 7 2 8 16 bit PPG Timer n0 Con trol Register PCn0 Register Functions Ad...

Page 19: ...R2n SMC2n 514 CHAPTER 24 I2 C BUS INTERFACE 24 7 1 I2C Bus Control Register 0 IBCR0n Revised the summary of this section 517 CHAPTER 24 I2C BUS INTERFACE 24 7 2 I2 C Bus Control Register 1 IBCR1n Revised the summary of this section 597 CHAPTER 27 COMPARATOR 27 6 1 Comparator Control Regis ter CMR0C Register Functions Revised the initial value of the IF bit X 0 Page Revisions For details see their ...

Page 20: ...xvi ...

Page 21: ...MN702 00009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 1 CHAPTER 1 MEMORY ACCESS MODE This chapter describes the memory access mode 1 1 Memory Access Mode ...

Page 22: ...a used to determine the memory access mode of the CPU The mode data address is fixed at 0xFFFD Always set the mode data of the Flash memory to 0x00 to select the single chip mode Figure 1 1 1 Mode Data Settings After a reset is released the CPU fetches mode data first The CPU then fetches the reset vector after the mode data It starts executing instructions from the address set in the reset vector...

Page 23: ...009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 3 CHAPTER 2 CPU This chapter describes the functions and operations of the CPU 2 1 Dedicated Registers 2 2 General purpose Register 2 3 Placement of 16 bit Data in Memory ...

Page 24: ...er an instruction is executed or an interrupt or a reset occurs The initial value set immediately after a reset is the mode data read address 0xFFFD Accumulator A The accumulator is a 16 bit register for arithmetic operation It is used for a variety of arithmetic and transfer operations of data in memory or data in other registers such as the temporary accumulator T The data in the accumulator can...

Page 25: ...he memory address for data access The initial value after a reset is 0x0000 Stack pointer SP The stack pointer is a 16 bit register which holds the address referenced when an interrupt or a sub routine call occurs and by the stack push and pop instructions During program execution the value of the stack pointer indicates the address of the most recent data pushed onto the stack The initial value a...

Page 26: ...0 and 31 in the upper five bits of the register bank pointer Each register bank has eight 8 bit general purpose registers which are selected by the lower three bits of the op code The register bank pointer allows the space from 0x0100 to 0x01FF max to be used as a general purpose register area However certain products have restrictions on the size of the area available for the general purpose regi...

Page 27: ... the value of the direct bank pointer and the operand Table 2 1 1 shows the relationship between the direct bank pointer DP and the access area Table 2 1 2 lists the direct addressing instructions The available access area varies among products For details refer to the device data sheet CCR DP RP PS 0b000 DP initial value R4 R3 R2 R1 R0 DP2 DP1 DP0 H I IL1 IL0 N Z V C bit15 bit14 bit13 bit12 bit11...

Page 28: ...PU 2 1 Dedicated Registers Table 2 1 2 Direct Address Instruction List Applicable instructions CLRB dir bit SETB dir bit BBC dir bit rel BBS dir bit rel MOV A dir CMP A dir ADDC A dir SUBC A dir MOV dir A XOR A dir AND A dir OR A dir MOV dir imm CMP dir imm MOVW A dir MOVW dir A ...

Page 29: ...is set to 0 Do not use this flag for any operation other than addition and subtraction as the flag is intended for decimal adjusted instructions Negative flag N This flag is set to 1 when the value of the most significant bit is 1 due to the result of an operation and is set to 0 when the value of the most significant bit is 0 Zero flag Z This flag is set to 1 when the result of an operation is 0 ...

Page 30: ... instructions set and clear the flag to 1 and 0 respectively Interrupt level bits IL 1 0 These bits indicate the level of the interrupt currently accepted by the CPU The interrupt level is compared with the value of the interrupt level setting register ILR0 to ILR5 that corresponds to the interrupt request IRQ00 to IRQ23 of each peripheral function The CPU services an interrupt request only when i...

Page 31: ...urpose register area in RAM Up to 32 banks can be used each of which consists of eight registers R0 to R7 The register bank pointer RP specifies the register bank currently being used and the lower three bits of the op code specify the general purpose register 0 R0 to the general purpose register 7 R7 Figure 2 2 1 shows the configuration of the register banks Figure 2 2 1 Configuration of Register...

Page 32: ...nning of an interrupt service routine This therefore eliminates the need to save data of a general purpose register in a stack thereby enabling the CPU to receive interrupts at high speed Note In an interrupt service routine include one of the following in a program to ensure that values of the interrupt level bits CCR IL 1 0 of the condition code register are not modified when modifying a registe...

Page 33: ...bit data the upper byte is stored at the address closer to the op code instruction and the lower byte is stored at the address next to the one at which the upper byte is stored That is true whether an operand is either a memory address or 16 bit immediate data Figure 2 3 2 shows how 16 bit data in an instruction is placed Figure 2 3 2 Placement of 16 bit Data in Instruction Storage state of 16 bit...

Page 34: ...MB95630H Series 14 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 2 CPU 2 3 Placement of 16 bit Data in Memory ...

Page 35: ... operations of the clock controller 3 1 Overview 3 2 Oscillation Stabilization Wait Time 3 3 Registers 3 4 Clock Modes 3 5 Operations in Low Power Consumption Mode Standby Mode 3 6 Clock Oscillator Circuit 3 7 Overview of Prescaler 3 8 Configuration of Prescaler 3 9 Operation of Prescaler 3 10 Notes on Using Prescaler ...

Page 36: ... selects the clock source and controls the internal CR oscillator and frequency divider circuits The clock controller controls the internal clock according to the clock mode standby mode settings and the reset operation The clock mode is used to select an internal operating clock the standby mode is used to enable and disable clock oscillation and signal supply The clock controller selects the opt...

Page 37: ...k FCRH 6 Sub CR clock FCRL 7 Source clock SCLK 8 Machine clock MCLK 9 Main CR PLL clock FMCRPLL Main CR clock oscillator circuit Main clock oscillator circuit Subclock oscillator circuit Main CR PLL clock oscillator circuit Sub CR clock oscillator circuit Divide by 2 5 6 9 1 2 3 4 Watch or time base timer mode Sleep mode Stop mode Clock for time base timer Clock for watch timer MPEN MPMC1 MPMC0 MP...

Page 38: ...it This block controls the supply of the machine clock to the CPU and each peripheral resource according to the standby mode used or oscillation stabilization wait time Oscillation stabilization wait circuit This block outputs oscillation stabilization wait time signals according to clocks that are enabled to operate In the case of main clock its oscillation stabilization signal can be selected fr...

Page 39: ...clock main CR clock subclock and sub CR clock and to display the ready signals of main clock oscillation subclock oscillation sub CR oscillation and main CR oscillation Oscillation stabilization wait time setting register WATR This register is used to set the oscillation stabilization wait time for the main clock and subclock Standby control register 2 STBC2 This register is used to control the de...

Page 40: ... mode the frequency of a selected clock can be divided Table 3 1 1 Clock Modes and Machine Clock Selection Clock mode Machine clock Main clock mode The machine clock is generated by dividing the main oscillation clock by 2 Main CR clock mode The machine clock is generated from the main CR clock Main CR PLL clock mode The machine clock is generated by multiplying the main CR clock by a PLL multipli...

Page 41: ...r NVR interface For details of the non volatile register NVR interface see CHAPTER 26 NON VOLATILE REGISTER NVR INTERFACE Table 3 1 2 Standby Mode and Clock Supply States Standby mode Clock supply state Sleep mode Clock supply to the CPU is stopped As a result the CPU stops operating but other peripheral functions continue operating Time base timer mode Clock signals are only supplied to the time ...

Page 42: ...ate by the deep standby mode control bit in the standby control register 2 STBC2 DSTBYX Table 3 1 3 Combinations of Standby Mode and Clock Mode and Internal Operating States 1 Function RUN Sleep Main clock mode Main CR clock mode Main CR PLL clock mode Subclock mode Sub CR clock mode Main clock mode Main CR clock mode Main CR PLL clock mode Subclock mode Sub CR clock mode Main clock Operating Stop...

Page 43: ... control register 2 STBC2 DSTBYX Table 3 1 4 Combinations of Standby Mode and Clock Mode and Internal Operating States 2 Function Time base timer Watch Stop Main clock mode Main CR clock mode Main CR PLL clock mode Subclock mode Sub CR clock mode Main clock mode Main CR clock mode Main CR PLL clock mode Subclock mode Sub CR clockmode Main clock Operating Stopped 1 Stopped Stopped Main CR clock Mai...

Page 44: ...are operation before making the clock mode transit to another mode the clock controller automatically waits for the oscillation stabilization wait time of the clock for that mode to elapse Figure 3 2 1 shows how the oscillator runs immediately after starting oscillating Figure 3 2 1 Behavior of Oscillator Immediately after Starting Oscillation Oscillation stabilization wait time of main clock subc...

Page 45: ...n stop state is generated due to a change of clock mode caused by an interrupt in standby mode or by the software operation the clock controller automatically waits for the CR oscillation stabilization wait time to elapse Table 3 2 3 shows the CR oscillation stabilization wait time 1 FCRH 4 MHz 2 FCRL 150 kHz Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition If state trans...

Page 46: ...f clocks according to a designated order of priority Below are the respective orders of priority for counting different oscillation stabilization wait times in different clock modes Main clock mode Sub CR clock Subclock Main CR clock Main CR PLL clock Main CR clock mode Sub CR clock Subclock Main CR PLL clock Main clock Main CR PLL clock mode Sub CR clock Subclock Main clock Subclock mode Sub CR c...

Page 47: ...the clock controller Table 3 3 1 List of Clock Controller Registers Register abbreviation Register name Reference SYCC System clock control register 3 3 1 PLLC PLL control register 3 3 2 WATR Oscillation stabilization wait time setting register 3 3 3 STBC Standby control register 3 3 4 SYCC2 System clock control register 2 3 3 5 STBC2 Standby control register 2 3 3 6 ...

Page 48: ... source clock The machine clock is generated from the source clock according to the divide ratio set by these bits bit 7 6 5 4 3 2 1 0 Field SCM2 SCM1 SCM0 SCS2 SCS1 SCS0 DIV1 DIV0 Attribute R R R R W R W R W R W R W Initial value X X X 1 1 0 1 1 bit7 5 Details Reading 000 Indicates that the current clock mode is subclock mode Reading 010 Indicates that the current clock mode is main clock mode Re...

Page 49: ...er The settings of these bits can be modified only when the main CR PLL clock is stopped Thus these bits can be modified in main clock mode main CR clock mode subclock mode or sub CR clock mode Note When SCS 2 0 or SCM 2 0 are set to 0b111 writing values to MPMC 1 0 is prohibited bit4 MPRDY Main CR PLL clock oscillation stabilization bit This bit indicates whether the main CR PLL clock oscillation...

Page 50: ... subclock oscillation stop bit in the system clock control register 2 SYCC2 SOSCE set to 0 in main clock mode main CR clock mode main CR PLL clock mode or sub CR clock mode bit 7 6 5 4 3 2 1 0 Field SWT3 SWT2 SWT1 SWT0 MWT3 MWT2 MWT1 MWT0 Attribute R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 bit7 4 Details No of cycles Subclock FCL 32 768 kHz Writing 1111 215 2 215 2 FCL About 1 ...

Page 51: ...main clock oscillation stop bit in the system clock control register 2 SYCC2 MOSCE set to 0 in main CR clock mode main CR PLL clock mode subclock mode or sub CR clock mode bit3 0 Details No of cycles Main clock FCH 4 MHz Writing 1111 214 2 214 2 FCH About 4 10 ms Writing 1110 213 2 213 2 FCH About 2 05 ms Writing 1101 212 2 212 2 FCH About 1 02 ms Writing 1100 211 2 211 2 FCH About 511 5 µs Writin...

Page 52: ...p mode The read value of this bit is always 0 Note After an interrupt request is generated writing 1 to this bit is ignored For details see 3 5 1 Notes on Using Standby Mode bit5 SPL Pin state setting bit This bit sets the states of external pins in stop mode time base timer mode and watch mode bit 7 6 5 4 3 2 1 0 Field STP SLP SPL SRST TMD Attribute W W R W W W Initial value 0 0 0 0 0 0 0 0 bit7 ...

Page 53: ...values to these bits has no effect on operation Notes Set a standby mode after making sure that the transition to clock mode has been completed by comparing the values of the clock mode monitor bits SYCC SCM 2 0 and clock mode select bits SYCC SCS 2 0 in the system clock control register If two or more of the following bits stop bit STP sleep bit SLP software reset bit SRST and watch bit TMD are s...

Page 54: ...peration bit4 MCRDY Main CR clock oscillation stabilization bit This bit indicates whether the main CR clock oscillation has become stable This bit is read only Writing a value to this bit has no effect on operation bit 7 6 5 4 3 2 1 0 Field SRDY MRDY SCRDY MCRDY SOSCE MOSCE SCRE MCRE Attribute R R R R R W R W R W R W Initial value X X X X 0 0 1 1 bit7 Details Reading 0 Indicates that the clock co...

Page 55: ...his bit will be automatically set to 1 When SCS 2 0 or SCM 2 0 are set to 0b100 writing 0 to this is has no effect on operation When SCS 2 0 and SCM 2 0 are not set to 0b100 this bit can be modified independently of other bits bit0 MCRE Main CR clock oscillation enable bit This bit enables or disables the main CR clock oscillation When SCS 2 0 are set to 0b110 or 0b111 this bit will be automatical...

Page 56: ... the difference between the deep standby mode and the normal standby mode in power consumption Do not make the device transit to deep standby mode when a Flash command sequence except read reset has been invoked bit 7 6 5 4 3 2 1 0 Field DSTBYX Attribute R W Initial value 0 0 0 0 0 0 0 0 bit0 Details Writing 0 Sets the Flash memory to the low power state when the device enters standby mode accordi...

Page 57: ...ck Mode or Main CR PLL Clock Mode In main CR clock mode or main CR PLL clock mode the main CR clock or the main CR PLL clock is used as the machine clock for the CPU and peripheral functions The time base timer and the watchdog timer operate using the main CR clock or the main CR PLL clock The watch prescaler operates using the subclock or the sub CR clock While the device is operating in main CR ...

Page 58: ...abilization wait time sub CR clock oscillation stabilization wait time Main CR clock or main CR PLL clock oscillation stabilization wait time Main CR clock or main CR PLL clock oscillation stabilization Sub CR clock oscillation stabilization wait time Sub CR clock mode Main CR clock mode or main CR PLL clock mode Main CR clock mode 1 2 5 7 4 11 17 12 A reset occurs in any other state 1 Main clock ...

Page 59: ...he system clock control register 2 SYCC2 SRDY is 1 the device transits to subclock mode immediately after the clock mode select bits SYCC SCS 2 0 are set to 0b000 4 5 Main clock When the clock mode select bits in the system clock control register SYCC SCS 2 0 are set to 0b010 the device transits to main clock mode after waiting for the main clock oscillation stabilization wait time When the main c...

Page 60: ... control register SYCC SCS 2 0 are set to 0b111 the device transits to main CR PLL clock mode after waiting for the main CR PLL clock oscillation stabilization wait time 14 Main clock When the clock mode select bits in the system clock control register SYCC SCS 2 0 are set to 0b010 the device transits to main clock mode after waiting for the main clock oscillation stabilization wait time 15 Subclo...

Page 61: ...fore transiting to normal operation the device may wait for the oscillation stabilization wait time to elapse if necessary When the clock mode returns from standby mode due to a reset the device returns to main CR clock mode When the clock mode returns from standby mode due to an interrupt the device returns to the previous clock mode before transiting to standby mode Pin States in Standby Mode Th...

Page 62: ...instruction execution cycles Check that clock mode transition has been completed before setting the standby mode Before setting the standby mode ensure that clock mode transition has been completed by comparing the values of the clock mode monitor bits SYCC SCM 2 0 and clock mode select bits SYCC SCS 2 0 in the system clock control register An interrupt request may suppress the transition to stand...

Page 63: ...pt source it takes more time to wake up the device from deep standby mode than from normal standby mode 2 Normal standby mode STBC2 DSTBYX 1 In standby mode the power consumption in normal standby mode is higher than that in deep standby mode However since the device does not have to wait for the Flash recovery wait time to elapse before being woken up from normal standby mode by a reset or an int...

Page 64: ... the device transits to main CR clock mode If the reset that has occurred is a power on reset a watchdog reset a software reset or an external reset the device always wait for the main CR clock oscillation stabilization wait time and the sub CR clock oscillation stabilization wait time to elapse 1 Sleep mode The device transits to sleep mode when 1 is written to the sleep bit in the standby contro...

Page 65: ...vice transits to watch mode when 1 is written to the watch bit in the standby control register STBC TMD in subclock mode or sub CR clock mode 8 The device returns to the RUN state in response to an interrupt from a peripheral resource Table 3 5 1 Table of State Transition with Deep Standby Mode Disabled Transition to and from Standby Mode 2 2 State transition Description ...

Page 66: ...hine clock In main clock mode main CR clock mode or main CR PLL clock mode Maximum 10 SCLK 150 µs 6 MCLK In subclock mode or sub CR clock mode Maximum 2 SCLK 150 µs 6 MCLK Power on Reset state Normal RUN state Watch mode Main clock main CR clock main CR PLL clock subclock sub CR clock oscillation stabilization wait time Sleep mode Flash recovery wait time Sleep mode Flash recovery wait time Time b...

Page 67: ...device returns to the RUN state When the oscillation stabilization wait time is shorter than the Flash recovery wait time after the oscillation stabilization wait time elapses the device transits to sleep mode and remains in sleep mode until the Flash recovery wait time elapses When the oscillation stabilization wait time is longer than the Flash recovery wait time after the oscillation stabilizat...

Page 68: ...g timer if it is enabled in standby mode by the non volatile register function in sleep mode the sub CR clock does not stop and the hardware watchdog timer continues its operation For details see CHAPTER 26 NON VOLATILE REGISTER NVR INTERFACE Transition to sleep mode Writing 1 to the sleep bit in the standby control register STBC SLP causes the device to enter sleep mode Release from sleep mode A ...

Page 69: ...ome high impedance a pin is pulled up if the pull up resistor connection for that pin is selected in the pull up register Release from stop mode The device is released from stop mode by a reset or an external interrupt In any clock mode if the hardware watchdog timer is enabled in standby mode by the non volatile register function the sub CR clock does not stop and the watchdog timer and the watch...

Page 70: ... from stop mode by an interrupt a peripheral function having transited to stop mode during operation resumes operating from the point at which it transited to stop mode Therefore some settings of that peripheral function such as the initial interval time of the interval timer become undefined Initialize that peripheral function if necessary after releasing the device from stop mode ...

Page 71: ...ILE REGISTER NVR INTERFACE Transition to time base timer mode If the clock mode monitor bits in the system clock control register SYCC SCM 2 0 are 0b010 0b110 or 0b111 writing 1 to the watch bit in the standby control register STBC TMD causes the device to transit to time base timer mode The device can transit to time base timer mode only when the clock mode is main clock mode main CR clock mode o...

Page 72: ...mode by an interrupt a peripheral function having transited to time base timer mode during operation resumes operating from the point at which it transited to time base timer mode Therefore some settings of that peripheral function such as the initial interval time of the interval timer become undefined Initialize that peripheral function if necessary after releasing the device from time base time...

Page 73: ...o watch mode The device can transit to watch mode only when the clock mode is subclock mode or sub CR clock mode After the device transits to watch mode if the pin state setting bit in the standby control register STBC SPL is 0 the states of the external pins are kept if the SPL bit is 1 the states of the external pins become high impedance a pin is pulled up if the pull up resistor connection for...

Page 74: ...and Ceramic Oscillators Using external clock As shown in Figure 3 6 2 connect the external clock to the X0 pin while leaving the X1 pin unconnected or supplying inverted clock of the X0 pin to the X1 pin refer to the device data sheet To supply clock signals to the subclock from an external clock connect that external clock to the X0A pin while leaving the X1A pin unconnected Figure 3 6 2 Sample C...

Page 75: ...e CPU operates and from the count clock FCH 27 FCH 28 FCRH 26 FCRH 27 FMCRPLL 26 or FMCRPLL 27 output from the time base timer The count clock source is a clock whose frequency is divided by the prescaler or a buffered clock The peripheral functions listed below use the clock whose frequency is divided by the prescaler as the count clock source The prescaler has no control register and always oper...

Page 76: ...H 26 FCRH 27 FMCRPLL 26 or FMCRPLL 27 and supplies it to peripheral functions Input Clock The prescaler uses the machine clock or the output clock of the time base timer as the input clock Output Clock The prescaler supplies clocks to the following peripheral functions 8 16 bit composite timer 8 10 bit A D converter 8 16 bit PPG 16 bit PPG timer 16 bit reload timer UART SIO dedicated baud rate gen...

Page 77: ... from the time base timer are being supplied Table 3 9 1 Table 3 9 2 and Table 3 9 3 list the count clock sources generated by the prescaler Table 3 9 1 Count Clock Sources Generated by Prescaler FCH Count clock source frequency Frequency FCH 20 MHz MCLK 10 MHz Frequency FCH 32 MHz MCLK 16 MHz Frequency FCH 32 5 MHz MCLK 16 25 MHz MCLK 2 5 MHz 8 MHz 8 125 MHz MCLK 4 2 5 MHz 4 MHz 4 0625 MHz MCLK 8...

Page 78: ...y FMCRPLL 8 MHz MCLK 8 MHz Frequency FMCRPLL 10 MHz MCLK 10 MHz Frequency FMCRPLL 12 MHz MCLK 12 MHz Frequency FMCRPLL 16 MHz MCLK 16 MHz MCLK 2 4 MHz 5 MHz 6 MHz 8 MHz MCLK 4 2 MHz 2 5 MHz 3 MHz 4 MHz MCLK 8 1 MHz 1 25 MHz 1 5 MHz 2 MHz MCLK 16 0 5 MHz 0 625 MHz 0 75 MHz 1 MHz MCLK 32 0 25 MHz 0 3125 MHz 0 375 MHz 0 5 MHz FMCRPLL 26 125 kHz 156 25 kHz 187 5 kHz 0 25 MHz FMCRPLL 27 62 5 kHz 78 125...

Page 79: ...ral resource is started an error of up to one cycle of the clock source captured by that peripheral resource will occur depending on the output value of the prescaler Figure 3 10 1 Clock Capture Error Occurring Immediately after a Peripheral Function Starts The prescaler count value affects the following peripheral functions 8 16 bit composite timer 8 10 bit A D converter 8 16 bit PPG 16 bit PPG t...

Page 80: ...MB95630H Series 60 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 3 CLOCK CONTROLLER 3 10 Notes on Using Prescaler ...

Page 81: ...MN702 00009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 61 CHAPTER 4 RESET This section describes the reset operation 4 1 Reset Operation 4 2 Register 4 3 Notes on Using Reset ...

Page 82: ...essary for initializing the internal circuit In order to operate with the external clock external clock signals must be input However the external pins including I O ports and peripheral functions are reset asynchronously In addition there is a standard value of the pulse width for external reset input If the value is below the standard value a reset signal may not be accepted The standard value i...

Page 83: ...e of the RAM access protection function lengthens according to the number of machine clock cycles selected before a reset When a reset occurs with the sub CR clock oscillation stabilization bit in the system clock control register 2 SYCC2 SCRDY set to 1 the device is released from the reset state after the main CR clock oscillation stabilization wait time elapses When a reset occurs with the sub C...

Page 84: ...function prevents a word data write operation from being interrupted by a reset while data of two bytes is being written Software reset Watchdog reset External reset input Power on reset low voltage delection reset Released from external reset Sub CR clock oscillation stabilization wait time reset state Sub CR clock oscillation stabilization wait time reset state Sub CR clock oscillation stabiliza...

Page 85: ...pheral resource pin remains high impedance until the setting of that I O port or that peripheral resource pin by software is executed after the reset is released Note Connect a pull up resistor to a pin that becomes high impedance during a reset to prevent the device from malfunctioning For details of the states of all pins during a reset refer to the device data sheet ...

Page 86: ... LIMITED MN702 00009 1v0 E CHAPTER 4 RESET 4 2 Register 4 2 Register This section provides details of the register for reset Table 4 2 1 List of Register for Reset Register abbreviation Register name Reference RSRR Reset source register 4 2 1 ...

Page 87: ...ite access writing 0 or 1 to this bit sets it to 0 bit2 PONR Power on reset flag bit When this bit is set to 1 that indicates a power on reset or a low voltage detection reset optional has occurred When any other reset occurs this bit retains the value that has existed before such reset occurs The circuit is only available on certain products Check the availability of the circuit in the device dat...

Page 88: ...t to 0 bit0 SWR Software reset flag bit When this bit is set to 1 that indicates a software reset has occurred When a hardware reset occurs the bit retains the value that has existed before the hardware reset occurs This bit reads 0 when read by a read access A write access writing 0 or 1 to this bit or a power on reset sets it to 0 Note Since reading the reset source register clears its contents ...

Page 89: ...s set to 1 that indicates a power on reset or low voltage detection reset optional has occurred HWR When this bit is set to 1 that indicates one of the following reset has occurred an external reset a watchdog reset a power on reset or a low voltage detection reset optional SWR When this bit is set to 1 that indicates that a software reset has occurred Table 4 2 2 State of Reset Source Register Re...

Page 90: ...et Notes on Using Reset Initialization of registers and bits by reset source Some registers and bits are initialized only by a certain reset source The type of reset source determines which bit in the reset source register RSRR is to be initialized The oscillation stabilization wait time setting register WATR of the clock controller can only be initialized by a power on reset ...

Page 91: ...MN702 00009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 71 CHAPTER 5 INTERRUPTS This chapter describes the interrupts 5 1 Interrupts ...

Page 92: ...ed in standby mode and resumes executing instructions Interrupt Requests from Peripheral Functions When the CPU receives an interrupt request it branches to the interrupt service routine with the interrupt vector table address corresponding to the interrupt request as the address of the branch destination The priority of each interrupt request in interrupt processing can be set to one of the four ...

Page 93: ...evel 0 to 3 in interrupt processing ILR0 bit 7 6 5 4 3 2 1 0 Field L03 1 0 L02 1 0 L01 1 0 L00 1 0 Attribute R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 ILR1 bit 7 6 5 4 3 2 1 0 Field L07 1 0 L06 1 0 L05 1 0 L04 1 0 Attribute R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 ILR2 bit 7 6 5 4 3 2 1 0 Field L11 1 0 L10 1 0 L09 1 0 L08 1 0 Attribute R W R W R W R W R W R...

Page 94: ...est is 3 the CPU ignores that interrupt request Table 5 1 1 shows the relationships between interrupt level setting bits and interrupt levels While the main program is being executed the interrupt level bits in the condition code register CCR IL 1 0 are 0b11 Table 5 1 1 Relationships Between Interrupt Level Setting Bits and Interrupt Levels LXX 1 0 Interrupt level Priority 00 0 Highest 01 1 10 2 1...

Page 95: ...of the same interrupt level made simultaneously and the evaluation of the interrupt enable flag CCR I Figure 5 1 1 shows the interrupt processing Figure 5 1 1 Interrupt Processing Interrupt from peripheral resource Peripheral resource interrupt request output enabled Determine interrupt priority and transfer interrupt level to CPU Compare interrupt level with IL bit in PS START Run main program Re...

Page 96: ...ade If there are interrupt requests having the same interrupt level their positions in the priority order are also compared in the interrupt controller 5 If the interrupt level received has priority over smaller interrupt level number the level set in the interrupt level bits CCR IL 1 0 in the condition code register the CPU checks the content of the interrupt enable flag CCR I and accepts the int...

Page 97: ...the interrupt level bits in the condition code register CCR IL 1 0 hold the same value as that of the interrupt level setting registers ILR0 to ILR5 corresponding to the timer interrupt level 2 in this example If an interrupt request whose interrupt level has priority over the interrupt level of the timer interrupt level 1 in the example is made that interrupt is processed first To temporarily dis...

Page 98: ...me reaches its maximum when an interrupt request occurs immediately after the CPU starts executing the DIVU instruction whose execution cycle is the longest 17 machine clock cycles Interrupt handling time After accepting an interrupt the CPU requires nine machine clock cycles to perform the following interrupt processing setup Saves the value of the program counter PC and that of the program statu...

Page 99: ... CPU executes the interrupt return instruction RETI at the end of interrupt processing it restores from the stack the value of the program status PS first and that of the program counter PC which is opposite to the sequence of saving the two values to the stack After the restoration both PS and PC return to their states before the start of interrupt processing Note Since the value of the accumulat...

Page 100: ...s and make the data area start from the smallest RAM address Figure 5 1 5 shows an example of setting the interrupt processing stack area Figure 5 1 5 Example of Setting Interrupt Processing Stack Area Note The stack area is utilized by interrupts sub routine calls the PUSHW instruction etc in descending order of addresses It is released by return instructions RETI RET the POPW instruction etc in ...

Page 101: ...MN702 00009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 81 CHAPTER 6 I O PORT This chapter describes the configuration and operations of the I O port 6 1 Overview 6 2 Configuration and Operations ...

Page 102: ...ng products For the exact number of I O ports on a product refer to the device data sheet In this chapter x represents the port number in a register name For details of register names and their respective abbreviations of a product refer to the device data sheet Table 6 1 1 lists the registers for each port Refer to I O MAP in the device data sheet for the availability of the A D input disable reg...

Page 103: ...operations as a general purpose I O port For details of peripheral functions see their respective chapters Configuration of I O Port An I O port is made up of the following elements General purpose I O pins peripheral function I O pins Port x data register PDRx Port x direction register DDRx Port x pull up register PULx A D input disable register upper AIDRH A D input disable register lower AIDRL ...

Page 104: ...t as an input port Reading the PDRx register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRx register the PDRx register value is returned Operation as a peripheral function output pin A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function correspond...

Page 105: ...hat of the peripheral function I O remains unchanged and the output level is maintained Operation as an analog input pin Set the bit in the DDRx register corresponding to the analog input pin to 0 and the bit corresponding to that pin in the AIDRH AIDRL register to 0 For a pin shared with other peripheral functions disable the output of such peripheral functions In addition set the corresponding b...

Page 106: ...MB95630H Series 86 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 6 I O PORT 6 2 Configuration and Operations ...

Page 107: ...TED 87 CHAPTER 7 TIME BASE TIMER This chapter describes the functions and operations of the time base timer 7 1 Overview 7 2 Configuration 7 3 Interrupt 7 4 Operations and Setting Procedure Example 7 5 Register 7 6 Notes on Using Time base Timer ...

Page 108: ... The length of an interval time can be selected from the following 16 types Table 7 1 1 shows the interval times available for the time base timer 1 FCH 4 MHz 2 FCH 0 5 μs 2 FCRH 4 MHz 1 FCRH 0 25 μs 3 FMCRPLL 8 MHz PLL multiplier 2 FCRH PLL multiplier 4 MHz 2 8 MHz 1 FMCRPLL 0 125 μs Table 7 1 1 Interval Times of Time base Timer Interval time if the main clock is used Interval time if the main CR...

Page 109: ... Time base timer counter Counter clear To prescaler To software watchdog timer Counter clear circuit Interval timer selector Time base timer control register TBTC Resets Software watchdog timer clear Time base timer interrupt FCH FCRH FCRH FCH divided by 2 System clock control register SYCC SCM2 SCM1 SCM0 SCS2 SCS1 SCS0 DIV1 DIV0 TBIF TBIE TBC3 TBC2 TBC1 TBC0 TCLR Main CR clock Main clock FMCRPLL ...

Page 110: ... timer selector This circuit selects one bit out of 16 bits in the 24 bits of the time base timer counter as the interval timer Time base timer control register TBTC This register selects the interval time clears the counter controls interrupts and checks the state of the time base timer Input Clock The time base timer uses the main clock divided by two or the main CR clock or the main CR PLL cloc...

Page 111: ... generated to the interrupt controller Regardless of the value of the TBIE bit the TBIF bit is set to 1 when the selected bit underflows With the TBIF bit having been set to 1 if the TBIE bit is changed from the disable state to the enable state 0 1 an interrupt request is generated immediately The TBIF bit will not be set to 1 if the counter is cleared TBTC TCLR 1 at the same time as the time bas...

Page 112: ...omes 1 In other words an interrupt request is generated at each interval time selected based on the time when the counter was last cleared Clearing Time base Timer With the output of the time base timer being used in other peripheral functions clearing the time base timer affects their operations in various ways such as changing the count time of a peripheral function When clearing the counter by ...

Page 113: ... cleared and the main clock stops Figure 7 4 2 Operations of Time base Timer TBIF bit TBIE bit 2 SLP bit STBC register 3 STP bit STBC register Counter value count down 0x000000 Oscillation stabilization wait time 1 Power on reset Interval cycle 0xFFFFFF Sleep Stop Stop mode released by external interrupt When setting the interval time select bits in time base timer control register TBTC TBC 3 0 to...

Page 114: ...gs 1 Set the interrupt level ILR 2 Set the interval time TBTC TBC 3 0 3 Enable interrupts and clear the interrupt request flag TBTC TBIE 1 TBTC TBIF 0 4 Clear the counter TBTC TCLR 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the device data sheet Processing interrupts 1 Clear the interrupt request fla...

Page 115: ... LIMITED 95 CHAPTER 7 TIME BASE TIMER 7 5 Register 7 5 Register This section describes the register of the time base timer Table 7 5 1 List of Time base Timer Register Register abbreviation Register name Reference TBTC Time base timer control register 7 5 1 ...

Page 116: ... instruction this bit always returns 1 bit6 TBIE Time base timer interrupt request enable bit This bit enables or disables output of interrupt requests to interrupt controller When this bit and the time base timer interrupt request flag bit TBIF are set to 1 a time base timer interrupt request is output bit5 Undefined bit The read value is always 0 Writing a value to this bit has no effect on oper...

Page 117: ...212 1 FMCRPLL 512 µs Writing 0110 213 2 FCH 4 096 ms 213 1 FCRH 2 048 ms 213 1 FMCRPLL 1 024ms Writing 0010 214 2 FCH 8 192 ms 214 1 FCRH 4 096 ms 214 1 FMCRPLL 2 048 ms Writing 0111 215 2 FCH 16 384 ms 215 1 FCRH 8 192 ms 215 1 FMCRPLL 4 096 ms Writing 0011 216 2 FCH 32 768 ms 216 1 FCRH 16 384 ms 216 1 FMCRPLL 8 192 ms Writing 1000 217 2 FCH 65 536 ms 217 1 FCRH 32 768 ms 217 1 FMCRPLL 16 384 ms...

Page 118: ... base timer is selected as the count clock of the software watchdog timer WDTC CS 1 0 0b00 or 0b01 clearing the time base timer also clears the software watchdog timer Peripheral functions receiving clock from time base timer In the mode where the source oscillation of the main clock is stopped the counter is cleared and the time base timer stops operating In addition if the counter of the time ba...

Page 119: ...TED 99 CHAPTER 8 HARDWARE SOFTWARE WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer 8 1 Overview 8 2 Configuration 8 3 Operations and Setting Procedure Example 8 4 Register 8 5 Notes on Using Watchdog Timer ...

Page 120: ...x0FEB 0x0FEC In the case of software activation software watchdog the watchdog timer register WDTC must be set to start the watchdog timer function In the case of hardware activation hardware watchdog the watchdog timer starts automatically after a reset It can also stop or run in stop mode according to the values at the addresses 0xFFBE and 0xFFBF on the Flash memory which are copied to the watch...

Page 121: ...E1 Count clock selector Watchdog timer clear selector Counter clear control circuit Reset control circuit Reset signal Clear signal from time base timer Clear signal from watch prescaler Sleep mode starts Stop mode starts Time base timer watch mode starts FCH FCL 214 FCL or 213 FCRL 213 FCL or 212 FCRL Watch prescaler output 221 FCH or 220 FCRH or 220 FMCRPLL 220 FCH or 219 FCRH or 219 FMCRPLL Tim...

Page 122: ...circuit This circuit generates a reset signal when the watchdog timer counter overflows Watchdog timer clear selector This selector selects the watchdog timer clear signal Counter clear control circuit This circuit controls the clearing and stopping of the watchdog timer counter Watchdog timer control register WDTC This register performs setup for activating clearing the watchdog timer counter as ...

Page 123: ...ation after a reset is released CS 1 0 and CSP bits are read only bits fixed at 0b001 The counter of the watchdog timer is cleared by a reset and the watchdog timer resumes its operation after the reset is released Clearing the watchdog timer When the counter of the watchdog timer is not cleared within the interval time it overflows allowing the watchdog timer to generate a watchdog reset The coun...

Page 124: ...og timer Figure 8 3 1 shows the correlation between the timing of clearing the watchdog timer and the interval time when the time base timer output FCH 221 FCH main clock is selected as the count clock main clock 4 MHz Figure 8 3 1 Clearing Timing and Interval Time of Watchdog Timer Operation in subclock mode When a watchdog reset is generated in subclock mode the timer starts operating in main cl...

Page 125: ...re watchdog timer 1 Write any value except 0xA596 to the addresses 0xFFBE and 0xFFBF on the Flash memory After a reset the data in 0xFFBE and 0xFFBF on the Flash memory are copied to the watchdog timer selection ID register upper lower WDTH WDTL 0x0FEB 0x0FEC Writing 0xA597 to the addresses 0xFFBE and 0xFFBF on the Flash memory enables the hardware watchdog timer except in standby modes writing an...

Page 126: ...v0 E CHAPTER 8 HARDWARE SOFTWARE WATCHDOG TIMER 8 4 Register 8 4 Register This section describes the register of the watchdog timer Table 8 4 1 List of Watchdog Timer Register Register abbreviation Register name Reference WDTC Watchdog timer control register 8 4 1 ...

Page 127: ...d to confirm the start stop of the hardware watchdog timer bit 7 6 5 4 3 2 1 0 Field CS1 CS0 CSP HWWDT WTE3 WTE2 WTE1 WTE0 Attribute and initial values for software watchdog timer Attribute R W R W R W R W W W W Initial value 0 0 0 0 0 0 0 0 Attribute and initial values for hardware watchdog timer Attribute R R R R W W W W Initial value 0 0 1 1 0 0 0 0 bit7 bit6 bit5 Details FCH main clock FCRH ma...

Page 128: ...he watchdog timer in the first write access after a reset or clears it from the second write access after a reset In the case of activating the watchdog timer Writing 0101 to these bits in the first write access after a reset starts the software watchdog timer In the case of clearing the watchdog timer Writing 0101 to these bits in the first write access or later after a reset clears the hardware ...

Page 129: ...hdog timer Clearing the timer time base timer or watch prescaler or sub CR timer used as the count clock of the watchdog timer also clears the counter of the watchdog timer The counter of the watchdog timer is cleared when the watchdog timer transits to sleep mode stop mode time base timer mode or watch mode except in the case of activating hardware watchdog timer whose operation in standby mode h...

Page 130: ...MB95630H Series 110 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 8 HARDWARE SOFTWARE WATCHDOG TIMER 8 5 Notes on Using Watchdog Timer ...

Page 131: ...TED 111 CHAPTER 9 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler 9 1 Overview 9 2 Configuration 9 3 Interrupt 9 4 Operations and Setting Procedure Example 9 5 Register 9 6 Notes on Using Watch Prescaler ...

Page 132: ...ub CR clock divided by two as its count clock The counter of the watch prescaler counts down and an interrupt request is generated whenever the selected interval time has elapsed The interval time can be selected from the following eight types Table 9 1 1 shows the interval times of the watch prescaler 1 2 FCRL 20 µs when FCRL 100 kHz 2 2 FCL 61 035 µs when FCL 32 768 kHz Note Refer to the device ...

Page 133: ...Prescaler Figure 9 2 1 Block Diagram of Watch Prescaler Counter clear circuit Interval timer selector WTIF WTIE WTC1 WTC0 WCLR Watch prescaler counter counter Watch prescaler control register WPCR Resets or stops subclock oscillation or sub CR clock oscillation Interrupt of watch prescaler Watchdog timer clear FCL divided by 2 FCRL divided by 2 FCL Subclock FCRL Sub CR clock Counter clear Software...

Page 134: ...the watch prescaler Interval timer selector This circuit selects one out of the eight bits used for the interval timer among 17 bits available in the watch prescaler counter Watch prescaler control register WPCR This register selects the interval time clears the counter controls interrupts and checks the status Input Clock The watch prescaler uses the subclock divided by two or the sub CR clock di...

Page 135: ...interrupt request is output from the watch prescaler to the interrupt controller Regardless of the value in the WTIE bit the WTIF bit is set to 1 as soon as the time set by the watch interrupt interval time select bits has elapsed When the WTIF bit is set to 1 changing the WTIE bit from the disable state to the enable state WPCR WTIE 0 1 immediately generates an interrupt request The WTIF bit will...

Page 136: ...he output of the watch prescaler is selected as the count clock clearing the watch prescaler also clears the watchdog timer The watch prescaler is cleared not only by the watch prescaler clear bit WPCR WCLR but also when the subclock or the sub CR clock is stopped and the oscillation stabilization wait time is necessary The watch prescaler is cleared in the following situations When the device tra...

Page 137: ...TIF bit WTIE bit 2 SLP bit STBC register 3 STP bit STBC register Counter value count down 0x0000 Oscillation stabilization wait time 1 Power on reset Interval time WPCR WTC 2 0 0b011 0xFFFF Sleep Stop Sleep mode released by watch interrupt Stop mode released by external interrupt When setting interval time select bits in the watch prescaler control register WPCR WTC 2 0 to 0b011 2 14 2 FCL Count v...

Page 138: ...gs 1 Set the interrupt level ILR 2 Set the interval time WPCR WTC 2 0 3 Enable interrupts and clear the interrupt request flag WPCR WTIE 1 WPCR WTIF 0 4 Clear the counter WPCR WCLR 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the device data sheet Processing interrupts 1 Clear the interrupt request fla...

Page 139: ...LIMITED 119 CHAPTER 9 WATCH PRESCALER 9 5 Register 9 5 Register This section describes the register of the watch prescaler Table 9 5 1 List of Watch Prescaler Register Register abbreviation Register name Reference WPCR Watch prescaler control register 9 5 1 ...

Page 140: ... write RMW type of instruction this bit always returns 1 bit6 WTIE Watch prescaler interrupt request enable bit This bit enables or disables output of interrupt requests to interrupt controller When this bit and the watch prescaler interrupt request flag bit WTIF are set to 1 a watch prescaler interrupt request is output bit5 4 Undefined bits Their read values are always 0 Writing values to these ...

Page 141: ... clears the software watchdog timer bit3 1 Details Interval time Subclock FCL 32 768 kHz Interval time Sub CR clock FCRL 100 kHz Writing 100 210 2 FCL 62 5 ms 210 2 FCRL 20 48 ms Writing 000 211 2 FCL 125 ms 211 2 FCRL 40 96 ms Writing 001 212 2 FCL 250 ms 212 2 FCRL 81 92 ms Writing 010 213 2 FCL 500 ms 213 2 FCRL 163 84 ms Writing 011 214 2 FCL 1 s 214 2 FCRL 327 68 ms Writing 101 215 2 FCL 2 s ...

Page 142: ...aler also clears the software watchdog timer Watch prescaler interrupts In stop mode in which the main clock the main CR clock or the main CR PLL clock is used the watch prescaler performs counting and can generate the watch prescaler interrupt Peripheral functions receiving clock from the watch prescaler If the counter of the watch prescaler is cleared when the output of the watch prescaler is us...

Page 143: ...CTOR LIMITED 123 CHAPTER 10 WILD REGISTER FUNCTION This chapter describes the functions and operations of the wild register function 10 1 Overview 10 2 Configuration 10 3 Operations 10 4 Registers 10 5 Typical Hardware Connection Example ...

Page 144: ...ster Function The wild register consists of three wild register data setting registers three wild register address setting registers a 1 byte address compare enable register and a 1 byte wild register data test setting register If addresses and data that are to be modified are set to these registers ROM data can be replaced with modification data set in the registers Data of up to three different ...

Page 145: ...ster address compare enable register WREN Wild register data test setting register WROR Control circuit block Block Diagram of Wild Register Function Figure 10 2 1 Block Diagram of Wild Register Function Access control circuit Address compare circuit Decoder and logic control circuit Wild register address compare enable register WREN Wild register data test setting register WROR Wild register data...

Page 146: ...placed The wild register address compare enable register WREN enables the wild register function for each wild register data setting register WRDR In addition the wild register data test setting register WROR enables the normal read function for each wild register data setting register WRDR Control circuit block This circuit compares the actual address data with addresses set in the wild register ...

Page 147: ...ress 0x0078 Since the address 0x0078 is used as a mirror address for the register bank pointer and the direct bank pointer this address cannot be patched Table 10 3 1 Procedure for Setting Registers of Wild Register Function Step Operation Operation example 1 Read replacement data from a peripheral function outside through a certain communication method Suppose the built in ROM code to be modified...

Page 148: ... data setting register 0 10 4 1 WRDR1 Wild register data setting register 1 10 4 1 WRDR2 Wild register data setting register 2 10 4 1 WRAR0 Wild register address setting register 0 10 4 2 WRAR1 Wild register address setting register 1 10 4 2 WRAR2 Wild register address setting register 2 10 4 2 WREN Wild register address compare enable register 10 4 3 WROR Wild register data test setting register ...

Page 149: ...ned by the wild register address setting register WRAR Data is valid at an address corresponding to one of the wild register numbers The read access to one of these bits is enabled only when the data test setting bit in the wild register data test setting register WROR corresponding to the bit to be read is set to 1 WRDR0 bit 7 6 5 4 3 2 1 0 Field RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Attribute R W R W ...

Page 150: ...ng register WRAR0 bit 15 14 13 12 11 10 9 8 Field RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 Field RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 WRAR1 bit 15 14 13 12 11 10 9 8 Field RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 Attribute R W R W R W R W R W R W ...

Page 151: ...ways 0 Writing values to these bits has no effect on operation bit5 3 Reserved bits Always set these bits to 0 bit2 0 EN 2 0 Wild register address compare enable bits These bits enable or disable the operation of the wild register EN0 corresponds to wild register number 0 EN1 corresponds to wild register number 1 EN2 corresponds to wild register number 2 bit 7 6 5 4 3 2 1 0 Field Reserved Reserved...

Page 152: ...no effect on operation bit5 3 Reserved bits Always set these bits to 0 bit2 0 DRR 2 0 Wild register data test setting bits These bits enable or disable the normal reading from the corresponding data setting register of the wild register DRR0 corresponds to wild register number 0 DRR1 corresponds to wild register number 1 DRR2 corresponds to wild register number 2 bit 7 6 5 4 3 2 1 0 Field Reserved...

Page 153: ...cal Hardware Connection Example 10 5 Typical Hardware Connection Example Below is an example of typical hardware connection for the application of the wild register function Hardware Connection Example Figure 10 5 1 Typical Hardware Connection Example E2 PROM Storing correction program SO SI SCK SIN SOT SCK MCU ...

Page 154: ...MB95630H Series 134 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 10 WILD REGISTER FUNCTION 10 5 Typical Hardware Connection Example ...

Page 155: ...Operation of Interval Timer Function One shot Mode 11 7 Operation of Interval Timer Function Continuous Mode 11 8 Operation of Interval Timer Function Free run Mode 11 9 Operation of PWM Timer Function Fixed cycle mode 11 10 Operation of PWM Timer Function Variable cycle Mode 11 11 Operation of PWC Timer Function 11 12 Operation of Input Capture Function 11 13 Operation of Noise Filter 11 14 Regis...

Page 156: ...d the counter counts from 0x00 again The timer outputs square wave as a result of this repeated operation Interval Timer Function Free run Mode When the interval timer function free run mode is selected the counter starts counting from 0x00 When the counter value matches the value of the 8 16 bit composite timer data register the timer output is inverted and an interrupt request occurs Under these...

Page 157: ...terrupt Input Capture Function When the input capture function is selected the counter value is stored in a register immediately after the detection of an edge of an external input signal This function is available in either free run mode or clear mode for count operation In clear mode the counter starts counting from 0x00 and transfers its value to a register to generate an interrupt after an edg...

Page 158: ...ster 0 Tn0CR0 Tn1CR0 8 16 bit composite timer status control register 1 Tn0CR1 Tn1CR1 8 16 bit composite timer timer mode control register TMCRn Output controller Control logic Count clock selector Edge detector Noise filter The number of pins and that of channels of the 8 16 bit composite timer vary among products For details refer to the device data sheet In this chapter n in a pin name and a re...

Page 159: ...bit composite timer data register value 8 bit counter 8 bit comparator 8 bit data register Count clock selector Count clock selector Edge detector Output controller 8 bit counter 8 bit comparator 8 bit data register Output controller Control logics Control logics Timer n1 IRQ logic IRQXX Timer output Timer output 16 bit mode clock Tn0CR0 Tn0CR1 Tn1CR1 Tn1CR0 TOn0 ECn0 TOn1 ENn0 ENn1 IRQXX 16 bit m...

Page 160: ...oller controls timer output The timer output is supplied to the external pin when the pin output has been enabled Control logic The control logic controls timer operation Count clock selector The selector selects the counter operating clock signal from different prescaler output signals divided machine clock signal and time base timer output signal Edge detector The edge detector selects the edge ...

Page 161: ... 8 16 bit composite timer Channel of 8 16 bit Composite Timer On a channel there are two 8 bit counters They can be used as two 8 bit timers or one 16 bit timer The following table lists the external pins on a channel Table 11 3 1 External Pins of 8 16 bit Composite Timer Pin name Pin function TOn0 Timer n0 output TOn1 Timer n1 output ECn Timer n0 input and timer n1 input ...

Page 162: ...ion variable cycle mode or input capture function in use the output becomes undetermined ECn pin The ECn pin is connected to the ECn0 and ECn1 internal pins ECn0 internal pin This pin serves as the external count clock input pin for timer n0 when the interval timer function or PWM timer function is selected or as the signal input pin for timer n0 when the PWC timer function or input capture functi...

Page 163: ... cycle mode Overflow in the PWC timer operation or the input capture operation Completion of measurement in the PWC timer operation or edge detection in the input capture operation Interrupt flag Tn0CR1 IF Tn0CR1 IF Tn0CR1 IR Interrupt enable Tn0CR1 IE and Tn0CR0 IFE Tn0CR1 IE and Tn0CR0 IFE Tn0CR1 IE Table 11 5 2 Timer n1 Interrupt Item Description Interrupt generating source Comparison match in ...

Page 164: ... selected count clock signal When the counter value matches the value of the 8 16 bit composite timer data register Tn0DR Tn1DR the timer output TMCRn TO0 TO1 is inverted the interrupt flag Tn0CR1 Tn1CR1 IF is set to 1 the timer operation enable bit Tn0CR1 Tn1CR1 STA is set to 0 and the counter stops counting The value of the 8 16 bit composite timer data register Tn0DR Tn1DR is transferred to the...

Page 165: ...er value 0xFF 0x80 0x00 Timer cycle Cleared by program Time IF bit STA bit Tn0DR Tn1DR value 0xFF Timer output pin Automatically cleared Reactivated Inverted For initial value 1 on activation If the Tn0DR Tn1DR data register value is modified during operation the new value is used from the next active cycle Automatically cleared Automatically cleared Reactivated Reactivated with output initial val...

Page 166: ...lue in the 8 16 bit composite timer data register Tn0DR Tn1DR the timer output bit TMCRn TO0 TO1 is inverted the interrupt flag Tn0CR1 Tn1CR1 IF is set to 1 and the counter returns to 0x00 and restarts counting The timer outputs square wave as a result of this continuous operation The value of the 8 16 bit composite timer data register Tn0DR Tn1DR is transferred to the temporary storage latch comp...

Page 167: ...0DR Tn1DR value 0xE0 Cleared by program Time IF bit STA bit Counter clear 2 Timer output pin 1 If the Tn0DR Tn1DR data register value is modified during operation the new value is used from the next active cycle 0xE0 Compare value 0xE0 Activated Matched Matched Matched Matched Matched 2 The counter is cleared and the data register settings are loaded into the comparison data latch whenever a match...

Page 168: ...te timer data register Tn0DR Tn1DR the timer output bit TMCRn TO0 TO1 is inverted and the interrupt flag Tn0CR1 Tn1CR1 IF is set to 1 If the counter continues to count with the above settings and then reaches 0xFF it returns to 0x00 and restarts counting The timer outputs square wave as a result of this continuous operation The value of the 8 16 bit composite timer data register Tn0DR Tn1DR is tra...

Page 169: ...tion Diagram of Interval Timer Function Free run Mode Counter value 0xFF 0x80 0x00 Tn0DR Tn1DR value 0xE0 Cleared by program Time IF bit STA bit Counter value match Timer output pin 0xE0 0xE0 Activated Matched Matched Even though a match is detected during operation the counter is not cleared The data register settings are reloaded into the comparison data latch Matched Matched ...

Page 170: ...the value in the 8 16 bit composite timer data register Tn0DR Tn1DR This function has no effect on the interrupt flag Tn0CR1 Tn1CR1 IF Since each cycle always starts with H pulse output the timer output initial value setting bit Tn0CR1 Tn1CR1 SO has no effect on operation The value of the 8 16 bit composite timer data register Tn0DR Tn1DR is transferred to the temporary storage latch comparison da...

Page 171: ...0DR Tn1DR register value 0x00 duty ratio 0 Counter value H L H L H L 0x00 Counter value Counter value PWM waveform PWM waveform PWM waveform Tn0DR Tn1DR register value 0x80 duty ratio 50 Tn0DR Tn1DR register value 0xFF duty ratio 99 6 0x80 One count width Note When the PWM function has been selected the timer output pin holds the level at the point when the counter stops Tn0CR1 Tn1CR1 STA 0 0x00 0...

Page 172: ...tput the timer initial value setting bit Tn0CR1 Tn1CR1 SO has no effect on operation An interrupt flag Tn0CR1 Tn1CR1 IF is set when the 8 bit counter corresponding to that interrupt flag matches the value in its corresponding 8 16 bit composite timer data register Tn0DR Tn1DR The 8 16 bit composite timer data register value is transferred to the temporary storage latch comparison data storage latc...

Page 173: ...eform PWM waveform Tn0DR register value 0x80 Tn1DR register value 0x80 duty ratio 0 0xFF 0x00 0x80 0x00 0x00 0x80 0x00 0x80 0x00 0x00 0x80 0x00 Counter timer n1 value Counter timer n0 value Counter timer n1 value 0x00 0x00 0x00 0x80 0x00 0x00 0x80 0x00 0x40 0x40 Counter timer n0 value Counter timer n1 value 0x00 0x00 One count width timer n0 value timer n1 value Tn0DR register value 0x40 Tn1DR reg...

Page 174: ...xt measurement result is lost since the count value has not been transferred to the 8 16 bit composite timer data register There is an exception With the F3 bit to F0 bit in the Tn0CR0 Tn1CR0 register having been set to 1001B even though the BF bit is set to 1 the H pulse measurement result is transferred to the 8 16 bit composite timer data register while the cycle measurement result is not trans...

Page 175: ...ation of PWC Timer Function Figure 11 11 2 Operation Diagram of PWC Timer Example of H pulse Width Measurement Pulse input Input waveform to PWC pin Counter value 0xFF STA bit IR bit BF bit H width Counter operation Time Cleared by program Data transferred from counter to Tn0DR Tn1DR T0nDR Tn1DR data register read ...

Page 176: ...transferred to the 8 16 bit composite timer data register Tn0DR Tn1DR the interrupt flag Tn0CR1 Tn1CR1 IR is set to 1 and the counter returns to 0x00 and restarts counting In free run mode when an edge is detected the counter value is transferred to the 8 16 bit composite timer data register Tn0DR Tn1DR and the interrupt flag Tn0CR1 Tn1CR1 IR is set to 1 In this case the counter continues to count...

Page 177: ...es on Using 8 16 bit Composite Timer for notes on using the input capture function Figure 11 12 2 Operating Diagram of Input Capture Function 0xFF 0xBF 0x7F 0x9F 0x3F 0x3F 0x9F Counter free run mode Counter clear mode 0xBF 0x7F Capture value in Tn0DR Tn1DR Falling edge of capture Rising edge of capture External input Falling edge of capture Rising edge of capture ...

Page 178: ...used to eliminate the pulse noise of the signal from the external input pin ECn H pulse noise L pulse noise or H L pulse noise elimination can be selected by the FE11 FE10 FE01 and FE00 bits in the TMCRn register The maximum pulse width that can be eliminated is three machine clock cycles If the noise filter function is activated the signal input will be delayed for four machine clock cycles Figur...

Page 179: ...on Register name Reference Tn0CR0 8 16 bit composite timer n0 status control register 0 11 14 1 Tn1CR0 8 16 bit composite timer n1 status control register 0 11 14 1 Tn0CR1 8 16 bit composite timer n0 status control register 1 11 14 2 Tn1CR1 8 16 bit composite timer n1 status control register 1 11 14 2 TMCRn 8 16 bit composite timer timer mode control register 11 14 3 Tn0DR 8 16 bit composite timer...

Page 180: ...ter Configuration Register Functions bit7 IFE IF flag interrupt enable bit This bit enables or disables IF flag interrupts During timer operation Tn0CR1 Tn1CR1 STA 1 the write access to this bit has no effect on operation Ensure that the timer has stopped before modifying this bit With this bit set to 1 an IF flag interrupt request is output when both the IE bit Tn0CR1 Tn1CR1 IE and the IF flag Tn...

Page 181: ...eration mode with the bits set to 0b111 When these bits are set to 0b110 the count clock from the time base timer will be used as the count clock Depending on the settings of the SYCC register the count clock from the time base timer can be generated from the main clock the main CR clock or the main CR PLL clock In the case of using the count clock from the time base timer as the count clock reset...

Page 182: ... timer operation Tn0CR1 Tn1CR1 STA 1 bit3 0 Details Writing 0000 Interval timer one shot mode Writing 0001 Interval timer continuous mode Writing 0010 Interval timer free run mode Writing 0011 PWM timer fixed cycle mode Writing 0100 PWM timer variable cycle mode Writing 0101 PWC timer H pulse rising edge to falling edge Writing 0110 PWC timer L pulse falling edge to rising edge Writing 0111 PWC ti...

Page 183: ...ster can be used to enable or disable the timer operation If the STA bit in one of the registers is set to 0 the STA bit in the other one is automatically set to the same value In 16 bit operation TMCRn MOD 1 use the STA bit in the Tn0CR1 timer n0 register to enable or disable timer operation If the STA bit of one of the timers is set to 0 the STA bit in the other one is automatically set to the s...

Page 184: ...er reload overflow flag Tn0CR1 Tn1CR1 IF is 1 However an interrupt request from the timer reload overflow flag Tn0CR1 Tn1CR1 IF is not output unless the IF flag interrupt enable bit Tn0CR0 Tn1CR0 IFE is also set to 1 bit4 IR Pulse width measurement completion edge detection flag This bit indicates the completion of pulse width measurement or the detection of an edge Writing 0 to this bit sets it t...

Page 185: ...xt H pulse The BF bit in the Tn0CR1 timer n0 register is set to 0 when the Tn1DR timer n1 register is read during 16 bit operation The BF bit in the Tn1CR1 timer n1 register is set to 0 during 16 bit operation This bit is 0 when any timer function other than the PWC timer function is selected Writing a value to this bit has no effect on operation bit2 IF Timer reload overflow flag This bit detects...

Page 186: ...lid However in 16 bit operation although a value can be written to the SO bit in the Tn1CR1 timer n1 register even during timer operation the value written has no direct effect on the timer output When the PWM timer function fixed cycle mode or variable cycle mode or the input capture function is in use the value of this bit has no effect on operation bit0 OE Timer output enable bit This bit enabl...

Page 187: ...last value When the timer operating mode select bits Tn0CR0 Tn1CR0 F 3 0 are modified with the timer stopping operating this bit indicates the last value of timer operation if the same timer operation has been performed otherwise it indicates its initial value 0 bit6 TO0 Timer n0 output bit This bit indicates the output value of timer n0 When the timer starts operation Tn0CR1 Tn1CR1 STA 1 the valu...

Page 188: ...Writing 1 to this bit allows timers n0 and n1 to operate as a 16 bit timer While this bit is 1 if the timer starts operating Tn0CR1 Tn1CR1 STA 1 with the PWM timer function variable cycle mode this bit is automatically set to 0 During timer operation Tn0CR1 Tn1CR1 STA 1 the write access to this bit is invalid bit3 2 FE1 1 0 Timer n1 filter function select bits These bits select the filter function...

Page 189: ...tion or the input capture function is selected During timer operation Tn0CR1 STA 1 the write access to these bits is invalid The settings of the bits have no effect on operation when the interval timer function or the PWM timer function is selected the filter function does not operate bit1 0 Details Writing 00 Disables the filter function Writing 01 Filters out H pulse noise Writing 10 Filters out...

Page 190: ...rrent count value can be read from this register An attempt to write 0x00 to this register is disabled in interval timer function In 16 bit operation write the upper timer data to Tn1DR and lower timer data to Tn0DR and write or read Tn1DR first and then Tn0DR PWM timer function fixed cycle The 8 16 bit composite timer data register Tn0DR Tn1DR is used to set H pulse width time When the timer star...

Page 191: ... the BF bit is set to 0 While the BF bit is 1 no data is transferred to the 8 16 bit composite timer data register There is an exception With the F 3 0 bits in the Tn0CR0 Tn1CR0 register having been set to 0b1001 even though the BF bit is set to 1 the H pulse measurement result is transferred to the 8 16 bit composite timer data register while the cycle measurement result is not transferred to the...

Page 192: ...n the internal read buffer at the same time Read from Tn0DR The internal read buffer is read Write to Tn1DR Data is written to the internal write buffer Write to Tn0DR In addition to the write access to Tn0DR the value of the internal write buffer is stored in Tn1DR at the same time Figure 11 14 1 shows the Tn0DR and Tn1DR registers read from and written to during 16 bit operation Figure 11 14 1 R...

Page 193: ...measurement completion edge detection flag Tn0CR1 Tn1CR1 IR will not be set either In counter clear mode the counter will not be cleared at the first falling edge and no data will be transferred to the data register either The 8 16 bit composite timer will start the input capture operation from the next rising edge In counter free run mode no data will be transferred to the data register at the fi...

Page 194: ...interrupt HO bit Stop mode Wake up from sleep mode by interrupt Operation reactivated Operation halts Delay of oscillation stabilization wait time Interval time after wake up from stop mode indeterminate Request ends HO request HO request ends Operation resumes Sleep mode Cleared by program Counter value 0xFF 0x00 Tn0DR Tn1DR value 0xFF Time STA bit PWM timer output pin 0xFF SLP bit STBC register ...

Page 195: ...RRUPT CIRCUIT This chapter describes the functions and operations of the external interrupt circuit 12 1 Overview 12 2 Configuration 12 3 Channels 12 4 Pin 12 5 Interrupt 12 6 Operations and Setting Procedure Example 12 7 Register 12 8 Notes on Using External Interrupt Circuit ...

Page 196: ...rrupt controller Function of External Interrupt Circuit The external interrupt circuit detects any edge of a signal that is input to an external interrupt pin and generates interrupt requests to the interrupt controller The interrupt generated according to this interrupt request can cause the device to wake up from standby mode and return to its normal operating state Therefore the operating mode ...

Page 197: ... input to an external interrupt circuit pin INT matches the polarity of the edge selected in the interrupt control register EIC a corresponding external interrupt request flag bit EIR is set to 1 External interrupt control register EIC This register is used to select an edge enable or disable interrupt requests check for interrupt requests etc EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 External inter...

Page 198: ...ers of the external interrupt The number of external interrupt circuit units varies among products For the number of external interrupt circuit units in an individual product refer to the device data sheet Table 12 3 1 Pins and Register of External Interrupt Circuit Pin name Pin function Corresponding register INTn External interrupt input ch n External interrupt control register EIC INTn 1 Extern...

Page 199: ...terrupt input pin and as a general purpose I O port If the INT pin is set as an input port by the port direction register DDR and the corresponding external interrupt input is enabled by the external interrupt control register EIC that pin functions as an external interrupt input pin INT The state of a pin can always be read from the port data register PDR when that pin is set as an input port The...

Page 200: ...errupt Circuit When the specified edge of external interrupt input is detected the corresponding external interrupt request flag bit EIC EIR0 or EIR1 is set to 1 In this case if the interrupt request enable bit EIC EIE0 or EIE1 1 corresponding to that external interrupt request flag bit is enabled an interrupt request is generated to the interrupt controller In an interrupt service routine write 0...

Page 201: ...EIC EIR0 or EIR1 is set to 1 and the interrupt request is generated Always set the interrupt request enable bit to 0 when not using an external interrupt to wake up the device from standby mode When setting the edge polarity select bit SL0 1 0 or SL1 1 0 set the interrupt request enable bit EIE0 or EIE1 to 0 to prevent the interrupt request from being generated accidentally Also clear the interrup...

Page 202: ...0 1 0 3 Enable interrupt requests EIC EIE0 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the device data sheet Interrupt processing 1 Clear the interrupt request flag EIC EIR0 0 2 Process any interrupt Note An external interrupt input port shares the same pin with a general purpose I O port Therefore wh...

Page 203: ...12 EXTERNAL INTERRUPT CIRCUIT 12 7 Register 12 7 Register This section describes the register of the external interrupt circuit Table 12 7 1 List of External Interrupt Circuit Register Register abbreviation Register name Reference EIC External interrupt control register 12 7 1 ...

Page 204: ...t request is made If these bits are set to 0b01 rising edges are to be detected if 0b10 falling edges are to be detected if 0b11 both edges are to be detected bit4 EIE1 Interrupt request enable bit 1 This bit enables or disables outputting the interrupt request to the interrupt controller When this bit and the external interrupt request flag bit 1 EIR1 are 1 an interrupt request is output When usi...

Page 205: ...1 rising edges are to be detected if 0b10 falling edges are to be detected if 0b11 both edges are to be detected bit0 EIE0 Interrupt request enable bit 0 This bit enables or disables outputting the interrupt request to the interrupt controller When this bit and the external interrupt request flag bit 0 EIR0 are 1 an interrupt request is output When using an external interrupt pin write 0 to the co...

Page 206: ...ore setting the edge polarity select bits SL0 1 0 or SL1 1 0 set the interrupt request enable bit EIE0 or EIE1 to 0 disabling interrupt requests In addition clear the external interrupt request flag bit EIR0 or EIR1 to 0 after setting the edge polarity The external interrupt circuit cannot wake up from the interrupt service routine if the external interrupt request flag bit is 1 and the interrupt ...

Page 207: ...APTER 13 INTERRUPT PIN SELECTION CIRCUIT This chapter describes the functions and operations of the interrupt pin selection circuit 13 1 Overview 13 2 Configuration 13 3 Pins 13 4 Operation 13 5 Register 13 6 Notes on Using Interrupt Pin Selection Circuit ...

Page 208: ...s peripheral input pins Interrupt Pin Selection Circuit The interrupt pin selection circuit is used to select interrupt input pins from various peripheral inputs EC1 INT00 TRG1 UCK0 and UI0 The input signal from each peripheral function pin is selected by this circuit and the signal is used as the INT00 ch 0 input of external interrupt This enables the input signals to the peripheral function pins...

Page 209: ...in selection circuit control register This register is used to determine which of the available peripheral input pins should be output to the interrupt circuit and which interrupt pins they should serve as Selection circuit This circuit outputs the input from the pin selected by the WICR register to the INT00 input of the external interrupt circuit ch 0 P01 INT01 External interrupt circuit INT01 I...

Page 210: ... These input pins except INT00 are also connected to their respective peripheral units in parallel and can be used for both functions simultaneously Table 13 3 1 shows the correspondence between the peripheral functions and peripheral input pins Table 13 3 1 Correspondence between Peripheral Functions and Peripheral Input Pins Peripheral input pin name Peripheral functions name EC1 8 16 bit compos...

Page 211: ...input pin in the WICR register Write 0x01 to the WICR register At this point write 0 to the EIE0 bit in the EIC00 register of the external interrupt circuit to disable the operation of the external interrupt circuit 3 Enable the operation of INT00 of the external interrupt circuit ch 0 Set the SL0 1 0 bits in the EIC00 register to any value other than 0b00 in the external interrupt circuit to sele...

Page 212: ... PIN SELECTION CIRCUIT 13 5 Register 13 5 Register This section describes the register of the interrupt pin selection circuit Table 13 5 1 List of External Interrupt Circuit Register Register abbreviation Register name Reference WICR Interrupt pin selection circuit control register 13 5 1 ...

Page 213: ... the INT00 pin can generate an external interrupt if INT00 ch 0 operation is enabled in the external interrupt circuit bit5 4 Undefined bits Their read values are always 0 Writing values to these bits has no effect on operation bit3 EC1 EC1 interrupt pin select bit This bit determines whether to select the EC1 pin as an interrupt input pin Writing 0 to this bit deselects the EC1 pin as an interrup...

Page 214: ...n is enabled in the external interrupt circuit bit0 TRG1 TRG1 interrupt pin select bit This bit determines whether to select the TRG1 pin as an interrupt input pin Writing 0 to this bit deselects the TRG1 pin as an interrupt input pin and the interrupt pin selection circuit treats the TRG1 pin input as being fixed at 0 Writing 1 to this bit selects the TRG1 pin as an interrupt input pin and the ci...

Page 215: ...se bits while the INT00 ch 0 of the external interrupt circuit is enabled If modified the external interrupt circuit may detect a valid edge depending on the pin input level If multiple interrupt pins are selected in the WICR register simultaneously and the operation of INT00 ch 0 of the external interrupt circuit is enabled the values other than 0b00 are written to the SL0 1 0 bits in the EIC reg...

Page 216: ...ch 0 of the external interrupt circuit is enabled a value other than 0b00 is written to the SL0 1 0 bits in the EIC register of the external interrupt circuit to select a valid edge and 1 is written to the EIE0 bit to enable the interrupt request the input to the selected pins will remain enabled so as to accept interrupts even in standby mode If multiple interrupt pins are selected in the WICR re...

Page 217: ... UART This chapter describes the functions and operations of the LIN UART 14 1 Overview 14 2 Configuration 14 3 Pins 14 4 Interrupts 14 5 LIN UART Baud Rate 14 6 Operations of LIN UART and LIN UART Setting Procedure Example 14 7 Registers 14 8 Notes on Using LIN UART ...

Page 218: ...cated baud rate generator provided made of a 15 bit reload counter The external clock can be inputted It can be adjusted by the reload counter Data length 7 bits not in synchronous or LIN mode 8 bits Signal type NRZ Non Return to Zero Start bit timing Synchronization with the start bit falling edge in asynchronous mode Reception error detection Framing error Overrun error Parity error Not supporte...

Page 219: ...ve operation for the multiprocessor mode The communication format of operating mode 3 is fixed 8 bit data no parity stop bit 1 LSB first Table 14 1 2 LIN UART Operating Modes Operating mode Data length Synchronous method Stop bit length Data bit format No parity With parity 0 Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits LSB first MSB first 1 Multiprocessor mode 7 bits or 8 bits 1 Asyn...

Page 220: ...a register RDR Transmit control circuit Transmit shift register LIN UART transmit data register TDR Error detection circuit Oversampling circuit Interrupt generation circuit LIN synch break synch field detection circuit Bus idle detection circuit LIN UART serial control register SCR LIN UART serial mode register SMR LIN UART serial status register SSR LIN UART extended status control register ESCR...

Page 221: ...CES LBIE LBD RBI RIE TIE IRQ IRQ LBD SIN PE ORE FRE Machine clock SIN SOT MS SSM SCDE TDRE RDRF RBI TBI UPCL OTO EXT REST PE ORE FRE TBI RBI TBI SIN SCK SOT LBR LBR LBL1 LBL0 LBL1 LBL0 Pin Pin Pin Reload counter Restart receive reload counter Over sampling circuit Internal signal to 8 16 bit composite timer LIN break SynField detection circuit Error detection Internal data bus SSR register SMR reg...

Page 222: ...start circuit and a transmit parity counter The transmit bit counter counts the transmit data bits and sets a flag in the transmit data register when the transmission of one data is completed according to the specified data length If the transmit interrupt has been enabled a transmit interrupt request is made The transmit start circuit starts transmission when data is written to the TDR The transm...

Page 223: ...UART serial control register SCR Its operating functions are as follows Setting the use of the parity bit Parity bit select Setting stop bit length Setting data length Selecting the frame data format in operating mode 1 Clearing the error flag Enabling disabling transmission Enabling disabling reception LIN UART serial mode register SMR Its operating functions are as follows Selecting the LIN UART...

Page 224: ...ngth Direct access to SIN pin and SOT pin Setting continuous clock output in LIN UART synchronous clock mode Sampling clock edge selection LIN UART extended communication control register ECCR Its operating functions are as follows Bus idle detection Synchronous clock setting LIN synch break generation Input Clock The LIN UART uses a machine clock or an input signal from the SCK pin as an input cl...

Page 225: ...3 1 lists the LIN UART pin functions and settings for using them Table 14 3 1 Pins of LIN UART Pin name Pin function Settings required for using pin SIN Serial data input Set to the input port DDR corresponding bit 0 SOT Serial data output Enable output SMR SOE 1 SCK Serial clock input output Set to the input port when this pin is used for clock input DDR corresponding bit 0 Enable output when thi...

Page 226: ...ve interrupts Receive interrupts If one of the following operations occurs in reception mode the bit in the LIN UART serial status register SSR corresponding to that operation is set to 1 Data reception completed Received data is transferred from the LIN UART serial input shift register to the LIN UART receive data register RDR RDRF 1 Overrun error With RDRF 1 the next serial data is received whil...

Page 227: ...ted within the LIN synch field To detect a LIN synch break the reception must be disabled SCR RXE 0 Transmit Interrupts Table 14 4 2 shows the control bit and interrupt source of the transmit interrupt Transmit interrupts The transmit data register empty flag bit TDRE in the LIN UART serial status register SSR is set to 1 when the transmit data is transferred from the LIN UART transmit data regist...

Page 228: ...it composite interrupt has been enabled The difference in the count values detected by the 8 16 bit composite timer see Figure 14 4 1 is equivalent to eight bits of the master serial clock A new baud rate can be calculated from this value After set a new baud rate becomes effective from the falling edge detected at the next start bit set Figure 14 4 1 Baud Rate Calculation by 8 16 bit Composite Ti...

Page 229: ... all operating modes when a receive error occurs data in the LIN UART receive data register RDR becomes invalid Figure 14 4 2 shows the timing of reception and flag set Figure 14 4 2 Timing of Reception and Flag Set Note Figure 14 4 2 does not show all reception operations in mode 0 It only shows two examples of reception operations using different communication formats One reception operation use...

Page 230: ...B95630H Series 210 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 14 LIN UART 14 4 Interrupts Figure 14 4 3 ORE Flag Set Timing RDRF ORE ST 0 1 2 3 4 5 6 7 ST SP 0 1 2 3 4 5 6 7 SP Received data ...

Page 231: ...E bit is a read only bit and is cleared to 0 only when data is written to the LIN UART transmit data register TDR Figure 14 4 4 shows the timing of transmission and flag set Figure 14 4 4 Timing of Transmission and Flag Set Note Figure 14 4 4 does not show all transmission operations in operating mode 0 It only shows an example of a transmission operation using 8 bit data a parity bit even parity ...

Page 232: ... Since the initial value of the TDRE bit is 1 a transmit interrupt is generated immediately after the transmit interrupt is enabled SSR TIE 1 When deciding the timing of enabling the transmit interrupt take into consideration that the TDRE bit can be cleared only by writing new data to the LIN UART transmit data register TDR For interrupt request numbers and vector table addresses of respective pe...

Page 233: ...r divides the internal clock by the value set in BGR1 and BGR0 The baud rate is used in asynchronous mode and in synchronous mode transmit side of the serial clock As for clock source settings select the internal clock and use the baud generator clock SMR EXT 0 OTO 0 Baud rate derived from the external clock divided by the dedicated baud rate generator reload counter The external clock is used as ...

Page 234: ...3 BGR2 BGR1 BGR0 Txc 0 Txc v 2 OTO 1 0 1 0 BGR13 BGR12 BGR11 BGR14 F F Rxc 0 Rxc v 2 F F EXT OTO 1 0 Reload value v Receive 15 bit reload counter Transmit 15 bit reload counter Reload value v Counter value TXC Reload REST Start bit falling edge detection Receive clock Transmit clock SCK External clock input Reset Reset Set Set Internal data bus SMR register BGR1 register BGR0 register MCLK Machine...

Page 235: ... value b Baud rate MCLK Machine clock or external clock frequency Calculation example Assuming that the machine clock is 10 MHz the internal clock is used and the baud rate is set to 19200 bps Reload value Thus the actual baud rate can be calculated as shown below Note The reload counter stops if the reload value is set to 0 Therefore set the smallest reload value to 1 For transmission reception i...

Page 236: ...5 0 500000 15 0 19 0 31 0 400800 250000 31 0 39 0 63 0 64 0 230400 68 0 64 153600 51 0 16 64 0 16 103 0 16 105 0 19 125000 63 0 79 0 127 0 129 0 115200 68 0 64 86 0 22 138 0 08 140 0 04 76800 103 0 16 129 0 16 207 0 16 211 0 19 57600 138 0 08 173 0 22 277 0 08 281 0 04 38400 207 0 16 259 0 16 416 0 08 422 0 04 28800 277 0 08 346 0 06 555 0 08 563 0 04 19200 416 0 08 520 0 03 832 0 04 845 0 04 1041...

Page 237: ...n is used in operating mode 2 synchronous select the one to one external clock input mode SMR OTO 1 In this mode the external clock input to SCK is input directly to the LIN UART serial clock Note The external clock signal is synchronized with the internal clock MCLK machine clock in the LIN UART Therefore if the external clock becomes not divisible because its cycle is faster than half the cycle ...

Page 238: ...he operation of two reload counters using a reload value 832 as an example Figure 14 5 2 Operation of Dedicated Baud Rate Generator Reload Counter Note The falling edge of the serial clock signal is generated after the reload value divided by 2 V 1 2 is counted Transmit receive clock Reload counter Reload counter value 002 001 832 831 830 829 828 417 416 415 414 413 412 411 Falling at V 1 2 ...

Page 239: ...ive clock from the external clock or internal clock The count value in the transmit reload counter can be read from the LIN UART baud rate generator registers 1 0 BGR1 and BGR0 Start of counting Writing a reload value to the LIN UART baud rate generator registers 1 0 BGR1 BGR0 causes the reload counter to start counting Restart The reload counter restarts under the following conditions For both tr...

Page 240: ...ynchronous mode This automatic restart function is to synchronize the receive shift register with the received data Clear counter When a reset occurs the reload values in the LIN UART baud rate generator registers 1 0 BGR1 BGR0 and the reload counter are cleared to 0x00 and the reload counter stops Although the counter value is temporarily cleared to 0x00 by the LIN UART reset writing 1 to SMR UPC...

Page 241: ...lave supports both master operations and slave operations In operating mode 3 the communication format is fixed at 8 bit data no parity bit one stop bit LSB first If the operating mode is changed all transmission operations and reception operations are canceled and the LIN UART waits for the next transmission reception Table 14 6 1 LIN UART Operating Modes Operating mode Data length Synchronous me...

Page 242: ...e start bit falling edge As for the synchronous method the receive clock can be synchronized with the clock signal of the serial clock transmission side or with the clock signal of the LIN UART operating as the transmission side Signaling NRZ Non Return to Zero Enable Transmission Reception The LIN UART uses the SCR TXE bit and the SCR RXE bit to control transmission and reception respectively Exe...

Page 243: ...er direction LSB first or MSB first is determined by the BDS bit in the LIN UART serial status register SSR When the parity bit is used it is always placed between the last data bit and the first stop bit In operating mode 0 the data length can be 7 bits or 8 bits The use of the parity can be selected The stop bit length can also be selected from one and two In operating mode 1 the data length can...

Page 244: ...D1 D0 P ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 P SP SP SP Operating mode 0 Operating mode 1 ST Start bit SP Stop mode P Parity bit AD P None 8 bit data 7 bit data P Present P None P Present 8 bit ...

Page 245: ...rmed when reception is enabled SCR RXE 1 When a start bit is detected one frame data is received according to the data format defined in the LIN UART serial control register SCR If an error occurs an error flag SSR PE ORE FRE is set After the reception of one frame data ends the received data is transferred from the receive shift register to the LIN UART receive data register RDR and the receive d...

Page 246: ...he overrun error and the frame error can be detected However the parity error cannot be detected Parity The addition at transmission of and the detection during reception of a parity bit can be set The parity enable bit SCR PEN is used to select whether or not to use a parity the parity select bit SCR P is used to select the odd even parity In operating mode 1 the parity cannot be used Figure 14 6...

Page 247: ...UART extended status control register ESCR is 1 the serial clock is inverted In the case of serial clock reception side is selected the LIN UART samples data at the falling edge of the received serial clock In the case of serial clock transmission side is selected the mark level is set to 0 when the SCES bit is 1 Figure 14 6 4 Transmission Data Format During Clock Inverted Start stop bits When the...

Page 248: ... equal to the number of transmit receive data bits must be supplied from an external clock pin The clock signal must be kept at the mark level H if serial data is not related to transmission reception Clock delay When the SCDE bit in the ECCR is set to 1 a delayed transmit clock is output as shown in Figure 14 6 5 This function is required when the device on the reception side samples data at the ...

Page 249: ...UART baud rate generator registers 1 0 BGR1 BGR0 Set the dedicated baud rate reload counter to a required value LIN UART serial mode register SMR MD 1 0 0b10 Operating mode 2 SCKE 1 Uses the dedicated baud rate reload counter 0 Inputs an external clock SOE 1 Enables transmission reception 0 Enables only reception LIN UART serial control register SCR RXE TXE Set either bit to 1 AD Since the address...

Page 250: ...cation control register ECCR SSM 0 Not use start stop bits normal 1 Uses start stop bits extended function MS 0 Serial clock transmission side serial clock output 1 Serial clock reception side inputs serial clock from the device on the serial clock transmission side Note To start communication write data to the LIN UART transmit data register TDR To receive data only disable the serial output SMR ...

Page 251: ...ted as byte data 0x55 following a LIN synch break To prevent the generation of a transmit interrupt 0x55 can be written to the TDR after the LBR bit in ECCR is set to 1 even if the TDRE bit is 0 Operation as LIN slave In LIN slave mode the LIN UART must synchronize with the baud rate of the master The LIN UART generates a receive interrupt when LIN break interrupt is enabled LBIE 1 even though rec...

Page 252: ... of the 8 16 bit composite timer see 11 12 Operation of Input Capture Function LIN synch break detection interrupt and flag The LIN break detection LBD flag in ESCR is set to 1 when the LIN synch break is detected in slave mode When the LIN break interrupt is enabled LBIE 1 an interrupt is generated Figure 14 6 7 Timing of LIN Synch Break Detection and Flag Set The above diagram shows the timing o...

Page 253: ... RXE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bus RXE LBD IRQ RDRF SIN IRQ IRQ TII0 LIN LBIE RIE 8 16 bit composite timer count No clock Calculation frame Previous serial clock Newly calculated serial clock Enable receive interrupts LIN break starts LIN break detected interrupt generated IRQ clear by CPU LBD 0 IRQ clear input capture of 8 16 bit composite timer count starts IRQ clear Baud rate calc...

Page 254: ... the serial output pin SOT ESCR SOPE 1 write 0 or 1 to the serial I O pin direct access bit ESCR SIOP and then enable serial output SMR SOE 1 In LIN mode this feature is used for reading transmitted data and for error handling when there is a physical LIN bus line signal error Note Direct access is allowed only when transmission is not in progress the transmit shift register is empty Before enabli...

Page 255: ...ing bidirectional communication connect two CPUs as shown in Figure 14 6 11 Figure 14 6 11 Example of Connection for Bidirectional Communication in LIN UART Operating Mode 2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR SMR PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 0 0 0 0 0 0 0 Mode 2 0 1 0 0 0 SSR RDR TDR PE ORE FRE RDRF TDRE ...

Page 256: ...per one byte in this example regularly after receiving transmit data Figure 14 6 12 is an example of bidirectional communication flow chart Figure 14 6 12 Example of Bidirectional Communication Flow Chart NO NO YES YES Start Start Set operating mode 0 or 2 Communicate with 1 byte data set in TDR Data received Read and process received data Set operating mode same as that of the master Read and pro...

Page 257: ...nes connecting between one master CPU and multiple slave CPUs as shown in Figure 14 6 14 The LIN UART can be used as a master or a slave Figure 14 6 14 Connection Example of LIN UART Master Slave Mode Communication Function selection In master slave mode communication select the operating mode and the data transfer method as shown in Figure 14 6 14 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit...

Page 258: ...am to check address data and communicates with the master CPU when the address data matches the address assigned to that slave CPU Figure 14 6 15 is a flow chart showing master slave mode communication multiprocessor mode Table 14 6 4 Selection of Master Slave Mode Communication Functions Operating mode Data Parity Synchronous method Stop bit Bit direction Master CPU Slave CPU Address transmission...

Page 259: ...al data input Set SOT pin for serial data output Set SIN pin for serial data input Set SOT pin for serial data output Set 7 or 8 data bits Set 1 or 2 stop bits Set 7 or 8 data bits Set 1 or 2 stop bits Set AD bit to 1 Enable transmission reception Enable transmission reception Transmit address to slave Receive bytes AD bit 1 Set AD bit to 0 Communicate with slave CPU Terminate communication Commun...

Page 260: ...4 6 17 shows an example of communication in a LIN bus system The LIN UART can operate as a LIN master or a LIN slave Figure 14 6 17 Example of LIN Bus System Communication bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR SMR PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 3 0 1 1 0 0 0 SSR RDR TDR PE ORE FRE RDRF TDRE BDS RIE TIE Set con...

Page 261: ...Receive ID field 1 Enable reception LBD 0 Disable synch break interrupts No error Handle an error 2 Data field received Set transmit data 1 TDR Data 1 Enable transmit interrupts Wake up 0x80 reception Receive synch field 1 Set Identify field TDR ID RDRF 1 Receive interrupt RDRF 1 Receive interrupt Reception Transmission RDRF 1 Receive interrupt Receive data 1 1 Receive data N 1 RDRF 1 Receive inte...

Page 262: ...eceived Set transmit data 1 TDR Data 1 Enable transmit interrupts Read 8 16 bit composite timer data Clear 8 16 bit composite timer interrupt flag TII0 interrupt TII0 interrupt Reception Transmission RDRF 1 Receive interrupt Receive data 1 1 Receive data N 1 RDRF 1 Receive interrupt Set transmit data N TDR Data N Disable transmit interrupts Receive data 1 1 Read data 1 Receive data N 1 Read data N...

Page 263: ...ame Reference SCR LIN UART serial control register 14 7 1 SMR LIN UART serial mode register 14 7 2 SSR LIN UART serial status register 14 7 3 RDR LIN UART receive data register 14 7 4 TDR LIN UART transmit data register 14 7 4 ESCR LIN UART extended status control register 14 7 5 ECCR LIN UART extended communication control register 14 7 6 BGR1 LIN UART baud rate generator register 1 14 7 7 BGR0 L...

Page 264: ... is fixed at 0 in operating mode 3 LIN bit6 P Parity select bit With the parity bit having been enabled SCR PEN 1 setting this bit to 1 selects the odd parity and setting this bit to 0 selects the even parity bit5 SBL Stop bit length select bit This bit sets the bit length of the stop bit frame end mark in transmit data in operating mode 0 1 asynchronous or in operating mode 2 synchronous in which...

Page 265: ...ation of the LIN UART The LIN synch break detection in operating mode 3 is not affected by the setting of this bit Note When data frame reception is disabled RXE 0 while it is in progress the reception halts immediately In this case the integrity of data is not guaranteed bit0 TXE Transmit operation enable bit This bits enables or disables the transmit operation of the LIN UART Note When data fram...

Page 266: ...ial clock is selected ECCR MS 1 When the EXT bit in the SMR register is 0 the OTO bit is fixed at 0 bit4 EXT External serial clock source select bit This bit selects the clock input bit3 REST Reload counter restart bit This bit restarts the reload counter bit 7 6 5 4 3 2 1 0 Field MD1 MD0 OTO EXT REST UPCL SCKE SOE Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit7 6 Oper...

Page 267: ...nous When set as a serial clock output pin SCKE 1 the SCK pin functions as a LIN UART serial clock output pin regardless of the state of the general purpose I O port sharing the same pin with SCK Note To use the SCK pin as a LIN UART serial clock input pin SCKE 0 enable the use of the input port by setting the bit in the DDR register corresponding to the general purpose I O port sharing the same p...

Page 268: ...e LIN UART serial control register SCR When both the ORE bit and the RIE bit are 1 a receive interrupt request is output When this flag is set the data in the receive data register RDR is invalid bit5 FRE Framing error flag bit This flag bit detects the framing error in received data This bit is set to 1 when a framing error occurs during reception and cleared by writing 1 to the CRE bit in the LI...

Page 269: ...irst BDS 1 Note When data is written to or read from the serial data register the data on the upper side and that on the lower side are swapped Therefore if the BDS bit is modified after data is written to the RDR register the data in the RDR register becomes invalid In operating mode 3 LIN the BDS bit is fixed at 0 bit1 RIE Receive interrupt request enable bit This bit enables or disables the rec...

Page 270: ...rrupt has been enabled and no errors occur When a reception error occurs any of SSR PE ORE or FRE is 1 the data in the LIN UART receive data register RDR becomes invalid LIN UART Transmit Data Register TDR The LIN UART transmit data register TDR is the data buffer register for serial data transmission If the data to be transmitted is written to the LIN UART transmit data register TDR when transmis...

Page 271: ...RT transmit data register is a write only register the receive data register is a read only register Since both registers are located at the same address the write value and the read value are different Thus the read modify write RMW type of instruction such as the INC instruction and the DEC instruction cannot be used ...

Page 272: ...break detection flag bit This bit detects the LIN synch break This bit is set to 1 when a LIN synch break is detected in operating mode 3 the serial input is 0 when bit width is 11 bits or more If 0 is written to the LBD bit the LBD bit and the interrupt are cleared Although the bit always returns 1 if read by the read modify write RMW type of instruction this does not indicate that a LIN synch br...

Page 273: ...he value written to this bit is reflected in the SOT pin Note When the bit manipulation instruction is used the SIOP bit returns the bit value of the SOT pin in the read cycle bit5 4 Details Writing 00 13 bits Writing 01 14 bits Writing 10 15 bits Writing 11 16 bits bit3 Details Writing 0 Disables serial output pin direct access Writing 1 Enables serial output pin direct access bit2 Details Read a...

Page 274: ...hich the serial clock reception side is selected setting the SCES bit to 1 switches the sampling edge from the rising edge to the falling edge In operating mode 2 synchronous in which the serial clock transmission side is selected ECCR MS 0 when the SCK pin is used as an clock output pin the internal serial clock signal and the output clock signal are inverted In operating mode 0 1 3 set this bit ...

Page 275: ...ion side of the serial clock in operating mode 2 If the transmission side MS 0 is selected the LIN UART generates a synchronous clock If the reception side MS 1 is selected the LIN UART receives an external serial clock In mode 0 1 3 this bit is fixed at 0 Modify this bit only when the SCR TXE bit is 0 Note When the reception side is selected the external clock must be selected as the clock source...

Page 276: ... 0 bit2 Reserved bit Always set this bit to 0 bit1 RBI Receive bus idle detection flag bit If the SIN pin is at H level and no reception is executed this bit is 1 Do not use this bit when SSM 0 in operating mode 2 bit0 TBI Transmit bus idle detection flag bit If there is no transmission on the SOT pin this bit is 1 Do not use this bit when SSM 0 in operating mode 2 bit4 Details only for operating ...

Page 277: ...n be written to and the transmit reload counter value can be read from BGR1 and BRG0 In addition BGR1 and BGR0 can be accessed by byte access and word access Writing a reload value to the LIN UART baud rate generator registers causes the reload counter to start counting Write values to the BGR1 register or the BGR0 register only when the LIN UART has stopped operating BGR1 bit 7 6 5 4 3 2 1 0 Fiel...

Page 278: ...is made immediately after the transmit interrupt request is enabled SSR TIE 1 To prevent any transmit interrupt request from being made always set the TIE flag bit to 1 after setting transmit data Modifying operation settings With the sampling clock edge select bit ESCR SCES set to 0 before modifying any of the bits listed below disable reception and transmission After modifying them reset the LIN...

Page 279: ...k is received to ensure that a LIN synch break whose length is a minimum of 13 bits is successfully detected Bus idle function The bus idle function is not available in synchronous mode operating mode 2 AD bit LIN UART serial control register SCR Address data format select bit Pay attention to the following issues when using the AD bit The AD bit is used to select the address data for transmission...

Page 280: ...Handling framing errors If a framing error occurs stop bit SIN 0 and the next start bit SIN 0 immediately follows it this start bit is recognized regardless of a falling edge for the start bit and reception is started This sequence is used for detecting the continuous L state of the serial data input SIN when the next framing error is detected while the data stream is synchronized See When recepti...

Page 281: ...ception is temporarily disabled RXE 1 0 1 Framing error occurs Error is cleared Reception is ongoing regardress of no falling edge Falling edge is next start bit edge Next framing error occurs Framing error occurs Error is cleared Falling edge is next start bit edge Reception is ongoing regardress of no falling edge No further errors SIN FRE CRE RXE SIN FRE CRE Reception is reset Waitng for fallin...

Page 282: ...MB95630H Series 262 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 14 LIN UART 14 8 Notes on Using LIN UART ...

Page 283: ...8 10 BIT A D CONVERTER This chapter describes the functions and operations of the 8 10 bit A D converter 15 1 Overview 15 2 Configuration 15 3 Pin 15 4 Interrupt 15 5 Operations and Setting Procedure Example 15 6 Registers 15 7 Notes on Using 8 10 bit A D Converter ...

Page 284: ...ltage input voltage input through an analog input pin to an 8 bit or 10 bit digital value The input signal can be selected from multiple analog input pins The conversion speed can be set in a program can be selected according to operating voltage and frequency An interrupt is generated when A D conversion is completed The completion of conversion can be determined according to the ADI bit in the A...

Page 285: ...Figure 15 2 1 is the block diagram of the 8 10 bit A D converter Figure 15 2 1 Block Diagram of 8 10 bit A D Converter Clock selector This selects the A D conversion clock with continuous activation having been enabled ADC2 EXT 1 Analog channel selector This is the circuit selecting an input channel from several analog input pins AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0 ANS3 ANS2 ANS1 ANS0 ADI AD...

Page 286: ...rsion function sets the interrupt request flag bit ADC1 ADI to 1 A D converter data registers ADDH ADDL The upper two bits of 10 bit A D data are stored in the ADDH register the lower eight bits in the ADDL register If the A D conversion precision bit ADC2 AD8 is set to 1 the A D conversion precision becomes 8 bit precision and the upper eight bits of 10 bit A D data are to be stored in the ADDL r...

Page 287: ...eral purpose I O port AN pin When using the A D conversion function input to the AN pin the analog voltage to be converted To use an AN pin as an analog input pin write 0 to the bit in the port direction register DDR corresponding to that pin and the value corresponding to that pin to the analog input pin select bits ADC1 ANS A pin not used as an analog input pin can be used as a general purpose I...

Page 288: ...est flag bit ADC1 ADI is set to 1 Then if the interrupt request enable bit has been enabled ADC2 ADIE 1 an interrupt request is made to the interrupt controller Write 0 to the ADI bit using the interrupt service routine to clear the interrupt request The ADI bit is set to 1 when A D conversion is completed irrespective of the value of the ADIE bit The CPU cannot return from interrupt processing if...

Page 289: ... Function Software activation The settings shown in Figure 15 5 1 are required for activating the A D conversion function with the software Figure 15 5 1 Settings for A D Conversion Function Software Activation When the A D conversion function is activated A D conversion starts In addition the A D conversion function can be re activated even during conversion bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit...

Page 290: ...tor in the control circuit compares the voltage loaded into sample and hold capacitor with the A D conversion reference voltage from the most significant bit MSB to the least significant bit LSB and then transfers the results to the ADDH and ADDL registers After the results have been transferred to the two registers the conversion flag bit is cleared ADC1 ADMV 0 and the interrupt request flag bit ...

Page 291: ...mpling time ADC2 TIM 1 0 5 Select the clock ADC2 CKDIV 1 0 6 Set A D conversion precision ADC2 AD8 7 Select the operating mode ADC2 EXT 8 Select the start trigger ADC2 ADCK 9 Enable interrupts ADC2 ADIE 1 10 Activate the A D conversion function ADC1 AD 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the d...

Page 292: ...e registers of the 8 10 bit A D converter Table 15 6 1 List of 8 10 bit A D Converter Registers Register abbreviation Register name Reference ADC1 8 10 bit A D converter control register 1 15 6 1 ADC2 8 10 bit A D converter control register 2 15 6 2 ADDH 8 10 bit A D converter data register upper 15 6 3 ADDL 8 10 bit A D converter data register lower 15 6 3 ...

Page 293: ... be modified simultaneously The number of analog input pins vary among products For the number of analog input pins of a product refer to its data sheet Notes Do not write to ANS 3 0 any value other than those listed in the table above When the ADMV bit is 1 do not modify these bits Pins not used as analog input pins can be used as general purpose I O ports bit 7 6 5 4 3 2 1 0 Field ANS3 ANS2 ANS1...

Page 294: ...ffect on operation bit1 Reserved bit Always set this bit to 0 bit0 AD A D conversion start bit This bit starts the A D conversion function with the software Writing 1 to the bit starts the A D conversion function When the continuous start enable bit in the ADC2 register ADC2 EXT is 1 starting the A D conversion with this bit is disabled With the EXT bit set to 0 when 1 is written to this bit while...

Page 295: ...nly when the A D converter has stopped operating bit6 5 TIM 1 0 Sampling time select bits These bits select the sampling time Modify the sampling time according to operating conditions voltage and frequency The CKIN value is determined by the clock select bits ADC2 CKDIV 1 0 Note Modify these bits only when the A D converter has stopped operating bit4 ADCK External start signal select bit This bit...

Page 296: ... bits These bits select the clock CKIN to be used for A D conversion The input clock is generated by the prescaler See 3 9 Operation of Prescaler for details The sampling time varies according to the clock selected by these bits Modify these bits according to operating conditions voltage and frequency Note Modify these bits only when the A D converter has stopped operating bit3 Details Writing 0 D...

Page 297: ...btain 8 bit data These two registers are read only registers Writing data to them has no effect on operation In A D conversion in which 8 bit precision is selected SAR8 and SAR9 in the ADDH register become 0 A D conversion function When A D conversion is started the results of conversion are finalized and stored in the ADDH and ADDL registers after the conversion time according to the register set...

Page 298: ...nterrupt service routine Note on interrupt requests If the restart of A D conversion ADC1 AD 1 and the completion of A D conversion occur simultaneously the interrupt request flag bit ADC1 ADI is set A D conversion error As Vcc Vss decreases the A D conversion error increases proportionately 8 10 bit A D converter analog input sequences Turn on the analog input AN and the digital power supply VCC ...

Page 299: ...279 CHAPTER 15 8 10 BIT A D CONVERTER 15 7 Notes on Using 8 10 bit A D Converter When setting the A D converter in software ensure that the settings satisfy the specifications of sampling time and compare time of the A D converter mentioned in the device data sheet ...

Page 300: ...MB95630H Series 280 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 15 8 10 BIT A D CONVERTER 15 7 Notes on Using 8 10 bit A D Converter ...

Page 301: ...ONDUCTOR LIMITED 281 CHAPTER 16 LOW VOLTAGE DETECTION RESET CIRCUIT This chapter describes the function and operation of the low voltage detection reset circuit 16 1 Overview 16 2 Configuration 16 3 Pins 16 4 Operation 16 5 Register ...

Page 302: ...et Circuit The low voltage detection reset circuit monitors power supply voltage and generates a reset signal if the power supply voltage drops below the low voltage detection voltage level The LVD reset voltage selection ID register LVDR selects the reset threshold voltage At power on the lowest reset threshold voltage is selected in the LVDR register The circuit is only available on certain prod...

Page 303: ...tion Figure 16 2 1 is the block diagram of the low voltage detection reset circuit Block Diagram of Low voltage Detection Reset Circuit Figure 16 2 1 Block Diagram of Low voltage Detection Reset Circuit Reset signal Vref VCC N ch LVD reset voltage selection ID register LVDR LVRS7 LVRS6 LVRS4 LVRS3 LVRS2 LVRS1 LVRS0 LVRS5 0xAA 0x5A 0x55 Other values ...

Page 304: ...bes the pins of the low voltage detection reset circuit Pins of Low voltage Detection Reset Circuit VCC pin The low voltage detection reset circuit monitors the voltage of this pin VSS pin This is the GND pin serving as the reference for voltage detection RST pin The low voltage detection reset signal is output inside the microcontroller and to this pin ...

Page 305: ...Circuit The low voltage detection reset circuit generates a reset signal if the power supply voltage falls below the low voltage detection voltage Afterward if the low voltage detection reset circuit detects the low voltage detection reset release voltage it outputs a reset signal lasting for the oscillation stabilization wait time and then releases the reset For details of the electrical characte...

Page 306: ... DETECTION RESET CIRCUIT 16 5 Register 16 5 Register This section describes the register of low voltage detection reset circuit Table 16 5 1 List of Low voltage Detection Reset Circuit Register Register abbreviation Register name Reference LVDR LVD reset voltage selection ID register 16 5 1 ...

Page 307: ...d voltage with an 8 bit code They are cleared upon a power on reset Note The reset of the low voltage detection reset circuit has no effect on the reset threshold voltage settings as the reset cannot clear this register bit 7 6 5 4 3 2 1 0 Field LVRS7 LVRS6 LVRS5 LVRS4 LVRS3 LVRS2 LVRS1 LVRS0 Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit7 0 Reset threshold voltage Det...

Page 308: ...MB95630H Series 288 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 16 LOW VOLTAGE DETECTION RESET CIRCUIT 16 5 Register ...

Page 309: ... LIMITED 289 CHAPTER 17 CLOCK SUPERVISOR COUNTER This chapter describes the functions and operations of the clock supervisor counter 17 1 Overview 17 2 Configuration 17 3 Operations 17 4 Registers 17 5 Notes on Using Clock Supervisor Counter ...

Page 310: ...upervisor counter automatically counts up the counter based on the external clock input within the time base timer interval time selected from eight options The main oscillation clock or the sub oscillation clock can be selected as the count clock of this module Note The clock supervisor counter must operate in main CR clock mode with the hardware watchdog timer running in standby mode Otherwise i...

Page 311: ...ctor Counter source clock selector Block Diagram of Clock Supervisor Counter Figure 17 2 1 is the block diagram of the clock supervisor counter Figure 17 2 1 Block Diagram of Clock Supervisor Counter Time base timer output Main oscillation clock Sub oscillation clock Edge detection 8 bit Counter 1st 2nd counting starts counting stops Control Circuit Clock Monitoring Control Register CMCR Clock Mon...

Page 312: ...riod from eight different time base timer intervals start the counter and check whether the counter is operating or not Clock Monitoring Data Register CMDR This register block is used to read the counter value after the counter stops The software determines whether the external clock frequency is correct or not according to the contents of this register Time base timer interval selector This block...

Page 313: ...s Between two rising edges of the time base timer interval selected the internal counter is clocked by the external clock The count clock of this module can be selected from the main oscillation clock and the sub oscillation clock Figure 17 3 1 Clock Supervisor Counter Operation 1 Clock Supervisor Counter Operation 2 The CMDR register is cleared when the CMCEN bit changes from 0 to 1 Figure 17 3 2...

Page 314: ...tifies that the external clock selected is in the abnormal state Figure 17 3 4 Clock Supervisor Counter Operation 4 Clock Supervisor Counter Operation 5 The counter is cleared to 0 by the software if the CMCEN is set to 0 while the counter is operating Figure 17 3 5 Clock Supervisor Counter Operation 5 Selected time base timer interval Main Sub oscillation clock CMCEN Internal counter CMDR registe...

Page 315: ...RH 27 1 FCRH 29 1 FCRH 211 1 FCRH 213 1 FCRH 215 1 FCRH 217 1 FCRH 4 0 03277 2 1 0 0 0 1 7 31 130 525 2 1 1 1 1 3 9 35 137 548 0 5 2 1 0 0 6 30 124 500 2006 8030 2 1 1 3 9 33 131 523 2090 8360 1 2 1 0 2 14 61 249 1002 4014 16061 2 1 2 5 17 66 262 1045 4180 16719 4 2 1 2 14 61 249 1002 4014 16061 64249 2 1 5 17 66 262 1045 4180 16719 66874 6 2 1 4 22 93 375 1504 6022 24093 96375 2 1 7 25 98 392 156...

Page 316: ...base Timer Interval TBC 3 0 0b0110 213 1 FCRH Notes See 7 1 Overview for time base timer interval settings See 3 3 3 Oscillation Stabilization Wait Time Setting Register WATR for main sub oscillation stabilization time settings Counter value 2 3 1 FCRH TBTSEL 000 2 5 1 FCRH TBTSEL 001 2 7 1 FCRH TBTSEL 010 2 9 1 FCRH TBTSEL 011 2 11 1 FCRH TBTSEL 100 2 13 1 FCRH TBTSEL 101 2 15 1 FCRH TBTSEL 110 2...

Page 317: ...ternal clock is oscillating at an abnormal frequency In main CR clock mode wait for the elapse of the specified main clock subclock oscillation stabilization wait time by using the time base timer interrupt or other methods YES NO YES NO 0 1 0 1 Keep main CR clock mode If the oscillation stabilization wait time has elapsed but the main clock subclock oscillation stabili zation bit is not set to 1 ...

Page 318: ...COUNTER 17 4 Registers 17 4 Registers This section describes the registers of the clock supervisor counter Table 17 4 1 List of Clock Supervisor Counter Registers Register abbreviation Register name Reference CMDR Clock monitoring data register 17 4 1 CMCR Clock monitoring control register 17 4 2 ...

Page 319: ... check whether the external clock frequency is correct or not according to the counter value read and the time base timer interval selected bit7 0 CMDR 7 0 Clock monitoring data bits These bits indicate the clock supervisor counter value after the counter stops These bits are cleared if one of the following events occurs Reset The CMCEN bit in the CMCR register CMCR CMCEN is modified from 0 to 1 b...

Page 320: ...ect bits These bits select the time base timer interval The operation of the clock supervisor counter is enabled and disabled at specific times according to the time base timer counter output selected by these bits The first rising edge of the interval selected enables the counter operation and the second rising edge of the same output disables the counter operation bit 7 6 5 4 3 2 1 0 Field Reser...

Page 321: ...000000 Writing 1 to this bit enables the counter The counter starts counting when detecting the rising edge of the time base timer interval It stops counting when detecting the second rising edge of the same interval This bit is automatically set to 0 when the counter stops Notes Do not modify the CMCSEL bit when the CMCEN bit is 1 Do not modify the TBTSEL 2 0 bits when the CMCEN bit is 1 bit0 Det...

Page 322: ... the time base timer while the clock supervisor counter is counting with the external clock Select a time base timer interval that is sufficiently long for the clock supervisor counter to operate See Table 17 3 1 for time base timer intervals Read the CMDR register when CMCEN 0 The value of CMDR remains 0b00000000 while the clock supervisor counter is operating CMCEN 1 When using the clock supervi...

Page 323: ...e 17 5 1 Clock Supervisor Counter Operation 1 With the clock supervisor counter running if the external clock stops CMCEN is set to 0 when a falling edge of the time base timer interval selected is detected after the second rising edge of the same interval The counter is cleared at the same falling edge Figure 17 5 2 Clock Supervisor Counter Operation 2 Selected time base timer interval Main Sub o...

Page 324: ...MB95630H Series 304 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 17 CLOCK SUPERVISOR COUNTER 17 5 Notes on Using Clock Supervisor Counter ...

Page 325: ...PTER 18 8 16 BIT PPG This chapter describes the functions and operations of the 8 16 bit PPG 18 1 Overview 18 2 Configuration 18 3 Channel 18 4 Pins 18 5 Interrupt 18 6 Operations and Setting Procedure Example 18 7 Registers 18 8 Notes on Using 8 16 bit PPG ...

Page 326: ... a product refer to the device data sheet The 8 16 bit PPG functions are summarized as follows 8 bit PPG output independent operation mode In this mode the unit can operate as two 8 bit PPG PPG timer n0 and PPG timer n1 8 bit prescaler 8 bit PPG output operation mode The rising and falling edge detection pulses from the PPG timer n1 output can be input to the downcounter of the PPG timer n0 to ena...

Page 327: ... CLK START STOP BORROW LOAD PEN00 Edge detection PEN01 Edge detection MD1 MD0 1 0 01 S Q R REV00 PPG timer n0 PPG timer n1 S Q R REV01 1 0 PPGn1 Pin 1 0 1 0 1 0 PIE1 PPGn0 Pin PUF1 POEN1 IRQXX POEN1 PIE0 PUF0 POEN0 IRQXX POEN0 Edge detection 0 1 1 0 00 10 11 1 0 Used as the select signal of each selector Duty setup register Cycle setup buffer register Duty register buffer cycle setup Compa rator c...

Page 328: ...m the value of 8 16 bit PPG cycle setup buffer register 8 16 bit PPG timer n1 control register PCn1 The operation condition on the PPG timer n1 side of 8 16 bit PPG timer is set 8 16 bit PPG timer n0 control register PCn0 The operation mode of 8 16 bit PPG timer and the operation condition on the PPG timer n0 side are set 8 16 bit PPG timer n1 n0 cycle setup buffer register PPSn1 PPSn0 The compare...

Page 329: ... of 8 16 bit PPG Pin name Pin function PPGn0 PPG timer n0 8 bit PPG n0 16 bit PPG PPGn1 PPG timer n1 8 bit PPG n1 8 bit prescaler Table 18 3 2 Registers of 8 16 bit PPG Register abbreviation Corresponding register Name in this manual PCn1 8 16 bit PPG timer n1 control register PCn0 8 16 bit PPG timer n0 control register PPSn1 8 16 bit PPG timer n1 cycle setup buffer register PPSn0 8 16 bit PPG tim...

Page 330: ...s the pins of the 8 16 bit PPG Pins of 8 16 bit PPG PPGn0 pin and PPGn1 pin These pins function both as general purpose I O ports and 8 16 bit PPG outputs PPGn0 PPGn1 A PPG waveform is output to these pins The PPG waveform can be output by enabling the output by the 8 16 bit PPG timer n1 n0 control registers PCn0 POEN0 1 PCn1 POEN1 1 ...

Page 331: ...ion flag bit PUF in the 8 16 bit PPG timer n0 n1 control register PC to 1 When the interrupt request enable bit is enabled PIE 1 an interrupt request is output to the interrupt controller In 16 bit PPG mode the 8 16 bit PPG timer n0 control register PCn0 is available Table 18 5 1 Interrupt Control Bits and Interrupt Sources of 8 16 bit PPG Item Description PPG timer n1 8 bit PPG 8 bit prescaler PP...

Page 332: ...IT PPG 18 6 Operations and Setting Procedure Example 18 6 Operations and Setting Procedure Example This section describes the operations of the 8 16 bit PPG The 8 16 bit PPG has the following three operating modes 8 bit PPG independent mode 8 bit prescaler 8 bit PPG mode 16 bit PPG mode ...

Page 333: ...register is reloaded to repeat the counting H is output to the PPG output synchronizing with the count clock When the downcounter value matches the value in the 8 16 bit PPG timer n1 n0 duty setup buffer register PDS After H which is the value of duty setting is output L is output to the PPG output If however the PPG output level reverse bit is set to 1 the PPG output is set and reset inversely fr...

Page 334: ...io of 50 PPS setting value 2 set to PDS 5 4 3 2 1 5 4 3 2 1 5 4 3 2 Synchronizing with machine clock 1 2 α Downcounter value matches matches duty setting value Normal polarity PPGn0 Pin Inversion polarity Counter borrow PPG output source m 5 n 4 Stop 1 n T 2 m T T Count clock cycle m PPS register value n PDS register value α The value changes depending on the count clock selected and the start tim...

Page 335: ...to 1 the 8 bit prescaler PPG timer n1 loads the value in the 8 16 bit PPG timer n1 cycle setup buffer register PPSn1 and starts down count operation When the value of the downcounter matches the value in the 8 16 bit PPG timer n1 duty setup buffer register PDSn1 the PPGn1 output is set to H synchronizing with the count clock After H which is the value of duty setting is output the PPGn1 output is ...

Page 336: ...imer n1 output to 50 When PPG timer n0 is started with the 8 bit prescaler PPG timer n1 being stopped PPG timer n0 does not count When the duty of the 8 bit prescaler PPG timer n1 is set to 0 or 100 PPG timer n0 does not perform counting as the 8 bit prescaler PPG timer n1 output does not toggle Figure 18 6 4 shows the operation of 8 bit prescaler 8 bit PPG mode Figure 18 6 4 Operation of 8 bit Pr...

Page 337: ...PG timer n0 and start down count operation When the count value reaches 1 the values in the cycle setup register are reloaded and the counters repeat the counting When the values of the downcounters match the values in the 8 16 bit PPG timer duty setup buffer registers both the value in PDSn1 for PPG timer n1 and the value in PDSn0 for PPG timer n0 the PPGn0 pin is set to H synchronizing with the ...

Page 338: ...l is output to the PPGn0 pin Figure 18 6 6 shows the operation of 16 bit PPG mode Figure 18 6 6 Operation of 16 bit PPG Mode 256 255 254 2 1 256 255 m 256 n 2 2 1 256 255 1 2 m T 1 n T α 2 Synchronizing with machine clock Count clock Cycle T PEN00 Cycle setup PPSn1 and PPSn0 Duty setup PDSn1 and PDSn0 Counter value Normal polarity PPGn0 Inversion polarity Downcounter value matches matches duty set...

Page 339: ...e the output and interrupt PCn1 4 Select the operating clock enable the output and interrupt select the operation mode PCn0 5 Set the cycle PPS 6 Set the duty PDS 7 Set the 8 16 bit PPG output reverse register REVC 8 Start the 8 16 bit PPG PPGS For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the device data...

Page 340: ... Reference PCn1 8 16 bit PPG timer n1 control register 18 7 1 PCn0 8 16 bit PPG timer n0 control register 18 7 2 PPSn1 8 16 bit PPG timer n1 cycle setting buffer register 18 7 3 PPSn0 8 16 bit PPG timer n0 cycle setting buffer register 18 7 3 PDSn1 8 16 bit PPG timer n1 duty setting buffer register 18 7 4 PDSn0 8 16 bit PPG timer n0 duty setting buffer register 18 7 4 PPGS 8 16 bit PPG start regis...

Page 341: ...ode In 16 bit PPG mode this bit is not set to 1 even when a counter borrow occurs Writing 1 to this bit has no effect on operation Writing 0 to this bit clears it When read by the read modify write RMW type of instruction this bit always returns 1 bit3 POEN1 Output enable bit This bit enables or disables the PPG timer n1 pin output Setting this bit to 1 in 16 bit PPG mode sets the PPG timer n1 pin...

Page 342: ...rescaler In 16 bit PPG mode the settings of these bits have no effect on the operation Note In subclock mode or sub CR clock mode since the time base timer stops operating setting CKS1 2 0 to 0b110 or 0b111 is prohibited bit2 0 Details MCLK machine clock FCH main clock FCRH main CR clock FMCRPLL main CR PLL clock Writing 000 1 MCLK Writing 001 MCLK 2 Writing 010 MCLK 4 Writing 011 MCLK 8 Writing 1...

Page 343: ...ion flag for the PPG cycle downcounter of the PPG timer n0 In 16 bit PPG mode only this bit is effective and the PUF1 bit in the PCn1 register has no effect on operation Note In 8 bit PPG independent mode or 8 bit prescaler 8 bit PPG mode counter borrow detection is always enabled Writing 1 to this bit has no effect on operation Writing 0 to this bit clears it When read by the read modify write RM...

Page 344: ... edge detection pulses from the PPG timer n1 output are used as the count clock for PPG timer n0 Therefore the settings of these bits have no effect on operation In 16 bit PPG mode use these bits to select the operating clock Note In subclock mode or sub CR clock mode since the time base timer stops operating setting CKS0 2 0 to 0b110 or 0b111 is prohibited bit3 Details Writing 0 The PPG timer n0 ...

Page 345: ...eviously written value is reused in the next load 8 bit mode Cycle max 255 0xFF Input clock cycle 16 bit mode Cycle max 65535 0xFFFF Input clock cycle Initialized at reset Do not set the cycle to 0x00 or 0x01 when using the unit in 8 bit PPG independent mode or 8 bit prescaler mode 8 bit PPG mode Do not set the cycle to 0x0000 or 0x0001 when using the unit in 16 bit PPG mode If the cycle settings ...

Page 346: ... to PDSn0 PDSn1 is updated Initialized at reset To set the duty to 0 select 0x00 To set the duty to 100 set it to the same value as the 8 16 bit PPG timer n1 n0 cycle setup register PPSn0 PPSn1 When the 8 16 bit PPG timer n0 n1 duty setup register PDS is set to a larger value than the setting value of the 8 16 bit PPG cycle setup buffer register PPS the PPG output becomes L output in the normal po...

Page 347: ...stops the downcounter operation of PPG timer 11 ch 1 bit2 PEN10 PPG timer 10 ch 1 downcounter operation enable bit This bit enables or stops the downcounter operation of PPG timer 10 ch 1 bit 7 6 5 4 3 2 1 0 Field PEN21 PEN20 PEN11 PEN10 PEN01 PEN00 Attribute R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 Since the number of channels of the 8 16 bit PPG varies among products these bits may ...

Page 348: ...timer 01 ch 0 bit0 PEN00 PPG timer 00 ch 0 downcounter operation enable bit This bit enables or stops the downcounter operation of PPG timer 00 ch 0 bit1 Details Writing 0 Stops the downcounter operation of PPG timer 01 ch 0 Writing 1 Enables the downcounter operation of PPG timer 01 ch 0 bit0 Details Writing 0 Stops the downcounter operation of PPG timer 00 ch 0 Writing 1 Enables the downcounter ...

Page 349: ...1 PPG timer 11 ch 1 output level reverse bit This bit selects the output level of PPG timer 11 ch 1 bit2 REV10 PPG timer 10 ch 1 output level reverse bit This bit selects the output level of PPG timer 10 ch 1 bit 7 6 5 4 3 2 1 0 Field REV21 REV20 REV11 REV10 REV01 REV00 Attribute R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 Since the number of channels of the 8 16 bit PPG varies among pro...

Page 350: ...level reverse bit This bit selects the output level of PPG timer 01 ch 0 bit0 REV00 PPG timer 00 ch 0 output level reverse bit This bit selects the output level of PPG timer 00 ch 0 bit1 Details Writing 0 Selects normal polarity Writing 1 Selects reverse polarity bit0 Details Writing 0 Selects normal polarity Writing 1 Selects reverse polarity ...

Page 351: ...ock an error may occur in the first cycle of the PPG output immediately after the activation The error varies depending on the count clock selected The output however is performed properly in the succeeding cycles Note on interrupts A PPG interrupt is generated when the interrupt enable bit PIE1 PIE0 is set to 1 and the interrupt request flag bit PUF1 PUF0 in the 8 16 bit PPG timer n1 n0 control r...

Page 352: ...MB95630H Series 332 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 18 8 16 BIT PPG 18 8 Notes on Using 8 16 bit PPG ...

Page 353: ... 16 BIT PPG TIMER This chapter describes the functions and operations of the 16 bit PPG timer 19 1 Overview 19 2 Configuration 19 3 Channel 19 4 Pins 19 5 Interrupts 19 6 Operations and Setting Procedure Example 19 7 Registers 19 8 Notes on Using 16 bit PPG Timer ...

Page 354: ...rity Inverted polarity The count operation clock can be selected from 12 different clock sources MCLK MCLK 2 MCLK 4 MCLK 8 MCLK 16 MCLK 32 FCH 27 FCH 28 FCRH 26 FCRH 27 FMCRPLL 26 or FMCRPLL 27 MCLK machine clock FCH main clock FCRH main CR clock FMCRPLL main CR PLL clock Interrupt can be selectively triggered by the following four conditions Occurrence of a start trigger in the PPG timer Occurren...

Page 355: ...unt clock selector CLK LOAD START BORROW 16 bit downcounter S Q R Interrupt selection Prescaler MDSE PGMS OSEL POEN Pin Interrupt of 16 bit PPG IRS1 IRS0 IRQF IREN 16 bit PPG downcounter register Internal data bus STOP Edge detection STRG CNTE RTRG POEN 1 0 16 bit PPG cycle setting buffer register upper 8 bits 16 bit PPG cycle setting buffer register lower 8 bits 16 bit PPG cycle setting buffer re...

Page 356: ...value of 16 bit PPG cycle setting buffer register 16 bit PPG downcounter register upper lower PDCRHn PDCRLn The value of 16 bit downcounter of 16 bit PPG timer is read 16 bit PPG cycle setting buffer register upper lower PCSRHn PCSRLn The compare value for the cycle of 16 bit PPG timer is set 16 bit PPG duty setting buffer register upper lower PDUTHn PDUTLn The compare value for H width of 16 bit ...

Page 357: ...unction PPGn 16 bit PPG timer PPGn output TRGn Trigger n input Table 19 3 2 Registers of 16 bit PPG Timer Register abbreviation Corresponding register Name in this manual PDCRHn 16 bit PPG downcounter register upper PDCRLn 16 bit PPG downcounter register lower PCSRHn 16 bit PPG cycle setting buffer register upper PCSRLn 16 bit PPG cycle setting buffer register lower PDUTHn 16 bit PPG duty setting ...

Page 358: ...PPG Timer The pins of the 16 bit PPG timer are the PPGn pin and TRGn pin PPGn pin This pin serves as a general purpose I O port as well as a 16 bit PPG timer output PPGn A PPG waveform is output to this pin The PPG waveform can be output by using the 16 bit PPG status control register to enable output PCNTLn POEN 1 TRGn pin TRGn Used to start the 16 bit PPG timer by the hardware trigger ...

Page 359: ...er PCNTLn is set to 1 and interrupt requests are enabled PCNTLn IREN 1 in the 16 bit PPG timer an interrupt request is generated and output to the controller Table 19 5 1 Interrupt Control Bits and Interrupt Sources of 16 bit PPG Timer Item Description Interrupt flag bit PCNTLn IRQF Interrupt request enable bit PCNTLn IREN Interrupt type select bits PCNTLn IRS 1 0 Interrupt sources PCNTLn IRS 1 0 ...

Page 360: ...izing with count clock The output changes back to L when the H was output until the value of duty setting The output levels will be reversed if OSEL is set to 1 When the retrigger function is disabled RTRG 0 software triggers STRG 1 are ignored during the operation of the downcounter When the downcounter is not running the maximum time between a valid trigger input occurring and the downcounter st...

Page 361: ...9 6 2 When Retrigger Is Valid in PWM Mode m n 0 1 n T ns 2 m T ns PPG 1 2 Normal polarity Inverted polarity Time 16 bit downcounter value Software trigger n Value of PDUTH PDUTL registers m Value of PCSRH PCSRL registers T Count clock cycle Rising edge detected Trigger ignored PPG m n 0 1 n T ns 2 m T ns PPG PPG 1 2 Normal polarity Inverted polarity Time Counter value Software trigger Rising edge ...

Page 362: ...tput changes back to L when the counter reaches 1 The output levels will be reversed if OSEL is set to 1 Invalidating the retrigger RTRG bit in PCNTHn register 0 Figure 19 6 3 When Retrigger Is Invalid in One shot Mode Validating the retrigger RTRG bit in PCNTHn register 1 Figure 19 6 4 When Retrigger Is Valid in One shot Mode m n 0 Trigger ignored 1 n T ns 2 m T ns PPG PPG 1 2 Normal polarity Inv...

Page 363: ...r in PWM Mode Setting Procedure Example Below is an example of procedure for setting the 16 bit PPG timer Initial setup 1 Set the interrupt level ILR 2 Enable the hardware trigger and interrupts select the interrupt type and enable output PCNTLn 3 Select the count clock and the mode and enable timer operation PCNTHn 4 Set the cycle PCSRHn PCSRLn 5 Set the duty PDUTHn PDUTLn 6 Start the PPG by the ...

Page 364: ...ame Reference PDCRHn 16 bit PPG downcounter register upper 19 7 1 PDCRLn 16 bit PPG downcounter register lower 19 7 1 PCSRHn 16 bit PPG cycle setting buffer register upper 19 7 2 PCSRLn 16 bit PPG cycle setting buffer register lower 19 7 2 PDUTHn 16 bit PPG duty setting buffer register upper 19 7 3 PDUTLn 16 bit PPG duty setting buffer register lower 19 7 3 PCNTHn 16 bit PPG status control registe...

Page 365: ...d from this register Use the MOVW instruction use a 16 bit access instruction to read the PDCRHn register address Use the MOV instruction and read PDCRHn first and then PDCRLn reading PDCRHn automatically copies the lower 8 bits of the downcounter to PDCRLn This register is read only and writing a value to this register has no effect on the operation Note If you use the MOV instruction and read PD...

Page 366: ...n PCSRLn If a downcounter load occurs after writing data to PCSRHn but before writing data to PCSRLn the previous valid PCSRHn PCSRLn value will be loaded to the downcounter If the PCSRHn PCSRLn value is modified during counting the modified value will become effective from the next load of the downcounter Do not set PCSRHn and PCSRLn to 0x00 or PCSRHn to 0x01 and PCSRLn to 0x01 Note If the downco...

Page 367: ...the 16 bit PPG duty setting buffer registers is not transferred to the duty setting registers The relations between the value of the 16 bit PPG duty setting registers and output pulse are explained below When the same value is set in both the 16 bit PPG cycle setting buffer registers and duty setting registers the H level will always be output if normal polarity is set or the L level will always b...

Page 368: ...it PPG timer operation is enabled and the 16 bit PPG timer goes to standby to wait for a trigger bit6 STRG Software trigger bit This bit starts the 16 bit PPG timer by software With the CNTE bit set to 1 writing 1 to the STRG bit starts the 16 bit PPG timer bit5 MDSE Mode select bit This bit selects the operating mode of the 16 bit PPG timer Note While the 16 bit PPG timer is in operation modifyin...

Page 369: ...nd duty setting PDUTHn PDUTLn Writing 0 to this bit disables the PPGn output mask function Writing 1 to this bit enables the PPGn output mask function When the PPGn output polarity setting is set to normal PCNTLn OSEL 0 the output is always masked to L When the polarity setting is se to inverted PCNTLn OSEL 1 the PPGn output is always masked to H bit4 Details Writing 0 Disables using the software ...

Page 370: ...en the 16 bit PPG timer interrupt is generated When read by the read modify write RMW type of instruction this bit always returns 1 bit 7 6 5 4 3 2 1 0 Field EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit7 Details Writing 0 Disables stopping the operation of the 16 bit PPG timer at a falling edge of the TRGn input Writing 1 Enabl...

Page 371: ...d goes to L when a downcounter borrow occurs normal polarity When 1 is written to this bit the 16 bit PPG timer output is inverted inverted polarity bit3 2 Details Writing 00 Trigger by input software trigger or retrigger Writing 01 Counter borrow Writing 10 Rising edge of 16 bit PPG timer output in normal polarity or falling edge of 16 bit PPG timer output in inverted polarity Writing 11 Counter ...

Page 372: ...tting may change and cause the device to malfunction Therefore disable the timer enable bit PCNTHn CNTE 0 or disable the hardware trigger enable bit PCNTLn EGS1 0 EGS0 0 When the cycle and duty are set to the same value an interrupt is generated only once by duty match Moreover if the duty is set to a value greater than the value of the period no interrupt will be generated by a duty match While t...

Page 373: ...BIT RELOAD TIMER This chapter describes the functions and operations of the 16 bit reload timer 20 1 Overview 20 2 Configuration 20 3 Channel 20 4 Pins 20 5 Interrupt 20 6 Operations and Setting Procedure Example 20 7 Registers 20 8 Notes on Using 16 bit Reload Timer ...

Page 374: ...ter lower TMCSRLn is set to 1 the count will start if a valid edge rising falling or both selectable specified by the operating mode select bits MOD 2 0 is input to the TIn pin External gate input operation When the count enable bit CNTE in the timer control status register lower TMCSRLn is set to 1 the count will start if a valid trigger input level L or H selectable specified by the operating mo...

Page 375: ...imer reload register TMRLRHn TMRLRLn is loaded to the 16 bit downcounter and the 16 bit reload timer continues counting In addition since the interrupt request is output by an underflow the 16 bit reload timer can be used as the interval timer One shot mode An interrupt is generated when an underflow occurs on the 16 bit downcounter During counter operation the TOn pin outputs a square waveform in...

Page 376: ...tails of pin names register names and register abbreviations of a product refer to the device data sheet Block Diagram of 16 bit Reload Timer Figure 20 2 1 shows the block diagram of the 16 bit reload timer Figure 20 2 1 Block Diagram of 16 bit Reload Timer 16 bit reload timer reload register TMRLRHn TMRLRLn 16 bit reload timer timer register TMRHn TMRLn Input control circuit Valid clock judgment ...

Page 377: ...e 16 bit downcounter 16 bit reload timer timer register upper lower TMRHn TMRLn TMRHn and TMRLn form a 16 bit downcounter Reading these registers returns the current count value 16 bit reload timer reload register upper lower TMRLRHn TMRLRLn This register sets the load value to the 16 bit downcounter The register loads the setting value of the 16 bit reload timer reload register to the 16 bit down...

Page 378: ...tively Table 20 3 1 Pins of 16 bit Reload Timer Pin name Pin function TOn Timer output TIn Timer input Table 20 3 2 Registers of 16 bit Reload Timer Register abbreviation Corresponding register Name in this manual TMCSRHn 16 bit reload timer control status register upper TMCSRLn 16 bit reload timer control status register lower TMRHn 16 bit reload timer timer register upper TMRLn 16 bit reload tim...

Page 379: ...ny pulse edge input to this pin is counted during counter operation To use it as the external pulse input pin in counter operation set the corresponding bit in the port direction register DDR to 0 TOn pin This pin is used both as a general purpose I O port and as the output pin of the 16 bit reload timer TOn TOn This pin outputs waveforms of the 16 bit reload timer When this pin is used as the 16 ...

Page 380: ...er sets the underflow interrupt request flag bit UF in the 16 bit reload timer control status register lower TMCSRLn to 1 when an underflow occurs in the 16 bit downcounter 0x0000 0xFFFF If the underflow interrupt request has been enabled TMCSRLn INTE 1 the interrupt request will be output to the interrupt controller Table 20 5 1 Interrupt Control Bits and Interrupt Sources of 16 bit Reload Timer ...

Page 381: ...er register Holds the value at stop Value immediately after reset 0x0000 WAIT state CNTE 1 WAIT 1 TIn pin Only trigger input is valid TOn pin 16 bit reload timer reload register output 16 bit reload timer timer register Holds the value at stop Until loaded immediately after reset 0x0000 RUN state CNTE 1 WAIT 0 TIn pin 16 bit reload timer input TOn pin 16 bit reload timer reload register output 16 ...

Page 382: ...Hn MOD 2 0 5 Enable the output TMCSRLn OUTE 1 6 Select the output level TMCSRLn OUTL 7 Select reload TMCSRLn RELD 8 Enable a count TMCSRLn CNTE 1 9 Perform the software trigger TMCSRLn TRG 1 10 Enable underflow interrupt TMCSRLn INTE 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this hardware manual and INTERRUPT SOURCE TABLE in the device data sheet In...

Page 383: ...bit downcounter and downcounting starts If counting is enabled when the count enable bit CNTE and software trigger bit TRG are set to 1 at the same time the counting starts at the same time If the reload select bit RELD is 1 the value of the 16 bit reload timer reload register upper lower TMRLRHn TMRLRLn is reloaded to the 16 bit downcounter and the count continues when the 16 bit counter underflo...

Page 384: ... the one with an external trigger Figure 20 6 4 shows the external trigger input operation in reload mode Figure 20 6 4 Count Operation in Reload Mode External Trigger Input Operation Gate input operation The count starts when the count enable bit CNTE is set to 1 and the software trigger bit TRG is also set to 1 The timer continues counting while the valid gate input level L or H selectable set b...

Page 385: ...e count is started simultaneously If the reload select bit RELD is 0 the 16 bit counter halts at 0xFFFF when the 16 bit counter underflows 0x0000 0xFFFF In this case the underflow interrupt request flag bit UF is set to 1 and if the underflow interrupt request enable bit INTE is 1 an interrupt request is output A square waveform can be output from the TOn pin to indicate that the count is in progr...

Page 386: ...input operation The count starts when the count enable bit CNTE is 1 and the software trigger bit TRG is also set to 1 The timer continues counting as long as the trigger input enable level L or H selectable specified by the operating mode select bits MOD 2 0 is input to the TIn pin Figure 20 6 8 shows the external gate input operation in one shot mode Figure 20 6 8 Count Operation in One shot Mod...

Page 387: ...he pulses input to the TIn pin external count clock Operation of reload mode If the reload select bit RELD is 1 the value set in the 16 bit reload timer reload register TMRLRHn TMRLRLn is reloaded to the 16 bit counter and the count continues when the 16 bit counter underflows 0x0000 0xFFFF The underflow interrupt request flag bit UF in the 16 bit reload timer control status register lower TMCSRLn...

Page 388: ...t flag bit UF in the 16 bit reload timer control status register lower TMCSRLn is set to 1 with the underflow interrupt enable bit INTE set to 1 The TOn pin outputs a square waveform indicating that counting is in progress Figure 20 6 11 shows the count operation in one shot mode Figure 20 6 11 Counter Operation in One shot Mode Event Count Mode TIn pin Counter 1 0000 1 0000 1 0000 1 Data load sig...

Page 389: ... Reload Timer Registers Register abbreviation Register name Reference TMCSRHn 16 bit reload timer control status register upper 20 7 1 TMCSRLn 16 bit reload timer control status register lower 20 7 2 TMRHn 16 bit reload timer timer register upper 20 7 3 TMRLn 16 bit reload timer timer register lower 20 7 3 TMRLRHn 16 bit reload timer reload register upper 20 7 4 TMRLRLn 16 bit reload timer reload ...

Page 390: ...d 0b110 inclusive is written to these bits the 16 bit reload timer counts with the internal clock internal clock mode The internal clock is generated by the prescaler For details see 3 9 Operation of Prescaler When 0b111 is written to these bits the 16 bit reload timer counts with the edge of the external event clock event count mode MCLK machine clock FCH main clock FMCRPLL main CR PLL clock FCRH...

Page 391: ... is invalid Select the valid signal level H or L with the MOD0 bit The 16 bit reload timer counts using TMRHn TMRLn only while the valid signal level is being input Note When the MOD 2 0 bits are 0b000 external pin input becomes invalid In this case use the TRG bit to start the 16 bit reload timer by using the software Event count mode CSL 2 0 0b111 The MOD2 bit is always set to 0 The external eve...

Page 392: ...occurs the 16 bit reload timer stops counting When 1 is written to this bit the 16 bit reload counter enters reload mode In reload mode when an underflow occurs the value set to the 16 bit reload timer reload register TMRLRHn TMRLRLn is loaded to the 16 bit reload timer timer register TMRHn TMRLn and the 16 bit reload timer continues counting bit 7 6 5 4 3 2 1 0 Field OUTE OUTL RELD INTE UF CNTE T...

Page 393: ...t reload timer reload register TMRLRHn TMRLRLn is reloaded to the 16 bit reload timer timer register TMRHn TMRLn and then the 16 bit reload timer starts counting from the next count clock input Note Writing 1 to this bit and the CNTE bit simultaneously starts the 16 bit reload timer counting operation The read value of this bit is always 0 However this bit keeps reading 1 from the point at which 1...

Page 394: ... timer starts downcounting Notes This register can read the count value even during the counting operation of the 16 bit reload timer To read this register use a word transfer instruction or read the upper byte of this register first and then its lower byte The circuit of the 16 bit reload timer timer register is configured so that the lower byte value is saved when the upper byte value is read Th...

Page 395: ...gister can be modified during the counting operation of the 16 bit reload timer Notes A value can be written to this register even during the counting operation of the 16 bit reload timer To write a value to this register use a word transfer instruction or write the upper byte of this register first and then its lower byte The 16 bit reload timer reload register has a circuit configured so that th...

Page 396: ...truction or read the upper byte of this register first and then its lower byte A value can be written to the 16 bit reload timer reload register TMRLRHn TMRLRLn even during the counting operation of the 16 bit reload timer To write a value to this register use a word transfer instruction or write the upper byte of this register first and then its lower byte Notes on interrupts With the underflow i...

Page 397: ...E GENERATOR This chapter describes the specifications and operations of the multi pulse generator 21 1 Overview 21 2 Block Diagram 21 3 Pins 21 4 Interrupts 21 5 Operations 21 6 Registers 21 7 Notes on Using Multi pulse Generator 21 8 Sample Program for Multi pulse Generator ...

Page 398: ...er OPDUR and the 16 bit MPG output data register lower OPDLR The 16 bit MPG output data register upper lower OPDUR OPDLR determines the 16 bit PPG timer output to which OPT output OPT5 to OPT0 By loading different 16 bit MPG output data buffer register upper lower OPDBRHx OPDBRLx to the 16 bit MPG output data register upper lower OPDUR OPDLR various combination of OPT outputs OPT5 to OPT0 can be o...

Page 399: ...h during sequencer state changes the write timing WTO needs to be delayed and synchronized with the next coming edge of PPG output waveform See Figure 21 1 1 and Figure 21 1 2 for details This function can be enabled or disabled by software The WTS 1 0 bits in the 16 bit MPG input control register upper IPCUR are used to disable this function and to select the polarity of the PPG edge to synchroni...

Page 400: ...ct the rotor position of the DC motor There is a noise filter for all SNI2 to SNI0 input and Table 21 1 2 shows the noise width for noise filter of SNI2 to SNI0 pins The followings are conditions for the input position detect circuit 3 edge selection for all SNI2 to SNI0 Rising edge falling edge and both edges Compare the levels of SNI2 to SNI0 inputs with RDA 2 0 bits in the output data register ...

Page 401: ...d independently of the multi pulse generator 2 See Multi pulse Generator Interrupt Sources in 21 4 Interrupts 16 bit PPG timer The 16 bit PPG timer is used to provide the PPG signal for the waveform sequencer Details of the 16 bit PPG timer are described in CHAPTER 19 16 BIT PPG TIMER DTTI SNI2 SNI1 SNI0 TIN0 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 WAVEFORM SEQUENCER Pin Pin Pin Pin PPG1 Pin Pin Pin Pin Pin...

Page 402: ...0 Registers OPDUR Register OPDLR Register Data Write Control Unit 3 3 16 bit Timer 16 BIT MPG OUTPUT DATA BUFFER REGISTER 12 OPDBRHx Register OPDBRLx Register WTIN1 BNKF CCIRT PPG1 WTO TIN0O WTIN0 3 DTTI Control Circuit OPCUR Register OPCLR Register Comparison Circuit IPCUR Register IPCLR Register Sync Circuit WTS1 WTS0 Write Timing Interrupt Compare Match Interrupt Compare Clear Interrupt Positio...

Page 403: ...KF bit and RDA 2 0 bits in the 16 bit MPG output data register upper OPDUR to select which pair of the 16 bit MPG output data buffer register upper and 16 bit MPG output data buffer register lower OPDBRHx and OPDBRLx is loaded to the 16 bit MPG output data register upper and the 16 bit MPG output data register lower OPDUR and OPDLR DTTI control The DTTI control is used to stop the multi pulse gene...

Page 404: ...and OPDBRLB to OPDBRH0 and OPDBRL0 OPDBRHx is the upper byte register and OPDBRLx the lower byte register When a write signal is generated in the data write control circuit the values of the OPDBRHx register and OPDBRLx register specified by the BNKF bit and the RDA 2 0 bits are transferred to the 16 bit MPG output data register upper OPDUR and the 16 bit MPG output data register lower OPDLR Howev...

Page 405: ...up counter and the 16 bit MPG compare clear register upper lower CPCUR CPCLR 16 bit MPG compare clear register upper CPCUR and 16 bit MPG compare clear register lower CPCLR The 16 bit MPG compare clear register upper CPCUR and the 16 bit MPG compare clear register lower CPCLR are used to store the 16 bit value which is used to compare the value of the 16 bit up counter 16 bit up counter Prescaler ...

Page 406: ...r such as the clock frequency enable disable the interrupt Block Diagram of Data Write Control Unit Figure 21 2 4 Block Diagram of Data Write Control Unit 1 Cycle delay circuit The 1 Cycle Delay Circuit is used to delay one CPU clock cycle of the trigger signal when the 16 bit MPG output data buffer register 0 upper lower OPDBRH0 OPDBRL0 is written Selector 0 The selector 0 is used to select from ...

Page 407: ...ctor is used to detect the falling edge of the 16 bit reload timer output TOUT Rising and falling edge detector The rising and falling edge detector is used to detect the rising and falling edge of the 16 bit reload timer output TOUT When timer underflow trigger is used in following modes the WTIN0 signal is generated by the trigger edge selected by OPS 2 0 bits Table 21 2 1 TOUT Trigger Edge Sele...

Page 408: ...is used to compare the edge of the position input SNI2 to SNI0 with 3 different kind of edge setting If the selector is selected a data write time output signal is generated when an effective edge is detected at the one of SNI2 to SNI0 inputs Noise filter The noise filter is used to filter out the noise of the input signal in which there are 4 kind of sampling clock for selection Selector The sele...

Page 409: ...the OPT0 to OPT5 pins function as waveform output pins for the multi pulse generator SNI0 to SNI2 pins The SNI0 to SNI2 pins function as the position detect input pins for the multi pulse generator Set the corresponding bits in the port direction register DDR to 0 to use the SNI0 SNI1 and SNI2 pins as input ports DTTI pin The DTTI pin functions as the DTTI input pin for the multi pulse generator S...

Page 410: ... to 1 this write timing interrupt is generated when the write timing is generated by the data write control circuit to make data transfer from one of 12 pairs of 16 bit MPG output data buffer register upper lower OPDBRHB and OPDBRLB OPDBRH0 and OPDBRL0 to the 16 bit MPG output data register upper lower OPDUR OPDLR When this interrupt is generated the write timing interrupt flag bit in the 16 bit o...

Page 411: ...pt is generated the DTTI interrupt flag bit in the 16 bit output control register upper OPCUR DTIF is set to 1 Multi pulse Generator Interrupt Sources Interrupt A DTTI This interrupt is generated when a DTTI interrupt occurs DTTI interrupt is generated if OPCUR DTIE is set to 1 when an L level input is detected at the DTTI pin Interrupt B write timing compare clear This interrupt is generated when...

Page 412: ...ata register upper lower OPDUR OPDLR the OPTx pin outputs the corresponding kind of waveforms H or L or PPG output See Table 21 5 1 Output Data Register Block Diagram Figure 21 5 1 Output Data Register Block Diagram OP51 OP50 OP41 OP40 OUTPUT CONTROL CIRCUIT OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 DTTI OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 BNKF RDA2 RDA1 RDA0 OUTPUT DATA REGISTER 16 BIT PPG TIMER DECODER ...

Page 413: ...t waveform is updated Moreover the output level can be compulsorily fixed by the DTTI pin input The OPTx output waveform timing diagram is shown in Figure 21 5 2 and the operation is explained in following sections OPTx Output Waveform Timing Diagram WTS 1 0 0b00 Figure 21 5 2 OPTx Output Waveform Timing Diagram WTS 1 0 0b00 Table 21 5 1 16 bit MPG Output Data Register Upper Lower OPDUR OPDLR OPx1...

Page 414: ...t MPG input control register upper IPCUR is set to 0 only the edge detection of SNIx pins enabled by the SEE 2 0 bits will engage in the edge detection operation for the position detection For instance when only the SEE0 bit is set to 1 the input edge to the pin SNI0 is in effect the data write output signal is generated only when an effective edge is detected at the SNI0 pin See Figure 21 5 3 for...

Page 415: ...1 Output Condition and Register Setting CMPE CPE1 CPE0 SEEx WTIN1 Output Condition 0 0 0 0 No output Initial value 0 0 1 0 1 0 No output 0 0 0 1 No output 0 0 1 1 Detects SNIx rising edge 0 1 0 1 Detects SNIx falling edge 0 1 1 1 Detects SNIx both edges 1 0 0 0 1 Setting prohibited 1 0 1 0 1 Detects SNIx rising edge and SNIx RDAx comparison match 1 1 0 0 1 Detects SNIx falling edge and SNIx RDAx c...

Page 416: ...ed by the position detection comparison circuit Triggered by the position detection input SNI2 to SNI0 Triggered either by the 16 bit reload timer underflow or by the position detection input At the mean time the cause of generation of WTO will be defined by setting different value of the OPS 2 0 bits in the 16 bit MPG output control register upper OPCUR Signal Flow Diagram for OPDBRH0 and OPDBRL0...

Page 417: ...OPS 2 0 0b001 Figure 21 5 7 Signal Flow Diagram for Reload Timer Underflow OPS 2 0 0b001 The 16 bit reload timer can be started by TIN input or a software trigger The write signal is controlled by the 16 bit reload timer underflow OPS 2 0 WTO 0b000 ODBR1W RDA 2 0 ODBR0W OPDBRL0 0 0b001 0b101 OP00 OPDBRL1 0 OPDUR POSITION 16 BIT RELOAD TIMER TIN TOUT DETECTION TIN0O WTIN0 WTIN1 WTO TIN0 SNI2 to TI1...

Page 418: ...for Reload Timer Position Detect OPS 2 0 0b011 or 0b111 At this setting the16 bit reload timer is started by the compare match or effective edge input of the position detection circuit write signal is then generated whenever the 16 bit reload timer is underflow The compare match is triggered by any effective edge change in SNI2 to SNI0 pins POSITION 16 BIT RELOAD TIMER TIN TOUT DETECTION TIN0O WTI...

Page 419: ...n underflow occurs in the 16 bit reload timer The compare match is triggered by any effective edge change in SNI2 to SNI0 pins OPDUR and OPDLR Write Timing Diagram OPS 2 0 0b001 0b010 0b011 0b100 0b101 0b110 or 0b111 Figure 21 5 11 OPDUR and OPDLR Write Timing Diagram OPS 2 0 0b001 0b010 0b011 0b100 0b101 0b110 or 0b111 POSITION 16 BIT RELOAD TIMER TIN TOUT DETECTION TIN0O WTIN0 WTIN1 WTO TIN0 SNI...

Page 420: ...he 16 bit MPG output data register upper lower OPDUR OPDLR and the OPx1 OPx0 bits decide the shape of the output waveform The output waveform is updated automatically as long as the write timing WTO is generated An example of setting the 16 bit MPG output data buffer register upper lower OPDBRH OPDBRL is shown in Table 21 5 3 Table 21 5 3 16 bit MPG output data buffer register upper lower OPDBRH O...

Page 421: ...value of the 16 bit MPG output data register upper lower OPDUR OPDLR The following sequence begins to operate according to the write timing generated No 4 No 6 No 2 No 3 No 1 No 5 No A No B No 9 No 4 and recycle The data is transferred to the 16 bit MPG output data register upper lower OPDUR OPDLR sequentially The 16 bit MPG output data buffer register upper lower OPDBRHx OPDBRLx are not used if i...

Page 422: ... One shot Position Detection One shot Position Detection and 16 bit Reload Timer Underflow One shot Position Detection or 16 bit Reload Timer Underflow The value of the 16 bit MPG output data buffer register upper lower OPDBRHx OPDBRLx that is selected by the BNKF bit and RDA 2 0 bits in the 16 bit MPG output data register upper OPDUR is transferred to the 16 bit MPG output data register upper low...

Page 423: ...tructure between OPDBRHx OPDBRLx and OPDUR OPDLR 12 TO 1 SELECTOR TO OUTPUT CONTROL CIRCUIT OPDBRH0 OPDBRL0 OPS1 OPS0 RDA2 RDA1 RDA0 BNKF OPS2 OPDUR OPDLR WTO OPDBRH1 OPDBRL1 OPDBRH2 OPDBRL2 OPDBRH3 OPDBRL3 OPDBRH4 OPDBRL4 OPDBRH5 OPDBRL5 OPDBRH6 OPDBRL6 OPDBRH7 OPDBRL7 OPDBRH8 OPDBRL8 OPDBRH9 OPDBRL9 OPDBRHA OPDBRLA OPDBRHB OPDBRLB ...

Page 424: ...13 Timing Generated by OPDBRH0 and OPDBRL0 Write OPS 2 0 0b000 Note Word access to the output data buffer register 0 must be used in this operation byte access to either lower register or upper register does not start any transfer operation The reload timer is free to be used in this operation mode Figure 21 5 13 Timing Generated by OPDBRH0 and OPDBRL0 Write OPS 2 0 0b000 OP0 1 0 OPDLR PPG OPT0 0b...

Page 425: ...x which is triggered by the 16 bit reload timer underflow is shown in Figure 21 5 14 and Figure 21 5 15 Timing Generated by Reload Timer Underflow Figure 21 5 14 Timing Generated by Reload Timer Underflow No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 BNKF RDA2 RDA1 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 Timer 16 bit reload timer underflow occurs RDA0 starts...

Page 426: ...low is generated as shown in Figure 21 5 15 In order to use this method the reload timer should be used in Reload Mode Software trigger is needed to be used for the startup of the reload timer The 16 bit reload timer is needed for setting the update time in advance and executing the continuous control action Timing Generated by Reload Timer Underflow OPS 2 0 0b001 Figure 21 5 15 Timing Generated b...

Page 427: ...e 21 5 17 Timing Generated by Position Detection Figure 21 5 16 Timing Generated by Position Detection 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 SNI2 SNI1 SNI0 BNKF RDA2 RDA1 RDA0 Write signal is generated when theres is a comparison match between RDA 2 0 and SNI2 SNI0 or any effective edge input at SNI2 SNI0 The comparison is triggered by the input edge...

Page 428: ...PG output data buffer register upper lower OPDBRHx OPDBRLx specified by the BNKF bit and the RDA 2 0 bits is transferred to the 16 bit MPG output data register upper lower OPDUR OPDLR and the output data is renewed automatically when pins SNI2 to SNI0 are compared with the value of the RDA 2 0 bits and matches The reload timer can be used in this operation mode Timing Generated by Position Detecti...

Page 429: ...mer underflow is shown in Figure 21 5 18 and Figure 21 5 19 Timing Generated by Position Detection and Timer Underflow Figure 21 5 18 Timing Generated by Position Detection and Timer Underflow No 0 No 4 No 6 No 2 No 3 No 1 No 5 No A 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 BNKF RDA2 RDA1 RDA0 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 SNI2 SNI1 SNI0 16 bit reload timer down counting time Write s...

Page 430: ...e effective edge input to pin SNIx is shown in Figure 21 5 19 The 16 bit reload timer is started when the pins SNI2 to SNI0 are compared with the value of the RDA 2 0 bits and matches Data transfer from the 16 bit MPG output data buffer register upper lower OPDBRHx OPDBRLx specified by the RDA 2 0 bits to the 16 bit MPG output data register upper lower OPDUR OPDLR is triggered by the underflow of ...

Page 431: ...ing Generated by Position Detection and Timer Underflow OPS 2 0 0b011 Figure 21 5 19 Timing Generated by Position Detection and Timer Underflow OPS 2 0 0b011 OP0 1 0 OPDLR PPG OPT0 0b01 0b00 0b11 0b00 0b10 0b110 0b100 0b010 0b011 0b001 WTO RDA 2 0 OPDUR SNI0 SNI1 SNI2 Reload timer counter action TIN0O WTIN0 TOUT TIN 0b11 ...

Page 432: ... 0b100 Timing Generated by Position Detection or Timer Underflow Figure 21 5 20 Timing Generated by Position Detection or Timer Underflow 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 16 bit reload timer underflow occurs Write signal is generated when theres is a comparison match between RDA 2 0 and SNI2 SNI0 or any effective edge input at SNI2 SNI0 The comp...

Page 433: ...Timing Generated by Position Detection or Timer Underflow OPS 2 0 0b100 Figure 21 5 21 Timing Generated by Position Detection or Timer Underflow OPS 2 0 0b100 0b010 0b100 0b101 0b011 0b111 RDA 2 0 OPDUR Reload Timer Counter Action WTIN0 TOUT SNI0 SNI1 SNI2 WTIN1 OP0 1 0 OPDLR PPG OPT0 0b01 0b00 0b11 0b00 0b10 WTO 0b11 ...

Page 434: ...hat of the position detection except that after the first valid position is detected no further position detection is recognized until the operation mode is changed from one shot position detection to another operation mode The OPTx output waveform is shown in Figure 21 5 22 The reload timer is free to be used in this operation mode Timing Generated by One shot Position Detection OPS 2 0 0b110 Fig...

Page 435: ...hat after the first valid position is detected no further position detection is recognized until the operation mode is changed from one shot position detection and reload timer underflow to another operation mode The OPTx output waveform is shown in Figure 21 5 23 In order to use this method the reload timer should be used in one shot mode TIN0O must be longer than two machine cycles Timing Genera...

Page 436: ... underflow is the same as that of the position detection or reload timer underflow except that after the first valid position is detected no further position detection is recognized until the operation mode is changed from one shot position detection or reload timer underflow to another operation mode The OPTx output waveform is shown as in Figure 21 5 24 Timing Generated by One shot Position Dete...

Page 437: ... level is placed at the DTTI pin the output of OPTx is fixed at the inactive level The software can set the inactive level for each OPTX pin in PDRx of port x the OPTx pin is then driven by the data written in the PDRx of port x Even while the output is fixed at the inactive level by the input of the DTTI pin the timer keeps running the position detection function does not stop and the data transf...

Page 438: ...t Timing Diagram D 1 0 0b00 Figure 21 5 26 DTTI Circuit Timing Diagram D 1 0 0b00 Note In the worst case the time from DTTI being recognized after noise cancellation to DTISP in effect takes 2 cycles in best case it takes 1 cycle DTTI DTIF DTIE DTTI DTIF NRSL NRSL DTIE DTISP DTISP 4 Cycles MCLK DTIF is cleared by writing 0 to it ...

Page 439: ...tion X 0 X DTTI has no effect on OPTx Initial value 0 1 0 DTTI takes effect Noise filter is not enabled An L input at DTTI pin triggers the output of the inactive level set in PDRx The DTTI interrupt is generated 0 1 1 DTTI has no effect on OPTx 1 1 0 DTTI takes effect Noise filter is enabled An L input at DTTI pin triggers the output of the inactive level set in PDRx The DTTI interrupt is generat...

Page 440: ...uch as stop mode in which the oscillator stops SNI2 to SNI0 Pins Noise Cancellation Function When SNC 2 0 bits in the 16 bit MPG input control register lower IPCLR are set to 1 the noise cancellation function for SNI2 to SNI0 pins input can be used When the noise cancellation function is selected the input is delayed for about four machine clocks by the noise cancellation circuit Since the noise c...

Page 441: ...ue is cleared in the following conditions When an overflow has occurred When a match with the 16 bit MPG compare clear register upper lower CPCUR CPCLR is detected When 1 is written to the TCLR bit in the TCSR register during operation When a write timing signal is generated and MODE bit in TCSR is 0 When a position detection signal is generated and MODE bit in TCSR is 1 Reset An interrupt can be ...

Page 442: ...ure 21 5 27 Clearing the Counter by an Overflow Figure 21 5 28 Clearing the Counter upon a Match with Compare Clear Register 0xFFFF 0xBFFF 0x7FFF 0x3FFF 0x0000 Counter value Overflow Time Reset Interrupt 0xFFFF 0xBFFF 0x7FFF 0x3FFF 0x0000 0xBFFF Counter value Match Time Reset Compare clear Interrupt Match register value ...

Page 443: ...nt Timing The counter can be cleared upon a reset software clear TCLR a match with the compare clear register the Write Timing signal or the Position Detection signal By a reset the counter is immediately cleared By a match with the compare clear register software clear TCLR the Write Timing signal or the Position Detection signal the counter is cleared in synchronization with the count timing Fig...

Page 444: ... GENERATOR 21 5 Operations 16 bit Timer Buffer Operation Timing Diagram Figure 21 5 31 16 bit Timer Buffer Operation Timing Diagram Timer buffer 0 or 1 CLK WTIN1 MODE WTO Buffer load signal 0x0001 0x0000 Timer reset TMEN Counter value 0x0002 0x0002 0x0000 0x0001 0x0002 0xXXXX CPU clock TCSR ...

Page 445: ...oaded to the 16 bit MPG compare clear register upper CPCUR and the 16 bit MPG compare clear register lower CPCLR are the same as the timer counter value the comparison operation will not be performed until the next occasion in which the values of CPCUR and CPCLR are the same as the timer counter value The Compare Clear interrupt shares the same interrupt vector with the Write Timing interrupt whil...

Page 446: ... register upper 21 6 3 1 OPDLR 16 bit MPG output data register lower 21 6 3 2 OPDBRHx 16 bit MPG output data buffer register upper 21 6 4 1 OPDBRLx 16 bit MPG output data buffer register lower 21 6 4 2 IPCUR 16 bit MPG input control register upper 21 6 5 1 IPCLR 16 bit MPG input control register lower 21 6 5 2 CPCUR 16 bit MPG compare clear register upper 21 6 6 CPCLR 16 bit MPG compare clear regi...

Page 447: ... selects the noise cancellation function to be used when the DTTI pin input is enabled The noise cancellation circuit starts the internal n bit counter when an active level is input the value of n can be 2 3 4 or 5 which depends on the setting of D 1 0 bits in the noise cancellation control register If the active level is held until the counter overflows the circuit accepts input from the DTTI pin...

Page 448: ...he write timing interrupt When this bit is set to 1 and the write timing interrupt request flag bit WTIF is also set to 1 a write timing interrupt is generated bit4 2 Details Writing 000 Data is written to OPDBRHx OPDBRLx by the software and then is transferred from OPDBRHx OPDBRLx to OPDUR OPDLR Writing 001 An underflow in the 16 bit reload timer triggers data transfer from OPDBRHx OPDBRLx to OPD...

Page 449: ...ng 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit6 PDIE Position detection interrupt enable bit This bit enables or disables the position detection interrupt When this bit is set to 1 and the position detection interrupt request flag bit PDIF is also set to 1 a position detection inte...

Page 450: ...E1 OPT1 output enable bit This bit enables or disables OPT1 pin output bit0 OPE0 OPT0 output enable bit This bit enables or disables OPT0 pin output bit4 Details Writing 0 Disables OPT4 pin output Writing 1 Enables OPT4 pin output bit3 Details Writing 0 Disables OPT3 pin output Writing 1 Enables OPT3 pin output bit2 Details Writing 0 Disables OPT2 pin output Writing 1 Enables OPT2 pin output bit1 ...

Page 451: ...UR and the 16 bit MPG output data register lower OPDLR are two 8 bit registers used to read the 16 bit MPG output data register value Always use one of the following methods to access these registers Use the MOVW instruction use a 16 bit access instruction to read the OPDUR register address Use the MOV instruction to read OPDUR first and then OPDLR OPDLR will be updated when OPDUR is read For deta...

Page 452: ... OPDBRL1 is to be loaded to OPDUR OPDLR Reading 0010 Indicates that data in OPDBRH2 OPDBRL2 is to be loaded to OPDUR OPDLR Reading 0011 Indicates that data in OPDBRH3 OPDBRL3 is to be loaded to OPDUR OPDLR Reading 0100 Indicates that data in OPDBRH4 OPDBRL4 is to be loaded to OPDUR OPDLR Reading 0101 Indicates that data in OPDBRH5 OPDBRL5 is to be loaded to OPDUR OPDLR Reading 0110 Indicates that ...

Page 453: ...rm bits These bits indicate the output waveform to the OPT4 pin bit1 0 Details Reading 00 Indicates that L level is output to the OPT4 pin Reading 01 Indicates that the output of the PPG timer is output to the OPT4 pin Reading 10 Indicates that the inverted output is output to the OPT4 pin Reading 11 Indicates that H level is output to the OPT4 pin ...

Page 454: ... to the OPT3 pin Reading 01 Indicates that the output of the PPG timer is output to the OPT3 pin Reading 10 Indicates that the inverted output is output to the OPT3 pin Reading 11 Indicates that H level is output to the OPT3 pin bit5 4 Details Reading 00 Indicates that L level is output to the OPT2 pin Reading 01 Indicates that the output of the PPG timer is output to the OPT2 pin Reading 10 Indic...

Page 455: ...gister and OPDBRLx the lower byte register The data of the OPDBRHx OPDBRLx registers specified in the BNKF bit and RDA 2 0 bits in the OPDBRHx register is loaded to the OPDUR and OPDLR registers at the rising edge of the write signal generated by the data write control unit For details of the 16 bit MPG output data buffer register upper OPDBRHx see 21 6 4 1 16 bit MPG Output Data Buffer Register U...

Page 456: ...0 OPDBRL0 as the next data to be loaded to OPDUR OPDLR Writing 0001 Selects data in OPDBRH1 OPDBRL1 as the next data to be loaded to OPDUR OPDLR Writing 0010 Selects data in OPDBRH2 OPDBRL2 as the next data to be loaded to OPDUR OPDLR Writing 0011 Selects data in OPDBRH3 OPDBRL3 as the next data to be loaded to OPDUR OPDLR Writing 0100 Selects data in OPDBRH4 OPDBRL4 as the next data to be loaded ...

Page 457: ... OPT4 pin after the data in the OPDBRHx OPDBRLx specified in the BNKF bit and RDA 2 0 bits is loaded to the OPDUR OPDLR register bit1 0 Details Writing 00 Selects L level as the waveform to be output to the OPT4 pin Writing 01 Selects the output of the PPG timer as the waveform to be output to the OPT4 pin Writing 10 Selects the inverted output as the waveform to be output to the OPT4 pin Writing ...

Page 458: ... data in the OPDBRHx OPDBRLx specified in the BNKF bit and RDA 2 0 bits is loaded to the OPDUR OPDLR register bit 7 6 5 4 3 2 1 0 Field OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit7 6 Details Writing 00 Selects L level as the waveform to be output to the OPT3 pin Writing 01 Selects the output of the PPG timer as the waveform to...

Page 459: ... OPT0 pin after the data in the OPDBRHx OPDBRLx specified in the BNKF bit and RDA 2 0 bits is loaded to the OPDUR OPDLR register bit1 0 Details Writing 00 Selects L level as the waveform to be output to the OPT0 pin Writing 01 Selects the output of the PPG timer as the waveform to be output to the OPT0 pin Writing 10 Selects the inverted output as the waveform to be output to the OPT0 pin Writing ...

Page 460: ...gister upper lower IPCUR IPCLR consists of two 8 bit registers controlling position detection input IPCUR is the upper byte register and IPCLR the lower byte register For details of the 16 bit MPG input control register upper IPCUR see 21 6 5 1 16 bit MPG Input Control Register Upper IPCUR For details of the 16 bit MPG input control register lower IPCLR see 21 6 5 2 16 bit MPG Input Control Regist...

Page 461: ... interrupt is generated Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit4 CPIE Compare interrupt enable bit This bit enables or disables the compare interrupt When this bit is set to 1 and the compare interrupt request flag bit CPIF is also set to 1 a compare interrupt is genera...

Page 462: ...he compare operation in position detection bit3 1 Details Writing 000 If the RDA 2 0 bits are 000 a compare match occurs Writing 001 If the RDA 2 0 bits are 001 a compare match occurs Writing 010 If the RDA 2 0 bits are 010 a compare match occurs Writing 011 If the RDA 2 0 bits are 011 a compare match occurs Writing 100 If the RDA 2 0 bits are 100 a compare match occurs Writing 101 If the RDA 2 0 ...

Page 463: ... 1 0 and S0 1 0 bits in the noise cancellation control register If the active level is held until the counter overflows the circuit accepts input from the SNI2 to SNI0 pins Therefore the pulse width of noise that can be cancelled is about 2n machine cycles Note When the noise cancellation circuit is enable the input becomes invalid in a mode such as stop mode in which the internal clock is stopped...

Page 464: ...setting the CMPE bit in the input control register upper IPCUR to 0 bit0 SEE0 SNI0 enable bit This bit enables or disables the edge detection on the SNI0 pin Set this bit before setting the CMPE bit in the input control register upper IPCUR to 0 bit2 Details Writing 0 Disables the edge detection on the SNI2 pin Writing 1 Enables the edge detection on the SNI2 pin bit1 Details Writing 0 Disables th...

Page 465: ...ruction use a 16 bit access instruction to read and write the CPCUR register address Use the MOV instruction to read or write CPCUR first and then CPCLR Register Configuration Notes When the values of these registers match the count value of the 16 bit timer the 16 bit timer is reset to 0x0000 and the compare clear interrupt request flag bit TCSR ICLR is set In addition when the interrupt operatio...

Page 466: ...timer at the point at which a write timing trigger or a position detection trigger is generated The counter is cleared to 0x0000 upon the generation of the trigger Always use one of the following methods to access this register Use the MOVW instruction use a 16 bit access instruction to read the TMBUR register address Use the MOV instruction to read or write TMBUR first and then TMBLR Register Con...

Page 467: ... bit timer value the counter of the 16 bit timer is cleared and this bit is set to 1 With the compare clear interrupt request already enabled TCSR ICRE 1 when the ICLR bit is set to 1 a compare clear interrupt is generated Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit 7 6 5 4...

Page 468: ... 16 bit timer Note Since the count clock is changed immediately after these bits are updated it is recommend to modify these bits while the 16 bit timer is in stop state bit4 Details Writing 0 Disables the compare clear interrupt Writing 1 Enables the compare clear interrupt bit3 Details Writing 0 Disables the counting operation of the 16 bit timer Writing 1 Enables the counting operation of the 1...

Page 469: ...celled on the SNI0 pin bit1 0 D 1 0 DTTI noise width select bits These bits select the noise width to be cancelled on the DTTI pin bit 7 6 5 4 3 2 1 0 Field S21 S20 S11 S10 S01 S00 D1 D0 Attribute R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 bit7 6 Details Writing 00 4 machine cycle noise Writing 01 8 machine cycle noise Writing 10 16 machine cycle noise Writing 11 32 machine cycl...

Page 470: ...or data transfer OPCUR OPS 2 0 0b000 word access to output data buffer register 0 must be used byte access to either lower register or upper register does not start any transfer operation In order to use the 16 bit reload timer underflow transfer method OPCUR OPS 2 0 0b010 the reload timer should be used in reload mode Software trigger is needed to be used for the startup of the reload timer The 1...

Page 471: ... the timer counter should be disable first by setting the TMEN bit to 0 Modify the CLK 2 0 bits in the 16 bit MPG timer control status register TCSR only when the 16 bit timer is not counting If the values loaded to the 16 bit MPG compare clear register upper CPCUR and the 16 bit MPG compare clear register lower CPCLR are the same as the timer counter value the comparison operation will not be per...

Page 472: ... EQU 007DH Interrupt control register for the waveform sequencer PCSR1 EQU 0FB2H 16 bit PPG cycle setting buffer register PDUT1 EQU 0FB4H 16 bit PPG duty setting buffer register PCNT1 EQU 0044H 16 bit PPG status control register OPCUR EQU 0066H 16 bit MPG output control register upper OPCLR EQU 0067H 16 bit MPG output control register lower OPCR EQU OPCUR 16 bit MPG output control register upper l...

Page 473: ...0 OPDBRL0 write method for data transfer Enable write timing interrupt Clears interrupt flag MOVW A 0009H MOVW OPDBR0 A Sets OPT0 pin as PPG output Sets OPT1 pin as inverted PPG output Starts data transfer SETI Interrupt enable LOOP MOV A 00H Endless loop MOV A 01H JMP LOOP Interrupt program WARI CLRB WTIF Clears interrupt request flag User processing RETI Returns from interrupt CODE ENDS Vector s...

Page 474: ...MB95630H Series 454 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 21 MULTI PULSE GENERATOR 21 8 Sample Program for Multi pulse Generator ...

Page 475: ...DUCTOR LIMITED 455 CHAPTER 22 UART SIO This chapter describes the functions and operations of UART SIO 22 1 Overview 22 2 Configuration 22 3 Channel 22 4 Pins 22 5 Interrupts 22 6 Operations and Setting Procedure Example 22 7 Registers ...

Page 476: ...ouble buffer that allows 2 way full duplex communication The synchronous or asynchronous transfer mode can be selected The optimum baud rate can be selected with the dedicated baud rate generator The data length is variable it can be set to 5 bit to 8 bit when no parity is used or to 6 bit to 9 bit when parity is used See Table 22 1 1 The serial data direction endian can be selected The data trans...

Page 477: ...bbreviations of a product refer to the device data sheet Block Diagram of UART SIO Figure 22 2 1 Block Diagram of UART SIO Dedicated baud rate generator 1 4 Pin Pin Pin Clock selector External clock input UCKn Serial data input UIn Start bit detection Recep tion bit count Parity operation Shift register for reception UART SIO serial input data register UART SIO serial status and data register UART...

Page 478: ...ut serial data output transmission reception and interrupts and to clear the receive error flag UART SIO serial status and data register SSRn This register indicates the transmission reception status and error status of UART SIO UART SIO serial input data register RDRn This register holds the receive data The serial input is converted and then stored in this register UART SIO serial output data re...

Page 479: ...T SIO respectively Table 22 3 1 Pins of UART SIO Pin name Pin function UCKn Clock input output UOn Data output UIn Data input Table 22 3 2 Registers of UART SIO Register abbreviation Corresponding register Name in this manual SMC1n UART SIO serial mode control register 1 SMC2n UART SIO serial mode control register 2 SSRn UART SIO serial status and data register TDRn UART SIO serial output data reg...

Page 480: ... this time do not select the external clock set SMC1n CKS 0 When it is to be used as a UART SIO clock input pin disable the clock output SMC2n SCKE 0 and make sure that it is set as input port by the corresponding port direction register At this time be sure to select the external clock set SMC1n CKS 0 UOn Serial data output pin for UART SIO When the serial data output is enabled SMC2n TXOE 1 it s...

Page 481: ...CPL bit is set to 1 upon completion of transmission of all pieces of transmit data At this time an interrupt request to the interrupt controller occurs when transmission completion interrupt enable bit has been enabled SMC2n TCIE 1 Receive Interrupt If the data is input successfully up to the stop bit the RDRF bit is set to 1 If an overrun error a parity error or a framing error occurs the corresp...

Page 482: ... SIO Initial setup 1 Set the port input DDR 2 Set the interrupt level ILR 3 Set the prescaler PSSRn 4 Set the baud rate BRSRn 5 Select the clock SMC1n CKS 6 Set the operation mode SMC1n MD 7 Enable disable the serial clock output SMC2n SCKE 8 Enable reception SMC2n RXE 1 9 Enable interrupts SMC2n RIE 1 For details of the interrupt level setting register ILR refer to CHAPTER 5 INTERRUPTS in this ha...

Page 483: ...nerator see CHAPTER 23 UART SIO DEDICATED BAUD RATE GENERATOR Figure 22 6 1 Baud Rate Calculation when Using Dedicated Baud Rate Generator Baud rate value Machine clock MCLK bps 4 1 2 4 8 2 255 UART baud rate setting register BRSRn Baud rate setting BRS 7 0 UART prescaler select register PSSRn Prescaler select PSS 1 0 Table 22 6 2 Sample Asynchronous Transfer Rates Based on Dedicated Baud Rate Gen...

Page 484: ... start bit L level and ends with the stop bit H level by performing the specified data bit length transfer with MSB first or LSB first LSB first or MSB first can be selected by the BDS bit in the SMC1n register It becomes H level at the idle state Figure 22 6 2 Transfer Data Format Table 22 6 3 Baud Rate Setting Range in Clock Asynchronous Mode UART PSS 1 0 BRS 7 0 0b00 to 0b11 0x02 2 to 0xFF 255 ...

Page 485: ...t data register RDRn and the next frame of serial data can be received When the RDRn register stores data the receive data register full flag bit SSRn RDRF is set to 1 A receive interrupt occurs the moment the RDRF bit is set to 1 when the receive interrupt enable bit SMC2n RIE contains 1 Received data is read from the RDRn register after each error flag PER OVE FER in the UART SIO serial status a...

Page 486: ...not match the parity polarity bit TDP when the parity control bit PEN contains 1 Framing error FER The framing error bit FER is set to 1 if 1 is not detected at the position of the first stop bit in serial data received in the set character bit length CBL under parity control PEN Note that the stop bit is not checked if it appears at the second bit or later Overrun error OVE Upon completion of rec...

Page 487: ...rent bit is regarded as the start bit The frequency quartered circuit is activated upon detection of the start bit and serial data is input to the reception shift register at intervals of four periods of BRCLK When data is received sampling is performed at three points of the baud rate clock BRCLK and data sampling clock DSCLK and received data is confirmed on a majority basis when two bits out of...

Page 488: ...it data is transferred from the TDRn register to the transmission shift register and the TDRE bit is set to 1 When the transmit interrupt enable bit TIE contains 1 a transmit interrupt occurs if the TDRE bit is set to 1 This allows the next piece of transmit data to be written to the TDRn register by interrupt handling To detect the completion of serial transmission by transmit interrupt set the t...

Page 489: ...ata Register Empty Flag Bit TDRE When TXE Is Switched from 0 to 1 Concurrent transmission and reception In asynchronous clock mode UART transmission and reception can be performed independently Therefore transmission and reception can be performed at the same time or even with transmitting and receiving frames overlapping each other in shifted phases UOn D0 D1 TDRE Transmit interrupt TXE 1 Writing...

Page 490: ...he external clock signal set the SCKE bit to 0 To output the dedicated baud rate generator output as a shift clock signal set the SCKE bit to 1 The serial clock signal is obtained by dividing clock by two which is supplied by the dedicated baud rate generator The baud rate in the SIO mode can be set in the following range For more information about the dedicated baud rate generator also see CHAPTE...

Page 491: ...lock signal is output under control of the output for transmit data When only reception is performed therefore set transmission control TXE 1 to write dummy transmit data to the UART SIO serial output register Refer to the device data sheet for the UCKn clock value Baud rate value Machine clock MCLK bps 2 1 2 4 8 1 256 UART baud rate setting register BRSRn Baud rate setting BRS 7 0 UART prescaler ...

Page 492: ... two procedures can be used Set the transmission operation enable bit TXE to 1 then write transmit data to the UART SIO serial output data register to generate the serial clock signal and start reception Write transmit data to the TDRn register then set the TXE bit to 1 to generate the serial clock signal and start reception SMC1n UART SIO serial mode control register 1 bit7 bit6 bit5 bit4 bit3 bi...

Page 493: ... received data read it from the RDRn register after checking the overrun error flag bit OVE in the UART SIO serial status and data register SSRn When received data is read from the RDRn register the RDRF bit is cleared to 0 Figure 22 6 12 8 bit Reception of Synchronous Clock Mode Operation when receive error occurs When an overrun error OVE 1 occurs received data is not transferred to the RDRn reg...

Page 494: ...er empty flag bit TDRE is set to 1 When the transmit data is written to the TDRn register the TDRE bit is cleared to 0 When serial transmission is started after transmit data is transferred from the TDRn register to the transmission shift register the TDRE bit is set to 1 SMC1n UART SIO serial mode control register 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BDS PEN TDP SBL CBL1 CBL0 CKS MD 1 SMC2n ...

Page 495: ...on completion flag bit SSRn TCPL is set to 1 and a transmission completion interrupt occurs Figure 22 6 15 8 bit Transmission in Synchronous Clock Mode Concurrent transmission and reception When external clock is enabled Transmission and reception can be performed independently of each other Transmission and reception can therefore be performed at the same time or even when their phases are shifte...

Page 496: ...of the UART SIO Table 22 7 1 List of UART SIO Registers Register abbreviation Register name Reference SMC1n UART SIO serial mode control register 1 22 7 1 SMC2n UART SIO serial mode control register 2 22 7 2 SSRn UART SIO serial status and data register 22 7 3 RDRn UART SIO serial input data register 22 7 4 TDRn UART SIO serial output data register 22 7 5 ...

Page 497: ...ol bit This bit controls the stop bit length in clock asynchronous mode UART Note The setting of this bit is only valid for transmission operation in clock asynchronous mode UART In a receive operation regardless of the setting of this bit the UART SIO completes the receive operation when detecting a stop bit one bit and sets the receive data register full flag bit SSRn RDRF to 1 bit 7 6 5 4 3 2 1...

Page 498: ...bit to 1 forcibly disables the output of the UCKn pin The external clock cannot be used in clock asynchronous mode UART bit0 MD Operation mode select bit This bit selects an operation mode from the clock asynchronous mode UART or the clock synchronous mode SIO Note During data transmission or reception do not modify the settings of the UART SIO serial mode control register 1 SMC1n bit3 2 Details W...

Page 499: ...t to 0 the output from the UCKn bit will always be H bit6 TXOE Serial data output enable bite bit This bit controls the output of the serial data pin UOn bit5 RERC Receive error flag clear bit This bit clears the receive error flags The read value of this bit is always 1 bit 7 6 5 4 3 2 1 0 Field SCKE TXOE RERC RXE TXE RIE TCIE TEIE Attribute R W R W R W R W R W R W R W R W Initial value 0 0 1 0 0...

Page 500: ...ata register full flag bit SSRn RDRF or any of the receive error flag bits SSRn PER OVE FER is set to 1 bit1 TCIE Transmission completion interrupt enable bit This bit enables or disables the transmission completion interrupt With this bit set to 1 transmission completion interrupt enabled a transmission completion interrupt is generated immediately after the transmission completion flag bit SSRn ...

Page 501: ...n an overrun error occurs during a receive operation reception Writing 0 to the RERC bit in the SMC2n register clears this bit When an overrun error is detected at the same time as clearing this bit by writing 0 to the RERC bit setting this bit to 1 is given priority bit3 FER Framing error flag bit This bit detects the framing error in receive data This bit is set to 1 when a framing error occurs ...

Page 502: ... and writing 0 to this bit to clear it occur simultaneously the former one is given priority Writing 1 to this bit has no effect on operation bit0 TDRE Transmit data register empty flag bit This bit indicates the state of the UART SIO serial output data register TDRn When transmit data is written to the TDRn register this bit is set to 0 When transmit data is loaded to the shift register for the t...

Page 503: ...ister When received data is set correctly in this register the receive data register full flag bit SSRn RDRF is set to 1 At this time an interrupt occurs if receive interrupt requests have been enabled If an RDRF bit check by the program or using an interruption shows that received data is stored in this register the reading of the content for this register clears the RDRF bit to 0 When the charac...

Page 504: ... transmit data when transmit data empty occurs or the TDRE bit is set to 1 When the character bit length SMC1n CBL 1 0 is set to shorter than eight bits the excess upper bits beyond the set bit length are ignored Note The data in this register cannot be updated when the TDRE bit in UART SIO serial status and data register SSRn is 0 When this register is updated at writing complete the transmission...

Page 505: ...NDUCTOR LIMITED 485 CHAPTER 23 UART SIO DEDICATED BAUD RATE GENERATOR This chapter describes the functions and operations of the dedicated baud rate generator for the UART SIO 23 1 Overview 23 2 Channel 23 3 Operations 23 4 Registers ...

Page 506: ...details refer to the device data sheet In this chapter n in a pin name and a register abbreviation represents the channel number For details of pin names register names and register abbreviations of a product refer to the device data sheet Block Diagram of UART SIO Dedicated Baud Rate Generator Figure 23 1 1 Block Diagram of UART SIO Dedicated Baud Rate Generator Input Clock The UART SIO dedicated...

Page 507: ...d rate generator Channel of UART SIO Dedicated Baud Rate Generator Table 23 2 1 shows the registers of the UART SIO dedicated baud rate generator Table 23 2 1 Registers of Dedicated Baud Rate Generator Register abbreviation Corresponding register Name in this manual PSSRn UART SIO dedicated baud rate generator prescaler select register BRSRn UART SIO dedicated baud rate generator baud rate setting...

Page 508: ...sfer Rates by Baud Rate Generator Machine Clock 10MHz 16MHz 16 25MHz UART SIO Dedicated baud rate generator setting UART internal division Total division ratio PSS BRS 4 Baud rate 10 MHz Total division ratio Baud rate 16 MHz Total division ratio Baud rate 16 25 MHz Total division ratio Prescaler select PSS 1 0 Baud rate counter setting BRS 7 0 1 Setting value 0 0 20 4 80 125000 200000 203125 1 Set...

Page 509: ...s This section describes the registers of the UART SIO dedicated baud rate generator Table 23 4 1 List of UART SIO Baud Rate Generator Registers Register abbreviation Register name Reference PSSRn UART SIO dedicated baud rate generator prescaler select register 23 4 1 BRSRn UART SIO dedicated baud rate generator baud rate setting register 23 4 2 ...

Page 510: ...t on operation bit2 BRGE Baud rate clock output enable bit This bit enables or disables outputting the baud rate clock BRCLK When 1 is written to this bit the value of the BRS 7 0 bits in the BRSRn register is loaded to the 8 bit downcounter and BRCLK to be supplied to the UART SIO is output Writing 0 to this bit stops the output of BRCLK bit1 0 PSS 1 0 Prescaler select bits These bits select a pr...

Page 511: ...ting register BRSRn controls the baud rate settings Register Configuration Register Functions This register sets the cycle of the 8 bit downcounter and can be used to set any baud rate clock BRCLK Stop the UART SIO operation before writing a value to this register In clock asynchronous mode UART do not set BRS 7 0 to 0x00 or 0x01 bit 7 6 5 4 3 2 1 0 Field BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0 At...

Page 512: ...MB95630H Series 492 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 23 UART SIO DEDICATED BAUD RATE GENERATOR 23 4 Registers ...

Page 513: ... I2C BUS INTERFACE This chapter describes functions and operations of the I2 C bus interface 24 1 Overview 24 2 Configuration 24 3 Channel 24 4 Pins 24 5 Interrupts 24 6 Operations and Setting Procedure Example 24 7 Registers 24 8 Notes on Using I2 C Bus Interface ...

Page 514: ...ch device Furthermore the interface establishes a master slave relationship between devices The I2 C bus interface can connect multiple devices provided the bus capacitance does not exceed an upper limit of 400 pF The I2 C bus interface is a true multi master bus with collision detection and a communication control protocol that prevent loss of data even if more than one master attempts to start a...

Page 515: ...etection circuit Arbitration lost detection circuit Slave address comparison circuit IBSRn register IBCR0n register IBCR1n register ICCRn register IAARn register IDDRn register The number of pins and that of channels of the I2 C bus interface vary among products For details refer to the device data sheet In this chapter n in a pin name and a register abbreviation represents the channel number For ...

Page 516: ... Error Sync Start Master ACK enable GC ACK enable Bus busy Repeat start Last bit Transmit receive Arbitration lost detection circuit SDAn line SCLn line First byte I C enable Start stop condition detection circuit ICCRn EN CS2 CS1 CS0 RSC LRB TRX FBT BB IBCR1n Transfer interrupt End 8 5 Machine clock Shift clock edge DMBP CS4 CS3 6 7 8 22 4 2 AAS GCA Slave IDDRn register IAARn register Slave addre...

Page 517: ...ed IBCR0n ALF is set to 1 and the master changes to a slave automatically Slave address comparison circuit The slave address comparison circuit receives the slave address after the start condition to compare it with its own slave address The address is seven bit data followed by a data direction R W bit in the eighth bit position If the received address matches the own slave address the comparison...

Page 518: ...ns and registers on a channel of the I2 C bus interface respectively Table 24 3 1 Pins of I2C Bus Interface Pin name Pin function SDAn I2 C bus interface I O SCLn Table 24 3 2 Registers of I2 C Bus Interface Register abbreviation Corresponding register Name in this manual IBCR0n I2 C bus control register 0 IBCR1n I2C bus control register 1 IBSRn I2C bus status register IDDRn I2 C data register IAA...

Page 519: ...e I2 C bus interface are SDAn and SCLn SDAn pin The SDAn pin is the data I O pin of the I2 C bus interface When the I2C bus interface is enabled ICCRn EN 1 the SDAn pin is automatically set as a data I O pin to function as the SDAn pin SCLn pin The SCLn pin is the serial clock I O pin of the I2 C bus interface When the I2 C bus interface is enabled ICCRn EN 1 the SCLn pin is automatically set as a...

Page 520: ...ansfer is completed the IBCR1n INT bit is set to 1 regardless of the value of the IBCR1n INTE bit Interrupt in response to a bus error When the following conditions are met a bus error is deemed to have occurred and the I2 C bus interface will be stopped When a stop condition is detected in master mode When a start or stop condition is detected during transmission or reception of the first byte Wh...

Page 521: ...st is output to the CPU if the arbitration lost detection interrupt request enable bit has been set to enable IBCR0n ALE 1 Either write 0 to the arbitration lost interrupt request flag bit IBCR0n ALF while the bus is idle or write 0 to the IBCR1n INT bit from the interrupt service routine while the bus is busy to clear the interrupt request When arbitration lost occurs the IBCR0n ALF bit is set to...

Page 522: ...eup function wakes up the MCU upon detection of a start condition from low power consumption mode such as stop or watch mode Setting Procedure Example Below is an example of procedure for setting the I2 C bus interface Initial settings 1 Set the port for input DDR 2 Set the interrupt level ILR 3 Set the slave address IAARn 4 Select the clock and enable I2 C operation ICCRn 5 Enable bus error inter...

Page 523: ...face is a true multi master bus with a collision detection function and arbitration function to prevent data from being lost if more than one master attempts to start data transfer at the same time I2 C Protocol Figure 24 6 1 shows the format required for data transfer Figure 24 6 1 Data Transfer Example The slave address is transmitted after a start condition S is generated This address is seven ...

Page 524: ...h the MSB The address data consists of eight bits the 7 bit slave address and the data transfer direction R W bit bit0 of IDDRn The acknowledgment from the slave is received after the address data is sent SDAn goes to L in the ninth clock cycle and the acknowledge bit from the receiving device is received See Figure 24 6 1 In this case the R W bit IDDRn bit0 is inverted logically and stored in the...

Page 525: ...ed if IBCR1n DACKE 1 In slave mode a data acknowledgment is generated if an address acknowledgment has already been generated and IBCR1n DACKE 1 The received acknowledgment is saved in IBSRn LRB in the ninth SCLn cycle If the data ACK depends on the content of received data such as packet error checking used by the SM bus control the data ACK by setting the data ACK enable bit IBCR1n DACKE after w...

Page 526: ...gment GCA General call address AL Arbitration lost When IBCR1n GACKE 1 ACK is given and IBSRn GCA is set IBCR1n INT is set at 9th SCLn Set IBCR0n INTS 1 IBCR1n INT is set at 9th SCLn Read IBSRn LRB IBCR1n INT is set at 8th SCLn Read IDDRn and control ACK NACK by IBCR1n DACKE To read IBSRn LRB set INTS 0 IBCR1n INT is set at 8th SCLn Read IDDRn and control ACK NACK by IBCR1n DACKE To read IBSRn LRB...

Page 527: ... a master transfer Arbitration occurs on the SDAn line while the SCLn line is at the H level When the send data is 1 and the data on the SDAn line is L at the master this is treated as arbitration lost In this case data output is halted and IBCR0n ALF is set to 1 If this occurs an interrupt is generated if arbitration lost interrupts have been enabled IBCR0n ALE 1 If IBCR0n ALF is set to 1 the mod...

Page 528: ...ns and Setting Procedure Example Figure 24 6 3 Timing Diagram with No Interrupt Generated with IBCR0n ALF 1 L L 1 0 0 SCLn pin or SDAn pin at L level SCLn pin SDAn pin I2C operation enabled ICCRn EN 1 Master mode set IBCR1n MSS 1 Arbitration lost detection bit IBCR0n ALF 1 Bus busy IBSRn BB Interrupt IBCR1n INT ...

Page 529: ...iagram with No Interrupt Generated with IBCR0n ALF 1 If this situation can occur use the following procedure to set up the module from the software 1 Trigger a start condition from the program by setting the IBCR1n MSS bit to 1 2 Check the IBCR0n ALF and IBSRn BB bits in the arbitration lost interrupt If IBCR0n ALF 1 and IBSRn BB 0 clear the IBCR0n ALF bit to 0 If IBCR0n ALF 1 and IBSRn BB 1 clear...

Page 530: ...on lost detected a IBCR1n INT bit interrupt occurs upon detection of IBCR0n ALF 1 Figure 24 6 6 Timing Diagram with Interrupt Generated with IBCR0n ALF 1 Detected Set master mode Set the MSS bit in I2 C bus control register 1 IBCR1n to 1 Enable AL interrupts IBCR0n ALE 1 IBCR0n ALF 1 IBSRn BB 0 YES YES NO NO Normal control Write 0 to IBCR0n ALF to clear AL flag and interrupt Write 0 to IBCR0n ALE ...

Page 531: ...r the MCU wakes up from stop or watch mode so that I2 C operation can restart as soon as possible The wakeup function only applies to the MCU stop and watch modes Figure 24 6 7 Comparison of Normal I2C Operation and Wakeup Operation SDAn SCLn IRQ by IBCR0n WUF Machine Clock 1 2 3 4 5 Set the IBCR0n WUE bit to 1 immediately before entering stop watch mode and make sure that IBSRn BB 0 Set the MCU t...

Page 532: ...ng Procedure Example The following sample flow chart illustrates the wakeup function Figure 24 6 8 Sample Flow Chart 2 NO Go to stop watch mode YES IBCR0n WUE 0 Enable wakeup function by setting IBSRn BB 0 IBSRn BB 0 YES NO Procedure for transition to stop watch mode Write 0 to IBCR0n ALE and clear AL interrupt IBCR0n WUE 1 ...

Page 533: ...egisters of the I2 C bus interface Table 24 7 1 List of I2 C Bus Interface Registers Register abbreviation Register name Reference IBCR0n I2C bus control register 0 24 7 1 IBCR1n I2 C bus control register 1 24 7 2 IBSRn I2 C bus status register 24 7 3 IDDRn I2 C data register 24 7 4 IAARn I2C address register 24 7 5 ICCRn I2C clock control register 24 7 6 ...

Page 534: ...ss data in the same way as during addressing If AACKX 1 and IBSRn FBT 1 when a transfer completion interrupt is generated IBCR1n INT 1 1 might be written to AACKX after addressing as in slave mode Either continue normal communication after setting AACKX to 0 again or restart communication after disabling I2 C operation ICCRn EN 0 bit6 INTS Timing select bit for transfer completion flag bit at data...

Page 535: ...CR1n INT bit to clear the transmission completion flag bit Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit4 ALE Arbitration lost interrupt enable bit This bit enables or disables the arbitration lost interrupt When this bit and the ALF bit are both set to 1 an arbitration lost interrupt request is generated b...

Page 536: ... from occurring immediately after the MCU wakes up after 100 µs assuming that the minimum oscillation stabilization wait time is 100 µs elapses since a wakeup caused by the start of I2C transmission upon detection of the falling edge of SDAn the SCLn must rise in the first cycle and the first bit must be received as data In standby mode of the MCU the status flags state machine and I2C bus output ...

Page 537: ...ed When read by the read modify write RMW type of instruction this bit always returns 1 When this bit is set to 1 the ICCRn EN bit is set to 0 and the I2C bus interface operation is disabled and data transfer is terminated bit6 BEIE Bus error interrupt enable bit This bit enables or disables the bus error interrupt When this bit and the BER bit are both set to 1 a bus error interrupt request is ge...

Page 538: ...occurs during data or address transfer in master mode this bit is cleared to 0 and the operation mode switches to slave mode Notes Do not set this bit to 0 or the SCC bit to 1 at the same time With the INT bit set to 0 an attempt to write 0 to the MSS bit is ignored With the INT bit set to 1 when writing 0 to the MSS bit and writing 0 to the INT bit occur simultaneously writing 0 to the MSS bit is...

Page 539: ...e following two conditions is satisfied this bit is set to 0 0 is written to this bit In master mode a repeated START condition IBCR1n SCC 1 or a STOP condition IBCR1n MSS 0 is generated Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 Writing 0 to clear this bit its value becomes 0 releases the SCLn line and the ...

Page 540: ...earing the interrupt request flag bit IBCR1n BER by writing 0 to it do not update the interrupt request enable bit IBCR1n BEIE at the same time All bits in the IBCR1n register except the BER and BEIE bits are cleared to 0 either when the I2C bus interface operation is disabled ICCRn EN 0 or when a bus error occurs IBCR1n BER 1 ...

Page 541: ... IAARn register In slave mode the slave address matches the address set in the IAARn register but the IBCR0n AACKX bit is set to 1 In slave mode the device receives a general call address but the IBCR1n GACKE bit is set to 0 A STOP condition is detected bit5 Undefined bit The read value of this bit is always 0 Writing a value to this bit has no effect on operation bit 7 6 5 4 3 2 1 0 Field BB RSC ...

Page 542: ...n cycle bit3 TRX Data transfer status bit This bit indicates the data transfer mode This bit is set to 1 when data transfer is executed in transmission mode If one of the following conditions is satisfied this bit is set to 0 In receive mode data transfer is executed The device receives an NACK in slave transmit mode bit2 AAS Addressing detection bit This bit indicates whether the MCU has undergon...

Page 543: ...byte of a general call address bit0 FBT First byte detection bit This bit detects the first byte This bit is set to 1 when a START condition is detected If one of the following conditions is satisfied this bit is set to 0 0 is written to the IBCR1n INT bit In slave mode the slave address does not match the address set in the IAARn register In slave mode the slave address matches the address set in...

Page 544: ...data transfer completion interrupt is cleared writing 0 to the IBCR1n INT bit or when a repeated start condition is generated writing 1 to the IBCR1n SCC bit Each bit of the shift register data is output shifted to the SDAn line Note that writing to this register has no effect on the current data transfer In slave mode however data is transferred to the shift register after the address is determin...

Page 545: ...2C bus interface receives address data from the master and compares it with the value of this register Register Configuration Register Functions bit7 Undefined bit The read value of this bit is always 0 Writing a value to this bit has no effect on operation bit6 0 A 6 0 Address bits These bits set the slave address bit 7 6 5 4 3 2 1 0 Field A6 A5 A4 A3 A2 A1 A0 Attribute R W R W R W R W R W R W R ...

Page 546: ...as no effect on operation bit5 EN I2 C bus interface operation enable bit This bit enables the I2 C bus interface operation Writing 0 to this bit disables the I2 C bus interface operation and clears the following bits to 0 AACKX INTS and WUE bits in the IBCR0n register All bits in the IBCR1n register except the BER and BEIE bits All bits in the IBSRn register Writing 1 to this bit enables the I2C ...

Page 547: ...frequency Fsck is set by the following equation Fsck φ represents the machine clock frequency MCLK Note If the standby mode wakeup function is not used disable the I2 C bus interface operation before making the MCU transit to stop mode or watch mode bit4 3 Details Writing 00 5 Writing 01 6 Writing 10 7 Writing 11 8 bit2 0 Details Writing 000 4 Writing 001 8 Writing 010 22 Writing 011 38 Writing 10...

Page 548: ...INT occur simultaneously the MSS bit is given priority and a STOP condition is generated Conflict between next byte transfer and start condition When writing 1 to IBCR1n SCC and clearing IBCR1n INT occur simultaneously the SCC bit is given priority and a START condition is generated Notes on setting up using software Do not select the repeated START condition IBCR1n SCC 1 or slave mode IBCR1n MSS ...

Page 549: ...the MCU enters stop mode or watch mode To ensure that the I2 C operation can restart immediately after the MCU wakes up from stop mode or watch mode clear write 0 to this bit as soon as possible When a wakeup interrupt request is generated the MCU wakes up after the oscillation stabilization wait time elapses In order to prevent data loss from occurring immediately after the MCU wakes up after 100...

Page 550: ...MB95630H Series 530 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 24 I2 C BUS INTERFACE 24 8 Notes on Using I2 C Bus Interface ...

Page 551: ...ions of the 64 96 160 288 Kbit Dual operation Flash memory 25 1 Overview 25 2 Sector Bank Configuration 25 3 Invoking Flash Memory Automatic Algorithm 25 4 Checking Automatic Algorithm Execution Status 25 5 Programming Erasing Flash Memory 25 6 Operations 25 7 Flash Security 25 8 Registers 25 9 Notes on Using Dual Operation Flash Memory ...

Page 552: ...yte 1 lower bank 2 Kbyte 2 Overview of Dual Operation Flash Memory The following methods can be used to write data into and erase data from the Flash memory Programming erasing using a dedicated serial programmer Programming erasing by program execution Since data can be written into and erased from the Dual operation Flash memory by instructions from the CPU via the Flash memory interface circuit...

Page 553: ...pts Capable of erasing data in specific sectors any combination of sectors Compatible with JEDEC standard commands Number of program erase cycles minimum 100000 Flash read cycle time minimum 1 machine cycle Programming and Erasing Flash Memory Programming data to and reading data from the same bank of the Flash memory cannot be executed simultaneously To program data to or erase data from a bank i...

Page 554: ...esses of each sector are shown in the figure Bank configuration The lower bank of the Flash memory is SA0 and SA1 and the upper bank SA2 Figure 25 2 1 Sector Bank Configuration of Dual Operation Flash Memory Flash memory 8 Kbyte Flash memory 12 Kbyte Flash memory 20 Kbyte Flash memory 36 Kbyte CPU address SA0 2 Kbyte SA0 2 Kbyte SA0 2 Kbyte SA0 2 Kbyte 0x1000 Lower bank 0x17FF SA1 2 Kbyte SA1 2 Kb...

Page 555: ...ress Data Address Data Address Data Read reset 1 0xUXXX 0xF0 Program 4 0xUAAA 0xAA 0xU554 0x55 0xUAAA 0xA0 PA PD Chip erase 6 0xUAAA 0xAA 0xU554 0x55 0xUAAA 0x80 0xUAAA 0xAA 0xU554 0x55 0xUAAA 0x10 Sector erase 6 0xUAAA 0xAA 0xU554 0x55 0xUAAA 0x80 0xUAAA 0xAA 0xU554 0x55 SA 0x30 Unlock bypass entry 3 0xUAAA 0xAA 0xU554 0x55 0xUAAA 0x20 Unlock bypass program 2 0xUXXX 0xA0 PA PD Unlock bypass reset...

Page 556: ...3 1 is not arbitrary but represents the upper four bits bit 15 to bit 12 of an address The chip erase command is accepted only when programming data into all sectors has been enabled The chip erase command is ignored if the bit for any sector in the flash memory sector write control register 0 SWRE0 has been set to 0 to disable programming data to that sector Note on Issuing Commands Do the follow...

Page 557: ...hardware sequence flag can be checked by a read access to the address of a target sector in the Flash memory after a command sequence is set Note that a hardware sequence flag is output only to the bank from which a command has been issued Table 25 4 1 shows the bit allocation of the hardware sequence flags To decide whether a program command a chip erase command or a sector erase command is being...

Page 558: ...ration Programming Programming completed when program address has been specified DQ7 DATA 7 Toggle DATA 6 0 DATA 5 0 DATA 3 0 DATA 2 Chip sector erase Erase completed 0 1 Toggle 1 0 1 1 Toggle 1 Sector erase wait Erase started 0 Toggle 0 0 1 Toggle Erasing sector erase suspended Sector being erased 0 Toggle 0 0 1 Toggle Sector erase suspended Erasing resumed Sector being erased 0 0 Toggle 0 1 Togg...

Page 559: ...ng erased during execution of the chip sector erase algorithm bit7 of Flash memory outputs 0 Bit7 of Flash memory outputs 1 upon completion of chip sector erase At sector erase suspension When read access takes place with a sector erase operation suspended the Flash memory outputs 0 to DQ7 if the read address is the sector being erased If not the Flash memory outputs bit7 DATA 7 of the value read ...

Page 560: ...gorithm Execution Status Note Once the automatic algorithm has been started read access to the specified address is ignored Data reading is allowed after the data polling flag DQ7 is set to 1 Data reading after the end of the automatic algorithm should be performed following read access made to confirm the completion of data polling ...

Page 561: ...sector erase suspension When a read access is made with a sector erase operation suspended the Flash memory outputs 0 if the read address is the sector being erased Otherwise the Flash memory outputs bit6 DATA 6 of the value read from the read address Note When using dual operation Flash memory Flash memory write control program is executed on the Flash memory the toggle bit flag DQ6 cannot be use...

Page 562: ...egardless of whether the automatic algorithm has been running or terminated When the execution timeout flag DQ5 outputs 1 it can be judged that programming fails if flash memory program erase status bit RDY in the flash memory status register FSR is 0 If an attempt is made to write 1 to a Flash memory address holding 0 for example the Flash memory is locked the time limit is exceeded and the execu...

Page 563: ...nd it is ignored until sector erase is terminated If the sector erase timer flag DQ3 is 0 the Flash memory can accept the sector erase command Before writing the sector erase command to the Flash memory make sure that the sector erase timer flag DQ3 is 0 If the flag is 1 the Flash memory may not accept suspending the sector erase command At sector erase suspension When a read access is made with t...

Page 564: ...rase algorithm is being executed the Flash memory outputs bit2 DATA 2 of the value read from a read address of each read access At sector erase suspension With a sector erase operation suspended when read accesses are continuously made to a sector to be erased the Flash memory toggles the output between 1 and 0 whenever a read access is made With a sector erase operation suspended when read access...

Page 565: ...atic algorithm can be invoked by programming the read reset program chip erase sector erase sector erase suspend and sector erase resume command sequence to the Flash memory from the CPU Always write the commands of a command sequence continuously from the CPU to the Flash memory The termination of the automatic algorithm can be checked by the data polling function After the automatic algorithm te...

Page 566: ...nd read reset commands in the command sequence table from the CPU to the Flash memory Since the read reset state is the initial state of the Flash memory the Flash memory always enters this state after power on or the normal termination of a command The read reset state is also regarded as the command input wait state In the read reset state data in the Flash memory can be read by a read access to...

Page 567: ...on timeout flag DQ5 indicates that an error has occurred because the execution time of the automatic algorithm exceeds the programming time specified When data is read in the read reset state the bit data remains 0 To make the bit data return from 0 to 1 erase the Flash memory All commands are ignored during programming During programming if a hardware reset occurs the integrity of data being writ...

Page 568: ...mmand sequence 1 0xUAAA 0xAA 2 0xU554 0x55 3 0xUAAA 0xA0 4 Program address Program data Next address Read internal address Data polling DQ7 Data polling DQ7 Data Data Execution timeout DQ5 1 End of programming 0 Last address YES NO Program error Data Data FSR WRE Enable Flash memory programming SWRE0 Enable disable programming data to a sector Write 0 to disable programming data or 1 to enable pro...

Page 569: ... six bus operations Chip erasing starts at the point when the sixth cycle of programming commands is complete In chip erase the user does not need to program data to the Flash memory before starting erasing data While the automatic erase algorithm is running it automatically writes 0 to all cells in the Flash memory before erasing data Note on Chip Erase The chip erase command is accepted only whe...

Page 570: ...t time elapses after the last sector erase code has been written To erase data from multiple sectors simultaneously input the addresses of sectors to be erased and the erase code in the sixth cycle of the command sequence within 35 µs If the erase code is input after 35 µs elapses it will not be accepted due to the end of the sector erase wait time The sector erase timer flag DQ3 can be used to ch...

Page 571: ... DQ5 End of erasing Erase error 6 Input code 0x30 to erase sector FSR WRE Enable Flash memory erasing FSR WRE Disable Flash memory erasing SWRE0 Enable disable programming data to a sector Write 0 to disable programming data or 1 to enable programming data to a sector Erase command sequence 1 0xUAAA 0xAA 2 0xU554 0x55 3 0xUAAA 0x80 4 0xUAAA 0xAA 5 0xU554 0x55 1 0 DQ3 1 0 Toggle bit DQ6 Data 1 Data...

Page 572: ...ctor erase suspend code 0xB0 is written Specify an address in the sector selected to be erased If an attempt is made to execute the sector erase suspend command again when sector erase has been suspended the new sector erase suspend command input is ignored When a sector erase suspend command is input during the sector erase wait period the sector erase wait time ends immediately the sector erase ...

Page 573: ... in the Flash memory Resuming Sector Erase of Flash Memory To resume suspended sector erase send the sector erase resume command mentioned in the command sequence table from the CPU to the Flash memory The sector erase resume command resumes a sector erase operation suspended by the sector erase suspend command The sector erase resume command is executed by writing erase resume code 0x30 Specify a...

Page 574: ...he normal command state the Flash memory will transit to the unlock bypass state In this state a program command can be executed if the command is input within two cycles as mentioned in Table 25 3 1 Returning from Unlock Bypass State to Normal Command State If an unlock bypass reset command is input in the unlock bypass state the Flash memory will return to the normal command state from the unloc...

Page 575: ...o read interrupt vector data The same data must be copied to SA1 and SA2 before the sector swap enable bit FSR SSEN is set Procedure for Setting Sector Swap Enable Bit FSR SSEN Figure 25 6 1 shows a sample procedure of setting the sector swap enable bit FSR SSEN To modify data in the upper bank it is necessary to set FSR SSEN to 1 While data is being written to the Flash memory modifying the setti...

Page 576: ...n an interrupt occurs during Flash memory programming erasing When two or more program erase routines exist wait for one program erase routine to finish before executing another program erase routine While data is being written to or erased from the Flash memory state transition in the current mode clock mode or standby mode is prohibited Ensure that programming data to or erasing data from the Fl...

Page 577: ...ory address 0xFFFC restricts access to the Flash memory disabling any read write access to the Flash memory from any external pin Once the protection of the Flash memory is enabled the function cannot be unlocked until a chip erase command operation is executed It is advisable to write the protection code at the end of Flash programming to avoid enabling unnecessary protection during writing Once ...

Page 578: ...ibes the registers for the Flash memory Table 25 8 1 List of Flash Memory Registers Register abbreviation Register name Reference FSR2 Flash memory status register 2 25 8 1 FSR Flash memory status register 25 8 2 SWRE0 Flash memory sector write control register 0 25 8 3 FSR3 Flash memory status register 3 25 8 4 FSR4 Flash memory status register 4 25 8 5 ...

Page 579: ...fter Flash memory programming is completed further Flash memory programming erasing is disabled Writing a reset command can make the Flash memory return to the normal command state When Flash memory programming fails FSR3 HANG 1 the PGMEND bit is cleared to 0 Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction ...

Page 580: ...rrupt request is generated when the ERSEND bit is set to 1 provided that generating an interrupt request upon completion of Flash memory sector erase has been enabled FSR2 EEIEN 1 When the ERSEND bit is set to 0 after Flash memory sector erase is completed further Flash memory programming erasing is disabled Writing a reset command can make the Flash memory return to the normal command state When ...

Page 581: ...to the normal command state An interrupt request is generated when the ERSTO bit is set to 1 provided that generating an interrupt request upon failure of Flash memory sector erase has been enabled FSR2 ETIEN 1 Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit1 Details Writing 0 ...

Page 582: ...ation When read by the read modify write RMW type of instruction this bit always returns 1 bit4 RDY Flash memory program erase status bit This bit indicates the program erase status of the Flash memory When the RDY bit is 0 programming data into and erasing data from the Flash memory are disabled The read reset command sector erase suspend command can still be accepted when the RDY bit is 0 When p...

Page 583: ...the Flash memory set FSR WRE to 1 to enable programming data to the Flash memory and set the flash memory sector write control register 0 SWRE0 according to the Flash memory sector into which data is to be written When Flash memory programming is disabled FSR WRE 0 no write access to a sector in the Flash memory can be executed even though it has been enabled by setting a bit corresponding to that...

Page 584: ...te SA0 2 Kbyte SA2 4 Kbyte SA2 2 Kbyte SA1 2 Kbyte SA2 2 Kbyte 0x1000 0x17FF 0x1800 0x2000 0x8000 0x7FFF 0x8000 0x7FFF 0xF000 0xEFFF 0x1FFF 0xF7FF 0xF800 0xFFFF FSR SSEN 0 FSR SSEN 1 0x1000 0x17FF 0x1800 0x2000 0x1FFF 0xF7FF 0xF800 0xFFFF MB95F632H F632K MB95F633H F633K MB95F634H F634K CPU address CPU address Interrupt vector Lower bank Upper bank 0x8000 0x7FFF 0xC000 0xBFFF Lower bank Upper bank ...

Page 585: ...ot be programmed into the sector corresponding to that bit To re program the data execute a reset operation Only write data to SWRE0 by the byte Setting the bits in SWRE0 using the bit manipulation instruction is prohibited Register Configuration Register Functions bit7 3 Reserved bits Always set these bits to 0 bit2 0 SA2E SA1E SA0E Programming function setup bits These bits are used to set the f...

Page 586: ... SAxE bit corresponding to that sector is set to 1 Figure 25 8 2 Examples of Flash Memory Program disabled Program enabled and Spurious Programming Prevention States Depending on Flash Memory Sector Write Control Register 0 SWRE0 Note on Setting SWRE0 Register To program data to or erase data from SA0 0x1000 to 0x17FF or SA1 0x1800 to 0x1FFF of the Flash memory when FSR SSEN is 0 set both SA0E and...

Page 587: ...e machine clock MCLK cycle is longer than 1 µs Use this bit with the machine clock MCLK cycle shorter than 1 s bit0 HANG Flash memory hang up status bit This bit indicates whether the Flash memory has malfunctioned or not bit 7 6 5 4 3 2 1 0 Field CERS ESPS SERS PGMS HANG Attribute R R R R R Initial value 0 0 0 X X X X X bit4 Details Reading 0 Indicates that Flash memory chip erase has been comple...

Page 588: ... normal command state When Flash memory chip erase fails FSR3 HANG 1 this bit is cleared to 0 Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit5 CTIEN CERTO interrupt enable bit This bit enables or disables the generation of interrupt requests triggered by the failure of Flash me...

Page 589: ...the CERTO bit is set to 1 after Flash memory chip erase is completed further Flash memory programming erasing is disabled Writing a reset command can make the Flash memory return to the normal command state Writing 0 to this bit clears it Writing 1 to this bit has no effect on operation When read by the read modify write RMW type of instruction this bit always returns 1 bit3 0 Undefined bits Their...

Page 590: ...e 25 8 3 FSR2 PGMEND during Flash Memory Programming Figure 25 8 4 FSR2 PGMTO when Flash Memory Programming Failed Figure 25 8 5 FSR2 ERSEND during Flash Memory Sector Erase FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 PGMEND Program command Program END FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 PGMTO Program command Program timeout Reset command FSR RDY FSR3 PGMS FSR3 SERS FSR3 ...

Page 591: ...emory Programming Failed with Flash Memory Sector Erase Suspended FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 ERSTO Sector erase command Sector erase timeout Reset command FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 PGMEND FSR2 ERSEND Sector erase command Sector erase suspend command Program command Sector erase suspend resume command FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 hA...

Page 592: ... Resumed Figure 25 8 11 FSR4 CERTO when Chip Erase Failed FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 ERSEND Sector erase command Sector erase suspend command Reset command read No effect Sector erase suspend resume command FSR RDY FSR3 PGMS FSR3 SERS FSR3 ESPS FSR3 HANG FSR2 PGMEND FSR2 ERSTO Sector erase command Sector erase suspend command Program command Sector erase suspend resume co...

Page 593: ...02 00009 1v0 E FUJITSU SEMICONDUCTOR LIMITED 573 CHAPTER 25 DUAL OPERATION FLASH MEMORY 25 8 Registers Figure 25 8 12 FSR4 CEREND during Chip Erase FSR RDY FSR3 CERS FSR3 SERS FSR4 CEREND Chip erase command Chip erase end ...

Page 594: ...8 13 Sample Procedure for Enabling Disabling Flash Memory Programming Start of programming Read internal address Programming command sequence 1 0xUAAA 0xAA 2 0xU554 0x55 3 0xUAAA 0xA0 4 Program address Program data Next address Read internal address FSR WRE Enable Flash memory programming SWRE0 Enable disable programming data to a sector Write 0 to disable programming data or 1 to enable programmi...

Page 595: ...he WRE bit to 1 to enable Flash memory programming and then set the bit in the SWRE0 register corresponding to a sector to which data is to be written When Flash memory programming is disabled by setting the WRE bit to 0 no write access to a sector in the Flash memory can be executed even though it has been enabled by setting a bit corresponding to that sector in the SWRE0 register to 1 ...

Page 596: ... Flash memory The Flash memory write control program is executed on the Flash memory the toggle bit flag DQ6 cannot be used to check the operating state of the Flash memory during programming or erasing Therefore use the data polling flag DQ7 to check the internal operating state of the Flash memory after programming data to the Flash memory or erasing data from the Flash memory as shown in the ex...

Page 597: ...TED 577 CHAPTER 26 NON VOLATILE REGISTER NVR INTERFACE This chapter describes the functions and operations of the NVR interface 26 1 Overview 26 2 Configuration 26 3 Registers 26 4 Notes on Main CR Clock Trimming 26 5 Notes on Using NVR Interface ...

Page 598: ... Functions of the NVR interface are as follows 1 The NVR interface retrieves all data from the NVR Flash area and stores it in the registers in the NVR I O area after a reset See Figure 26 1 1 and Figure 26 2 1 2 The NVR interface enables the user to know the value of the initial CR trimming setting 3 The NVR interface enables the user to select the hardware watchdog timer or software watchdog tim...

Page 599: ... ID WDTH and WDTL Main CR Temperature Dependent Adjustment CRTDA Block Diagram of NVR Interface Figure 26 2 1 Block Diagram of NVR Interface CRTH4 CRTH3 CRTH2 CRTH1 CRTH0 CRTL4 CRTL3 CRTL2 CRTL1 CRTL0 5 5 4 MHz Main CR clock CRTH CRTL CRTDA4 CRTDA3 CRTDA2 CRTDA1 CRTDA0 5 CRTDA Main CR clock oscillator WDTH7 WDTH6 WDTH5 WDTH4 WDTH3 Equal to 0xA5 Equal to 0x96 Equal to 0x97 WDTH2 WDTH1 WDTH0 WDTL7 W...

Page 600: ...e NVR interface Table 26 3 1 List of NVR Interface Registers Register abbreviation Register name Reference CRTH Main CR clock trimming register upper 26 3 1 CRTL Main CR clock trimming register lower 26 3 2 CRTDA Main CR clock temperature dependent adjustment register 26 3 3 WDTH Watchdog timer selection ID register upper 26 3 4 WDTL Watchdog timer selection ID register lower 26 3 4 ...

Page 601: ...oaded from the Flash address 0xFFBC bit4 0 after a reset Their initial values are determined by the pre loaded values in the NVR Flash area Coarse trimming modifies the main CR clock frequency with a bigger step Increasing the coarse trimming value decreases the main CR clock frequency See 26 4 Notes on Main CR Clock Trimming and 26 5 Notes on Using NVR Interface for details of main CR clock trimm...

Page 602: ...loaded from the Flash address 0xFFBD bit4 0 after a reset Their initial values are determined by the pre loaded values in the NVR Flash area Fine trimming modifies the main CR clock frequency with a smaller step Increasing the fine trimming value decreases the main CR clock frequency See 26 4 Notes on Main CR Clock Trimming and 26 5 Notes on Using NVR Interface for details of main CR clock trimmin...

Page 603: ... are determined by the pre load values in the NVR Flash area Temperature dependent adjustment maintains the accuracy of the main CR output frequency within a temperature range It works in combination with the coarse trimming settings in the CRTH register and the fine trimming settings in the CRTL register In addition increasing the value of the CRTDA register decreases the main CR clock frequency ...

Page 604: ...by the pre loaded values in the NVR Flash area These bits cannot be modified while the CPU is running See Table 26 3 2 for watchdog timer selection See 26 5 Notes on Using NVR Interface for notes on writing NVR values WDTH bit 7 6 5 4 3 2 1 0 Field WDTH7 WDTH6 WDTH5 WDTH4 WDTH3 WDTH2 WDTH1 WDTH0 Attribute R W R W R W R W R W R W R W R W Initial value X X X X X X X X WDTL bit 7 6 5 4 3 2 1 0 Field ...

Page 605: ...t main CR clock trimming value and the 5 bit temperature dependent adjustment value will be loaded from the NVR Flash area to registers in the NVR I O area Table 26 4 1 shows the step size of main CR clock trimming Table 26 4 1 Step Size of Main CR Clock Trimming Function Coarse trimming value CRTH 4 0 Fine trimming value CRTL 4 0 To achieve the minimum frequency 0b11111 0b11111 To achieve the max...

Page 606: ...A 4 0 0b10000 0 x 1 C 0 x 1 F 0 x 1 F 0 x 1 F 0 x 1 9 0 x 1 F 0 x 1 6 0 x 1 F 0 x 1 3 0 x 1 F 0 x 1 0 0 x 1 F 0 x 0 D 0 x 1 F 0 x 0 A 0 x 1 F 0 x 0 7 0 x 1 F 0 x 0 4 0 x 1 F 0 x 0 1 0 x 1 F 0 x 1 C 0 x 0 0 0 x 1 F 0 x 0 0 0 x 1 9 0 x 0 0 0 x 1 6 0 x 0 0 0 x 1 3 0 x 0 0 0 x 1 0 0 x 0 0 0 x 0 D 0 x 0 0 0 x 0 A 0 x 0 0 0 x 0 7 0 x 0 0 0 x 0 4 0 x 0 0 0 x 0 1 0 x 0 0 10000 9000 8000 7000 6000 5000 400...

Page 607: ...ckup of data in CRTH CRTH 4 0 CRTL CRTL 4 0 and CRTDA CRTDA 4 0 2 Erase the Flash 3 Restore all data in CRTH CRTH 4 0 CRTL CRTL 4 0 and CRTDA CRTDA 4 0 to the NVR Flash area If there is new data in CRTH CRTH 4 0 CRTL CRTL 4 0 and CRTDA CRTDA 4 0 the Flash writer will program the new data to the NVR Flash area 2 The trimming value has been preset before this device is shipped If the preset trimming...

Page 608: ...MB95630H Series 588 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E CHAPTER 26 NON VOLATILE REGISTER NVR INTERFACE 26 5 Notes on Using NVR Interface ...

Page 609: ...CONDUCTOR LIMITED 589 CHAPTER 27 COMPARATOR This chapter describes the functions and operations of the comparator 27 1 Overview 27 2 Configuration 27 3 Pins 27 4 Interrupt 27 5 Operations and Setting Procedure Example 27 6 Register ...

Page 610: ... of Comparator The function of the comparator is to monitor the two analog input voltages and compare them Using the voltage of the non inverting analog input positive input as a reference voltage the comparator outputs H if the voltage of the inverting analog input voltage negative input is lower than the reference voltage otherwise it outputs L In addition upon detection of a rising edge or fall...

Page 611: ...rator Figure 27 2 1 Block Diagram of Comparator VCID Edge detection circuit Comparator IE IF OS CMPn_P CMPn_N From an external pin From an external pin VCOE PD Comparator control register CMR0C Internal bus Interrupt request CMPn_O To an external pin To the external pin control circuit Enable CMPn_O output via an external pin To the external pin control circuit When CMPn_P and CMPn_N analog input ...

Page 612: ...ising edge or falling edge of comparator output the edge detection circuit automatically raises an interrupt flag CMR0C IF Comparator control register CMR0C This register has the following functions To power up or power down the comparator CMR0C PD To enable or disable comparator output CMR0C VCOE To enable or disable comparator analog input CMR0C VCID Except in stop mode watch mode or time base t...

Page 613: ...tion describes the pins of the comparator Pins of Comparator Table 27 3 1shows details of the pins of the comparator Table 27 3 1 Pins of Comparator Pin name Pin function CMPn_P Comparator non inverting analog input positive input CMPn_N Comparator inverting analog input negative input CMPn_O Comparator digital output ...

Page 614: ...able 27 4 1 shows details of the output edge detection interrupt Note In stop mode watch mode or time base timer mode the edge detection circuit stops operating and the output edge detection interrupt flag bit IF in the comparator control register CMR0C will not be updated even if the comparator has been turned on Table 27 4 1 Details of Output Edge Detection Interrupt Item Details Interrupt gener...

Page 615: ...arting to operate Note Before activating the comparator set the IE bit in the CMR0C register to 0 in advance in order to avoid any unexpected interrupt generated due to the comparator being unstable at its startup Setting Procedure Example Below is an example of procedure for setting the comparator Initial settings 1 Disable the comparator interrupt request CMR0C IE 0 2 Activate the comparator acc...

Page 616: ... MN702 00009 1v0 E CHAPTER 27 COMPARATOR 27 6 Register 27 6 Register This section describes the register of the comparator Table 27 6 1 List of Comparator Register Register abbreviation Register name Reference CMR0C Comparator control register 27 6 1 ...

Page 617: ...tion bit5 OS Output status bit This bit indicates the output status of the comparator Note This bit is not updated in stop mode watch mode or time base timer mode When the PD bit is set to 1 to power down the comparator the OS bit becomes 0 bit4 IF Output edge detection interrupt flag bit This bit detects the output rising edge and the output falling edge of the comparator With the comparator in o...

Page 618: ... Note When the analog input function is enabled by this bit the general purpose I O port function of the pin possessing the analog input function is disabled bit1 VCOE Comparator output enable bit This bit enables or disables comparator output bit0 PD Comparator power down control bit This bit powers up or down the comparator bit3 Details Writing 0 Disables the interrupt request of the comparator ...

Page 619: ...LIMITED 599 CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER This chapter describes the functions and operations of the system configuration controller called the controller in this chapter 28 1 Overview 28 2 Register 28 3 Notes on Using Controller ...

Page 620: ...YSC Selecting the general purpose I O port reset function for the PF2 RST pin Enabling disabling reset output for the RST pin Selecting the general purpose I O port oscillation function for the PG1 X0A SNI1 pin and that for the PG2 X1A SNI2 pin Selecting the general purpose I O port oscillation function for the PF0 X0 pin and that for the PF1 X1 pin Selecting the EC0 input pin as the external coun...

Page 621: ...601 CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER 28 2 Register 28 2 Register This section describes the register of the controller Table 28 2 1 List of Voltage Comparator Register Register abbreviation Register name Reference SYSC System configuration register 28 2 1 ...

Page 622: ...in clock oscillation enable bit SYCC2 MOSCE Writing 1 to this bit makes the PF0 and PF1 pins function as general purpose I O ports bit5 4 Reserved bits Always set these bits to 0 bit3 EC0SL EC0 clock select bit This bit selects the external count clock input pin EC0 for the 8 16 bit composite timer Before using the EC0 input function enable the external count clock input of the 8 16 bit composite ...

Page 623: ...of the PF2 RST pin and disables the general purpose I O port function Set bit2 in the PDRF register to 1 before modifying this bit Note To keep the reset input output function after the reset SYSC RSTEN and SYSC RSTOE are initialized to 1 after the power is switched on They are not initialized by any other type of reset When the reset input output functions have to be used in a system it is strong...

Page 624: ...ontroller This section provides notes on using the controller Notes on Using Controller Setting PPGSEL to 0 when using the multi pulse generator MPG While the MPG is in use P62 to P67 are being used as MPG output ports In this situation if it is necessary to use the PPG function set the PPGSEL bit to 0 to switch the PPG output pins to P10 P11 and P13 to P16 pins ...

Page 625: ...UJITSU SEMICONDUCTOR LIMITED 605 APPENDIX This section provides an overview of instructions A 1 Addressing A 2 Special Instruction A 3 Bit Manipulation Instructions SETB CLRB A 4 F2 MC 8FX Instructions A 5 Instruction Map ...

Page 626: ...instruction map Figure A 1 Instruction Code and Instruction Map The instruction is classified into following four types forwarding system operation system branch system and others There are various methods of addressing and ten kinds of addressing can be selected by the selection and the operand specification of the instruction This provides with the bit operation instruction and can execute the r...

Page 627: ...h T Temporary accumulator Whether 8 bit length or 16 bit length is decided by the instruction used TH Upper 8 bit of temporary accumulator 8 bit length TL Lower 8 bit of temporary accumulator 8 bit length IX Index register 16 bit length EP Extra pointer 16 bit length PC Program counter 16 bit length SP Stack pointer 16 bit length PS Program status 16 bit length dr Either of accumulator or index re...

Page 628: ...es for the instruction Operation It shows the operations for the instruction TL TH AH They show the change auto forwarding from A to T in the content when each TL TH and AH instruction is executed The sign in the column indicates the followings respectively No change dH upper 8 bits of the data described in operation AL and AH the contents become those of the immediately preceding instruction s AL...

Page 629: ... In this addressing when the operand address is 0x00 to 0x7F it is accessed into 0x0000 to 0x007F Moreover when the operand address is 0x80 to 0xFF the access can be mapped in 0x0080 to 0x047F by setting of direct bank pointer DP Figure A 1 1 shows an example Figure A 1 1 Example of Direct Addressing Extended addressing This is used when the area of the entire 64 Kbyte is accessed by addressing sh...

Page 630: ...ressing the content of the first operand is sign extended and added to IX index register to the resulting address Figure A 1 4 shows an example Figure A 1 4 Example of Index Addressing Pointer addressing This is used when the area of the entire 64 Kbyte is accessed by addressing shown EP in the instruction table In this addressing the content of EP extra pointer is assumed to be an address Figure ...

Page 631: ...en branching to the subroutine address registered in the table with the addressing shown vct in the instruction table In this addressing information on vct is contained in the operation code and the address of the table is created using the combinations shown in Table A 1 1 Figure A 1 8 shows an example Figure A 1 8 Example of Vector Addressing 0x0156 MOV A R 6 0xAB A 0xAB 0b01010 RP MOV A 56H 0x5...

Page 632: ... PC Figure A 1 9 shows an example Figure A 1 9 Example of Relative Addressing In this example by jumping to the address where the operation code of BNE is stored it results in an infinite loop Inherent addressing This is used when doing the operation decided by the operation code with the addressing that does not have the operand in the instruction table In this addressing the operation depends on...

Page 633: ... it for the reckless driving judgment Figure A 2 2 shows a summary of the instruction Figure A 2 2 MOVW A PC When this instruction is executed the content of A reaches the same value as the address where the following instruction is stored rather than the address where operation code of this instruction is stored Therefore in Figure A 2 2 the value 0x1234 stored in A corresponds to the address whe...

Page 634: ...ss contained in A before execution of the instruction After the instruction is executed A becomes the address that follows the address where the operation code of XCHW A PC is stored This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine Figure A 2 5 shows a summary of the instruction Figure A 2 5 XCHW A PC When this instruction is e...

Page 635: ... A 2 7 shows a summary of the instruction Figure A 2 7 Example of Executing CALLV 3 After the CALLV vct instruction is executed the contents of PC saved on the stack area are the address of the operation code of the next instruction rather than the address of the operation code of CALLV vct Accordingly Figure A 2 7 shows that the value saved in the stack 0x1232 and 0x1233 is 0x5679 which is the ad...

Page 636: ...verview A 2 Special Instruction Table A 2 1 Vector Table Vector use call instruction Vector table address Upper Lower CALLV 7 0xFFCE 0xFFCF CALLV 6 0xFFCC 0xFFCD CALLV 5 0xFFCA 0xFFCB CALLV 4 0xFFC8 0xFFC9 CALLV 3 0xFFC6 0xFFC7 CALLV 2 0xFFC4 0xFFC5 CALLV 1 0xFFC2 0xFFC3 CALLV 0 0xFFC0 0xFFC1 ...

Page 637: ... request flag bits the read destination differs between a normal read operation and a read modify write operation I O ports during a bit manipulation From some I O ports an I O pin value is read during a normal read operation while a port data register value is read during a bit manipulation This prevents the other port data register bits from being changed accidentally regardless of the I O direc...

Page 638: ...1 AL D5 18 MOVW IX off A 4 2 IX off AH IX off 1 AL D6 19 MOVW ext A 5 3 ext AH ext 1 AL D4 20 MOVW EP A 3 1 EP AH EP 1 AL D7 21 MOVW EP A 1 1 EP A E3 22 MOVW A d16 3 3 A d16 AL AH dH E4 23 MOVW A dir 4 2 AH dir AL dir 1 AL AH dH C5 24 MOVW A IX off 4 2 AH IX off AL IX off 1 AL AH dH C6 25 MOVW A ext 5 3 AH ext AL ext 1 AL AH dH C4 26 MOVW A A 3 1 AH A AL A 1 AL AH dH 93 27 MOVW A EP 3 1 AH EP AL E...

Page 639: ...A 1 1 AL TL AL C 32 15 INC Ri 3 1 Ri Ri 1 C8 to CF 16 INCW EP 1 1 EP EP 1 C3 17 INCW IX 1 1 IX IX 1 C2 18 INCW A 1 1 A A 1 dH C0 19 DEC Ri 3 1 Ri Ri 1 D8 to DF 20 DECW EP 1 1 EP EP 1 D3 21 DECW IX 1 1 IX IX 1 D2 22 DECW A 1 1 A A 1 dH D0 23 MULU A 8 1 A AL TL dH 01 24 DIVU A 17 1 A T A MOD T dL dH dH 11 25 ANDW A 1 1 A A T dH R 63 26 ORW A 1 1 A A T dH R 73 27 XORW A 1 1 A A T dH R 53 28 CMP A 1 1...

Page 640: ...h 4 2 if C 0 then PC PC rel F8 BNC BHS rel at no branch 2 5 BN rel at branch 4 2 if N 1 then PC PC rel FB BN rel at no branch 2 6 BP rel at branch 4 2 if N 0 then PC PC rel FA BP rel at no branch 2 7 BLT rel at branch 4 2 if V N 1 then PC PC rel FF BLT rel at no branch 2 8 BGE rel at branch 4 2 if V N 0 then PC PC rel FE BGE rel at no branch 2 9 BBC dir b rel 5 3 if dir b 0 then PC PC rel B0 to B7...

Page 641: ...D A R7 MOVW A PS MOVW PS A OR A ORW A OR A d8 OR A dir OR A IX d OR A EP OR A R0 OR A R1 OR A R2 OR A R3 OR A R4 OR A R5 OR A R6 OR A R7 CLRI CLRC MOV A T MOVW A T DAA MOV dir d8 MOV IX d d8 MOV EP d8 MOV R0 d8 MOV R1 d8 MOV R2 d8 MOV R3 d8 MOV R4 d8 MOV R5 d8 MOV R6 d8 MOV R7 d8 SETI SETC MOV A A MOVW A A DAS CMP dir d8 CMP IX d d8 CMP EP d8 CMP R0 d8 CMP R1 d8 CMP R2 d8 CMP R3 d8 CMP R4 d8 CMP R...

Page 642: ...MB95630H Series 622 FUJITSU SEMICONDUCTOR LIMITED MN702 00009 1v0 E APPENDIX A Instruction Overview A 5 Instruction Map ...

Page 643: ...1v0 E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL 8 BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL February 2012 the first edition Published FUJITSU SEMICONDUCTOR LIMITED Edited Sales Promotion Department ...

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