EDR-5000
IM02602007E
Name
Description
Logic.LE76.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE76.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE77.Gate Out
Signal: Output of the logic gate
Logic.LE77.Timer Out
Signal: Timer Output
Logic.LE77.Out
Signal: Latched Output (Q)
Logic.LE77.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE77.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE77.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE78.Gate Out
Signal: Output of the logic gate
Logic.LE78.Timer Out
Signal: Timer Output
Logic.LE78.Out
Signal: Latched Output (Q)
Logic.LE78.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE78.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE78.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE78.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE78.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE78.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE79.Gate Out
Signal: Output of the logic gate
Logic.LE79.Timer Out
Signal: Timer Output
Logic.LE79.Out
Signal: Latched Output (Q)
Logic.LE79.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE79.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE79.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE79.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE79.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE79.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE80.Gate Out
Signal: Output of the logic gate
Logic.LE80.Timer Out
Signal: Timer Output
Logic.LE80.Out
Signal: Latched Output (Q)
Logic.LE80.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE80.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE80.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE80.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE80.Gate In4-I
State of the module input: Assignment of the Input Signal
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