EDR-5000
IM02602007E
Name
Description
Logic.LE43.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE44.Gate Out
Signal: Output of the logic gate
Logic.LE44.Timer Out
Signal: Timer Output
Logic.LE44.Out
Signal: Latched Output (Q)
Logic.LE44.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE44.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE44.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE44.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE44.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE44.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE45.Gate Out
Signal: Output of the logic gate
Logic.LE45.Timer Out
Signal: Timer Output
Logic.LE45.Out
Signal: Latched Output (Q)
Logic.LE45.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE45.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE46.Gate Out
Signal: Output of the logic gate
Logic.LE46.Timer Out
Signal: Timer Output
Logic.LE46.Out
Signal: Latched Output (Q)
Logic.LE46.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE46.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE47.Gate Out
Signal: Output of the logic gate
Logic.LE47.Timer Out
Signal: Timer Output
Logic.LE47.Out
Signal: Latched Output (Q)
Logic.LE47.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE47.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Reset Latch-I
State of the module input: Reset Signal for the Latching
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