EDR-5000
IM02602007E
Name
Description
Logic.LE72.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE72.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE72.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE73.Gate Out
Signal: Output of the logic gate
Logic.LE73.Timer Out
Signal: Timer Output
Logic.LE73.Out
Signal: Latched Output (Q)
Logic.LE73.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE73.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE73.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE73.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE73.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE73.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE74.Gate Out
Signal: Output of the logic gate
Logic.LE74.Timer Out
Signal: Timer Output
Logic.LE74.Out
Signal: Latched Output (Q)
Logic.LE74.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE74.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE74.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE75.Gate Out
Signal: Output of the logic gate
Logic.LE75.Timer Out
Signal: Timer Output
Logic.LE75.Out
Signal: Latched Output (Q)
Logic.LE75.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE75.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE75.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE76.Gate Out
Signal: Output of the logic gate
Logic.LE76.Timer Out
Signal: Timer Output
Logic.LE76.Out
Signal: Latched Output (Q)
Logic.LE76.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE76.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE76.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE76.Gate In3-I
State of the module input: Assignment of the Input Signal
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