Data General AViiON 5000 Series, Customer Documentation

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Assigning VME Data Bus and Interrupt Priorities
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Introduction to Interrupt Priority
Any board on a VMEbus can interrupt the host to gain attention. A controller
usually wants the host’s attention because it has finished a command and needs to
communicate this information, along with completion status, back to the processor
that initiated the action. Even though interrupts are usually related to command
management, a controller can request the host’s attention whenever it has a reason
to do so. The returned interrupt status will indicate to the host what type of service
the board requires.
Interrupt requests are usually less frequent than requests for use of the data bus.
However, the ability of a controller to gain access to host services, when required,
may be as important to system performance as the ability to transfer data on
demand.
The VMEbus provides a two–dimensional interrupt priority scheme similar to that
previously described for prioritized DTB arbitration. The higher order hierarchy is
controlled by any one of seven interrupt request lines, IRQ1 through IRQ7. IRQ7
has the highest priority and IRQ1 the lowest. Each controller on the bus is assigned
to drive one of the seven request lines.
Once a host receives one or more interrupt requests, it acknowledges the highest
priority interrupt request line first. If two or more controllers on the bus have
requests at the same priority level, the one closest to the interrupt handler (slot 1)
receives service first.
DG/UX defines what the IRQ priority level will be on all VMEbus controllers Data
General sells for use in AViiON computer systems. If you suspect that the VMEbus
interrupt priority settings are causing a system problem, or if you are installing a
non–DGC VME controller and you require information on setting the interrupt
priority level, contact your Data General Customer Support Center.
For a detail description of the VMEbus interrupt priority system, refer to the
Motorola publication, The VMEbus Specification, revision C.1, or the ANSI/IEEE
specification 1014–1987.
End of Appendix