Cmsemicon CMS80F731 Series, Reference Manual

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/
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Rev.
1.00
CMS80F731x Reference Manual
Note:
1.
If the WDT in CONFIG is configured as: ENABLE, the WDT is always enabled, regardless of the state of the WDTRE
control bit. And the overflow reset function of WDT is forced on.
2.
If WDT in CONFIG is configured as: SOFTWARE CONTROL, WDTRE can be enabled or disabled using the WDTRE
control bit.
Modify the sequence of instructions required by WDCON (no other instructions can be inserted in the middle):
MOV
TA,#0AAH
MOV
TA,#055H
ORL
WDCON,#01H
8.2.2
Watchdog Overflow Control Register CKCON
0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CKCON WTS2 WTS1 WTS0 T1M T0M -- -- --
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 1 1 1
Bit7~Bit5
WTS<2:0>: WDT overflow time selection bits;
000=
2
17
*Tsys;
001=
2
18
*Tsys;
010=
2
19
*Tsys;
011=
2
20
*Tsys;
100=
2
21
*Tsys
101=
2
22
*Tsys;
110= 2
24
*Tsys;
111=
2
26
*Tsys.
Bit4
T1M: Timer1's clock source select bit;
0= Fsys/12;
1= Fsys/4.
Bit3
T0M: Clock source select bit of Timer0;
0= Fsys/12;
1= Fsys/4.
Bit2~Bit0
--
Reserved, must be 1.